Abstract: To generate an accurate frequency standard in an integrated circuit, it is proposed to activate a reference oscillator at certain time intervals and to calibrate the local oscillator. For this purpose, a calibration circuit is provided, which determines the clock ratio between the internal clock and the reference clock. The clock ratio determined is used for programming a frequency divider. The calibration circuit is particularly suitable for being used in mobile radio devices.

Abstract: A blank oscillator 300? is prepared for each office, and control data is written into this blank oscillator 300?, thereby manufacturing an oscillator 300. Upon receiving an order from a user terminal 10, a business center server 100 selects the most suitable office for the delivery of the oscillator and sends the data to the office. A data writing apparatus 200 installed in this office generates control data based on the data, and writes the control data into the blank oscillator 300?, thereby manufacturing the oscillator 300.

Abstract: A phase lock for a synthesizer phase reference oscillator that is used in conjunction with a conventional DDS circuit to synthesize an RF output frequency includes a second DDS circuit that is added with a reference increment value as an input to provide a phase offset frequency. A frequency/phase comparator compares a frequency reference oscillator output with the phase offset frequency to generate a control signal for phase locking the phase reference oscillator to the frequency reference oscillator. To determine the correct value for the reference increment value, a switch is provided between the frequency/phase comparator and the phase reference oscillator and the control signal is input to an analog-to-digital converter. During a “turn on” procedure the resulting digitized control signal is observed by a control system as the reference increment value is adjusted until a slow ramp, positive or negative, in the control signal is observed.

Abstract: A frequency synthesizer (100) that may have reduced spurious noise caused by a voltage controlled oscillator (VCO) (4) output sneaking into an input side of a phase comparison circuit (1) has been disclosed. A beat frequency component that may be generated by mixing of a portion of a VCO output sneaking into an input side of a phase comparison circuit (1) through a reference signal (REF) or a comparison signal (SIG) may be shifted to a high frequency region by providing a modulator circuit (7) on a reference signal side or a comparison signal side. Thus, a low pass filter circuit (3) may provide attenuation to the spurious noise. In this way, spurious noise in the VCO output may be reduced.

Abstract: A PLL (Phase-Locked Loop)-controlled oscillator has a temperature-compensated crystal oscillator having a quartz crystal unit, an oscillating circuit connected to the crystal unit, and a temperature compensating mechanism for generating a temperature compensating voltage for compensating for frequency vs. temperature characteristics of the crystal unit, and a voltage-controlled oscillator having an LC oscillating circuit, for being controlled by a PLL using the temperature-compensated crystal oscillator as a reference signal source. The temperature-compensated crystal oscillator has circuit components except for the crystal unit, the circuit components and the voltage-controlled oscillator being integrated in a one-chip IC. The one-chip IC and the crystal unit are integrally combined with each other in the PLL-controlled oscillator.

Abstract: An debug and emulation system includes a target device embodied in a single integrated circuit. The target device includes a function clock circuit and an operation circuit operating in synchronism with the function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The trace trigger circuit and the FIFO input operate on the function clock. The FIFO output and the trace port operate on the oscillator clock. Thus the trace may operate all on the function clock or be split between the function clock and the reference clock. The trace data is sensed in synchronism with the oscillator clock. The emulator is coupled to the target device to control the clock selection.

Abstract: A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.

Abstract: An AFC circuit compensates for an error of the oscillation frequency of a detecting oscillator based on a detection signal from a detector circuit. The detector circuit generates the detection signal at a timing tied to the oscillation frequency of said detecting oscillator. The AFC circuit has a frequency error determining circuit; a reference oscillator, a frequency error/control voltage conversion circuit; a PLL (phase lock loop) circuit; and a detecting frequency computing circuit. The reference oscillator is connected to provide an oscillator input to said PLL, and the PLL is connected to provide a control voltage to said detecting oscillator. The detecting oscillator is responsive to the control voltage for controlling the oscillation frequency thereof. The AFC circuit controls the oscillation frequency of the detecting oscillator based on the frequency error value so as to vary the oscillation frequency used as a sampling frequency of the detector circuit.

Abstract: A method and a device for reducing cycle slips resulting from frequency hops in a wireless communication device. In the method, a first signal pulse is received, which first signal pulse is either said reference signal pulse or said signal pulse to be compared, a second signal pulse is received, which second signal pulse is from another source than said first signal pulse, a control voltage is generated for controlling a voltage controlled oscillator in response to a phase difference between said first received and said second received signal pulses. At a time instant between the reception of said first and said second signal pulses, a constant voltage is added to said control voltage on receiving additionally one signal pulse, which is the same type as said first signal pulse. After receiving said second signal pulse, said constant voltage is removed from said control voltage on receiving at least one signal pulse, which is the same type as said second signal pulse.

Abstract: A phase-lock loop for preventing frequency drift and jitter problems is disclosed. A phase comparator compares an input signal and a feedback signal, and outputs a control voltage according to phase difference therebetween. A voltage-controlled oscillator outputs a plurality of multiple phase oscillating signals according to the control voltage. A phase swallower receives a plurality of multiple phase oscillating signals, and generates a phase swallow signal. The phase swallow signal is formed by adding or removing one phase in the oscillating signal per predetermined number of clocks. An output frequency divider divides the frequency of the phase swallow signal so as to generate a desired output signal.

Abstract: A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector and compares the absolute magnitude of the error signal to a first threshold signal corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter which continues counting so long as the error signal remains below the magnitude threshold value. The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.

Abstract: A frequency synchronous apparatus includes a switch, frequency division circuit, phase comparison circuit, frequency adjustment and calculation circuit, memory, conversion circuit, and voltage-controlled oscillator. The switch selects either one of a highly stable clock output and a reference clock output in accordance with a mode switching signal. The frequency division circuit divides the frequency of the synchronous clock. The phase comparison circuit detects the phase difference between an output clock from the frequency division circuit and an output clock from the switch, and outputs a phase difference value. The frequency adjustment and calculation circuit performs synchronous control so as to adjust the phase difference value output from the phase comparison circuit to 0, and outputs a synchronous control value at this time. The memory holds the synchronous control value output from the frequency adjustment and calculation circuit.

Abstract: A clock signal generating device is described, having an oscillator and a PLL connected downstream thereof. The clock signal generating device is distinguished by the fact that a phase shifting device is provided between the oscillator and the PLL. This phase shifting device can temporally shift the edges of the signal output by the oscillator to a variable extent, and feeds the resultant signal to the PLL as an input signal. Such a clock signal generating device makes it possible to realize a spread spectrum oscillator which is constructed in a simple manner and can be made small.

Abstract: A high-resolution DDS coupled to a phase-locked-loop (PLL) is provided that tracks the output of the DDS. The output of the PLL is provided to a synthesizer that scales the frequency from the PLL to the desired output frequency. When used to track the output of a DDS at a substantially fixed frequency, the PLL provides an output also at a substantially fixed frequency. The frequency translation of this PLL is chosen such that it allows the DDS to operate at an output frequency range that is spectrally pure. This DDS frequency range is determined either through analysis or found empirically. Once the PLL is ‘locked’ onto the output of the DDS, the output spectrum is filtered by the loop-filter of the PLL, and thus provides a very narrow bandpass filtering effect. If the DDS frequency is changed, the PLL provides a gradual change to the new frequency, thereby providing a gradual phase change through the transition.

Abstract: By supplying a control voltage that corresponds to the phase difference between an output signal of a temperature-compensated crystal oscillator (TCXO 1) and a signal obtained by dividing an output signal of a voltage-controlled SAW oscillator (VCSO 4) using the SAW resonator to the VCSO 4, the frequency of the output signal of the VCSO 4 is controlled so as to be constant over a wide temperature range.

Abstract: In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator.

Abstract: A phase locked loop (PLL) frequency synthesizer generates a high frequency signal by generating an output signal from a voltage controlled oscillator of a primary phase locked loop (PLL) circuit. The voltage controlled oscillator output is programmably divided with a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency. An external reference signal used for the primary phase locked loop circuit is isolated by generating a voltage controlled, clean reference signal and filtering and synchronizing the clean reference signal with the external reference signal within a secondary phase locked loop circuit to produce the reference signal output to the primary phase locked loop circuit.

Abstract: A method and apparatus for synchronizing clocks is provided that is flexible and compensates for process, voltage, and temperature (PVT) variations and other timing differences between two devices. The present invention includes producing an up-converted clock from a system clock, the up-converted clock having a frequency that is a multiple of the frequency of the system clock, producing an aligned clock from a data-aligned clock from a first device and a counter clock from a second device, producing a de-jittered clock, selecting a first reference clock to send to the first device from the up-converted clock, the aligned clock and the de-jittered clock, and selecting a second reference clock to send to the second device from the up-converted clock, the aligned clock and the de-jittered clock.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a plurality of output clock signals and a first control signal in response to a reference clock signal and a feedback signal. The second circuit may be configured to select one of the plurality of output clock signals as the feedback signal in response to the first control signal.

Abstract: A PLL-type frequency synthesizer (10) in which a loop filter (24) state is recorded during an earlier hop to a given frequency then assigned back to the loop filter (24) during a subsequent hop to the same frequency is disclosed. The state is recorded through an A/D converter (48) and assigned through a D/A converter (60). Offset and linearity error is compensated in a compensation circuit (54) so that the state subsequently assigned to the loop filter (24) accurately matches the state that was previously measured for recording. Reference frequency and output signal dividers (16, 40) are both immediately initialized at a hop boundary (82) so that the signals compared by a phase comparator (20) are forced into a phase-matched condition.

Abstract: An input reference timing signal oscillator of a phase-locked loop has a computer algorithm which adaptively models the multiple frequencies of an oscillator following a training period. The oscillator is part of a phase-locked loop and the oscillation frequency thereof is controlled in response to the phase detector output. The computer algorithm processes the control signal applied to the oscillator. The computer algorithm updates the characteristics of the model relating to the aging and temperature of the oscillator, using for example, a Kalman filter as an adaptive filter. By the algorithm, the subsequent model predicts the future frequency state of the oscillator on which it was trained. The predicted frequency of the model functions as a reference to correct the frequency of the oscillator in the event that no input reference timing signal is available. With the model updating algorithm, oscillators of low stability performance may be used as cellular base station reference oscillator.

Abstract: A phase-locked loop system configured to cause an output signal to tend toward a desired output frequency. The phase-locked loop system includes a charge pump system and an oscillator operatively coupled with the charge pump system. The charge pump system is configured to selectively effect proportional control over the output signal by producing a correcting pulse having a duration and applying the correcting pulse to a proportional control path of the phase-locked loop system. The charge pump system includes a correcting circuit configured to store a correcting charge corresponding to the correcting pulse, and then output the correcting charge over a period of time that is greater than the duration of the correcting pulse. Other configurations of the phase-locked loop system employ programmable current mirrors, and other structures and methods, to reduce charge pump current within the phase-locked loop.

Abstract: A frequency synthesizer, a multi-channel carrier generator, and a transceiver, as well as a method for generating a sub-carrier frequency are described.

Abstract: A phase locked loop (PLL) for reducing electromagnetic interference (EMI) is provided. The PLL is not sensitive to a manufacturing process, consumes less power, occupies a small layout space, and can flexibly control a modulation frequency and a modulation rate flexibly. The PLL for reducing the EMI controls the signals having a phase difference, which is n-times (where n is an integer) the basic delay time of the output signals from a voltage controlled oscillator (VCO), and determines the modulation rate. Then, the PLL repeats the procedure during the cycle of a pre-defined modulation frequency. The PLL for reducing the EMI not only reduces the EMI, but also does not require a ROM. Therefore, the layout space can be reduced and broad frequency ranges can be obtained. In addition, since the phase difference of the output signals of the VCO is controlled by logic circuits, the PLL is insensitive to changes in the manufacturing process.

Abstract: A periodic controlled realignment of the ring oscillator VCO in a phase locked loop is used to effect phase correction in a CMOS phase locked loop. A realignment to a buffered version of the reference signal is conducted periodically, at a time when an edge of the VCO waveform would ideally coincide with an edge in the reference signal. A preferred embodiment CMOS phase locked loop of the invention uses a ring oscillator voltage controlled oscillator. A divide by M circuit is driven by an output of the voltage controlled oscillator. A control voltage circuit accepts a reference signal and a signal from the divide by M circuit, and produces a control voltage proportional to a phase difference between the output of the voltage controlled oscillator and the reference signal to control the voltage controlled oscillator.

Abstract: A frequency synthesis method using a phase locked loop including a phase comparator. The method includes switching from a fractional frequency division operating mode to an integer frequency division operating mode after a time or time-delay for stabilizing operation of the loop has elapsed. The method is characterized in that it consists of effecting the operating mode switching by masking or eliminating a portion of the pulses of a reference signal (Sref) and a comparison signal (Scomp) before they are applied to inputs of the phase comparator (3).

Abstract: In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e.g., phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.

Abstract: A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. A further parameter can also be used to divide the output frequency of the phase locked loop circuit to supply a specified output frequency. The oscillators can be manufactured as generic programmable crystal oscillators without regard for output frequency and then quickly programmed to produce customer-specified output frequencies with a high degree of accuracy.

Abstract: A frequency-adjustable oscillator suitable for digital signal clock synchronization comprises a crystal oscillator circuit for generating a driving signal and having a voltage-variable control input for adjusting a frequency of the driving signal, a phase detector circuit for generating a phase offset signal, a filter which operates on the phase offset signal to produce a VCO control signal, a voltage controlled oscillator circuit operably linked to the filter and responsive to the VCO control signal for generating an analog controlled-frequency signal, a frequency divider circuit for generating a reduced frequency feedback signal in response to the controlled-frequency signal, and a sinewave-to-logic level translator circuit for generating a digital output signal having substantially the same frequency as the controlled-frequency signal. The crystal oscillator circuit includes a discrete varactor responsive to the control input and a fundamental mode AT-cut quartz resonator.

Abstract: An oscillator 10 with a noise reduction function has a memory 80 that memorizes modulation data DM for performing the spread spectrum modulation input from an output terminal fout, a modulation signal output circuit 60 that generates a modulation signal SM from the modulation data DM memorized in the memory 80, and a mixer 53 that overlays the modulation signal SM on the control voltage VC of a voltage control oscillator (VCO) 54 of a PLL circuit 50, and it becomes possible to output a spread spectrum modulated output signal CLv under a specification desired by a user by memorizing in the memory 80 the modulation data DM that corresponds to the spread spectrum modulation the user tries to set.

Abstract: A spurious-free fractional-N frequency synthesizer circuit is disclosed. The synthesizer circuit includes a multi-phase network circuit operative to provide output signals that are at least a 1/(2n+1)) fractional version of the input signal. The synthesizer circuit includes a phase lock loop (PLL) circuit, with the multi-phase network circuit being coupled to the negative feedback loop of the PLL. The multi-phase network circuit includes a smoothing circuit that removes any jitter present at the output of the PLL.

Abstract: Systems and methods are disclosed for recovering a clock or time reference for A/V systems. One method comprises receiving at least one input time reference generated using a first clock and generating, using a second clock asynchronous to the first clock, at least one time reference value representative of the at least one input time reference. The method further comprises outputting the generated time reference value used by the A/V system.

Abstract: A frequency detector includes a slicer to receive and slice a phase error against a compare threshold value. The slicer generates a symbol based on the phase error sliced against the compare threshold value. A symbol counter is provided to increment a symbol count if the symbol generated is the same as a last symbol. A logic circuit compares the symbol count with a symbol count limit if the symbol is different from the last symbol. The logic circuit increments a high counter and clears a low counter if the symbol count is less than the symbol count limit. The logic circuit increments the low counter and clears the high counter if the symbol count is greater than the symbol count limit. A combinational logic circuit is provided to generate a high frequency jitter true signal or a high frequency jitter false signal based on at least one of the symbol count, the high counter, and the low counter.

Abstract: A transmission mixer (10) has a local input port (10LO) supplied with a local signal, an intermediate input port (10in) supplied with an input signal having an input frequency (fin) a first output port (10out1) for producing a first output signal having a first output frequency (fout1), and a second output port (10out2) for producing a second output signal having a second output frequency (fout2). The first and the second output ports (10out1, 10out2) are connected to first and second loads (LD1, LD2), respectively. The first load (LD1) is that where impedance-matching is made at the first output frequency (fout1) while the second load (LD2) is that where impedance-matching is made at the second output frequency (fout2).

Abstract: An error-suppression signal measurement system and method therefor is provided. The system transmits a test signal from a first probe, through a device under test, and into a second probe. The probes extract normalization signals from reference signals therein, exchange specific ones of the normalization signals, and combine the normalization signals with data signals derived from the test signal to form receiver signals. The probes propagate the receiver signals to a receiver, where the signals are gain-ranged, digitized, normalized, and compensated for phase-noise.

Abstract: A circuit for controlling a phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock includes frequency dividers with selectable divisors for the reference and feedback signals, and a phase detector having a charge pump output circuit with selectable output current ranges. During acquisition of phase lock by the PLL, the divisors for the reference and feedback signal frequency dividers are increased by the same factor, and the charge pump current range is increased by the same ratio. As a result, the reference rate is decreased as the charge pump current range is increased simultaneously by the same ratio. Meanwhile, the linear loop bandwidth and phase margin remain substantially constant.

Abstract: In order to shorten the transient recovery duration, the phase-locked loop has a voltage-controlled oscillator providing an oscillator signal to a first frequency divider. The first frequency divider divides the frequency of the oscillator signal, generates a first divider output signal therefrom, and passes it to a phase comparator during the transient recovery duration of the phase-locked loop. Furthermore, a unit is provided, which, after the transient recovery duration of the phase-looped loop, divides the frequency of the first divider output signal and passes it to the phase comparator. The phase comparator compares the first divider output signal with a first reference signal during the transient recovery duration. The phase comparator compares the divided divider output signal with a second reference signal after the transient recovery duration. The output of the phase comparator is connected to the voltage-controlled oscillator via a controllable charge pump.

Abstract: Feedback methods and systems are provided to achieve rapid switching of oscillator frequencies without compromising operational feedback loop bandwidths that filter out spurious tones and phase noise to thereby enhance loop spectral and noise performance. The methods respond to frequency changes in a reference signal by providing an open-loop drive current to drive a feedback signal towards the reference signal. The drive current is terminated and the feedback control loop closed when the feedback signal is within a predetermined acquisition range of the reference signal. Preferably, the closed loop is initially configured with a first feedback bandwidth and is subsequently reconfigured with a second steady-state feedback bandwidth that is less than the first feedback bandwidth.

Abstract: A frequency synthesizer, a multi-channel carrier generator, and a transceiver, as well as a method for generating a sub-carrier frequency are described. The frequency synthesizer includes two directly-connected, sequential chains of flip-flops, the first chain having N flip-flops, and the second chain having M flip-flops. The first chain of N flip-flops is clocked by a reference frequency input. Each chain provides a clocked output to an optional duty-cycle recovery circuit, which is in turn coupled to a frequency-update module. There is a sub-threshold low-pass filter included in the frequency-update module which feeds into an oscillator, providing, in turn, the generated frequency as an input to the second chain of M flip-flops, and a sub-carrier frequency output.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a plurality of output clock signals in response to a reference clock signal and a feedback signal. The second circuit may be configured to select one of the plurality of output clock signals as the feedback signal in response to a first control signal. The first control signal may be configured to minimize a difference in delay between the plurality of output clock signals.

Abstract: A dual band voltage controlled oscillator that has low phase noise. The oscillator includes two voltage controlled oscillators that are each coupled to a tank circuit for adjusting the output frequency. One voltage controlled oscillator operates at a low frequency and one operates at a high frequency. Both voltage controlled oscillators are coupled to a combiner circuit that provides the oscillator output signal. A low frequency bandstop filter is coupled to the output of the second voltage controlled oscillator. The low frequency bandstop filter operates so as to reject the low frequency.

Abstract: A circuit and method for assuring rapid initiation of resonant oscillation of an electromechanically oscillatory system driven by phase lock loop circuits. An open loop starting signal commences driving of the object at a starting frequency above the resonant frequency. The starting signal reduces the drive frequency until the resonant frequency of the system is reached and the starting signal is removed.

Abstract: A clock recovery circuit for recovering clock signals from one of a plurality of input reference signals, includes an acquisition phase locked loop (PLL) for each input. The acquisition PLL having phase comparator for comparing the phase of an input signal to a feedback signal, and first and second digital controlled oscillators (DCOs) receiving an input from the phase comparator. The first DCO of the acquisition PLL is in a feedback loop to supply an input to the phase comparator and the second DCO of the acquisition PLL has a control input to introduce a phase offset therein relative to said the DCO of the acquisition PLL and provides an output for the acquisition PLL. An output PLL has a phase comparator selectively connectable to the output of each of the acquisition PLLs. The output PLL has a first DCO providing an output for the circuit and a second DCO in a feedback loop providing a feedback signal to the phase comparator of the output PLL.

Abstract: To generate an accurate frequency standard in an integrated circuit, it is proposed to activate a reference oscillator at certain time intervals and to calibrate the local oscillator. For this purpose, a calibration circuit is provided, which determines the clock ratio between the internal clock and the reference clock. The clock ratio determined is used for programming a frequency divider. The calibration circuit is particularly suitable for being used in mobile radio devices.

Abstract: A phase-lock loop is formed by a voltage-controlled oscillator, a local optical pulse source, an optical branching device for branching the locally generated optical pulse stream from the local optical pulse source, a harmonic component local generation part for locally generating a harmonic component electrical signal from the one of two branched locally generated optical pulse streams, and a phase comparison part for comparing the phases of the locally generated harmonic component electrical signal and an incoming signal component electrical signal generated from an incoming optical signal pulse stream and for supplying the voltage-controlled oscillator with a control voltage corresponding to the phase difference between the two input electrical signals. The other branched output from the optical branching device is output as a locally generated optical pulse stream bit-phase synchronized with the incoming optical signal pulse stream.

Abstract: The high frequency oscillator comprises a reference oscillator, a phase-locked loop circuit with a phase frequency detector, a charge pump, a ring oscillator and a divider, the reference oscillator being coupled to the phase frequency detector for frequency control. The ring oscillator is a symmetrical delay cell oscillator containing two amplifiers with a dual output stage for providing I/Q output signal generation. The reference oscillator works in the range of 1.25-1.5 GHz and is a Colpitts type digital controlled frequency synthesizer with an external tank circuit for providing a low phase noise, and the dividing factor of the divider is four for providing a tuned output range of 5 to 6 GHz. The phase-locked loop circuit is integrated together with the reference oscillator into an integrated circuit, using advantageously a BICMOS Silicon/Germanium process, which is well suited for RF applications.

Abstract: Feedback control loop systems are provided that enhance output-signal switching times without degrading other loop performance parameters. The systems reduce “kick-back” voltages that are generated in a loop filter by drive currents which rapidly drive a control loop oscillator to a loop acquisition range. This reduction reduces a frequency step in the oscillator output signal which would otherwise have to be driven to eliminate the frequency step with a consequent increase in the output-signal switching time. Structures are provided that reduce the kick-back voltage to thereby enhance output-signal switching times.

Abstract: The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, the convergence time required for frequency detection of a frequency detection circuit is short and wrong operation of the frequency detection circuit with a control signal is less likely to occur. A clock generator produces, based on an oscillation frequency clock of a VCO, a first clock signal of the same phase, a second clock signal having a phase delayed by 90 degrees from that of the first clock signal, and a third clock signal having a phase delayed by 45 degrees from that of the first clock signal. A phase detection circuit performs phase control based on the phase difference between the third clock signal and an input signal, and a frequency detection circuit fetches the first and second clock signals in synchronism with the input signal and performs frequency control based on the fetched signals.

Abstract: This invention is a remotely controllable clock circuit embodied in a single integrated circuit device. The clock circuit includes at least one externally writable clock control register, a reference clock input, a controllable oscillator circuit, a pre-scalar circuit and a comparison circuit. The comparison circuit controlling the frequency of the controllable oscillator circuit to achieve a frequency match between a pre-scaled reference clock signal and a pre-scaled oscillator clock signal. The pre-scale divide factors are stored in respective fields in the clock control register. The clock control register may be memory mapped into a device memory space, accessed via an indirect access register or accessed via a serial scan chain. A trace first-in-first-out buffer has an input for trace data operating under the function clock signal of the operating circuits and an output operating under the oscillator clock signal.

Abstract: An optoelectronic phase locked loop for clock recovery in high-speed optical time division multiplexed systems. The optoelectronic phase locked loop includes a balanced photodetector through which the polarity ambiguity in error signal is resolved and the cancellation of laser noise enabling clock recovery with low timing jitter. The optoelectronic phase locked loop also includes an electroabsorption modulator as a phase detector, a lowpass filter, a variable controlled oscillator, a power divider and an amplifer.