Abstract: A monolithically integratable display apparatus for receiving a picture signal having frames of video information and horizontal and vertical synchronizing components includes a matrix of display cells arranged in an array of M rows by N columns. Display cells in the matrix are individually addressable by row and column signals so as to receive the video information in the picture signal in response thereto. A first shift circuit coupled to the matrix provides the row signals in response to a first clocking signal and a data signal. A second shift circuit coupled to the matrix provides the column signals in response to a second clocking signal. A first clock circuit, such as a phase locked loop, receives the horizontal synchronizing component of the picture signal and produces the second clocking signal in response thereto. A synchronizing detector circuit receives the vertical synchronizing component of the picture signal and produces the data signal in response thereto.

Abstract: An automatic phase control apparatus for controlling the frequency of a sine wave produced from a variable frequency oscillator to be equal to that of the carrier wave of the extracted chrominance signal. A phase difference detector 4 detects a phase difference between the sine wave and the carrier wave. The detected phase difference is integrated to obtain an integrated value which is applied to the frequency oscillator for determining the oscillation frequency. A deviation detector is provided for detecting a deviation of the integrated value with respect to an expected frequency control data calculated by a calculator. When the deviation is greater than a predetermined range, the integrated value is replaced with the calculated data.

Abstract: A sync detecting apparatus and method thereof in an error correction technique employed for transmitting highly-reliable information even under poor channel environment in a transmission system of a high definition television (HDTV) includes a first sync detector for comparing a signal transmitted from a receiver with a previously-recognized reference signal to detect a sync signal and rotated amount thereof, a rotation compensator for compensating the rotated amount of the signal detected in the first sync detector, and a second sync detector for accurately detecting the synchronization in accordance with periodicity of the sync signal in case an error included an output signal from the rotation compensator, thereby effectively detecting the sync signal from the signal received into the receiver of the HDTV for performing interleave/deinterleave of the error correction technique as well as compensating the rotation of the signal.

Abstract: An analog image signal is converted into a digital image signal which is in turn subjected to various types of processing procedures. The resulting digital image data is added to synchronizing data having the same range of data change as that of the image data to generate image data containing the synchronizing data. This image data is then converted into an analog image signal. An offset signal is applied to the analog image signal to adjust the voltage level of the synchronizing signal for obtaining an image signal containing a correct synchronizing signal.

Abstract: A digital clamp combines a digitized luminance signal with a DC offset to clamp the back porch portions of the luminance signal to a predetermined IRE level. The clamp generates a reference signal having successive values indicative of successive IRE levels of the back porch portions prior to being clamped. A summer generates successive slice level values indicative of successive averages of the reference signal values and a fixed value. A limiter restricts the successive slice level values to a range of slice levels. A comparator generates a composite synchronizing signal by comparing the luminance signal to the successive slice level values, as limited.

Abstract: An apparatus for generating a clock signal phase-locked to a sync signal of a video signal. The apparatus comprises an error detector for detecting a phase error between the sync signal of the digitized video signal and a comparison signal produced internally; a clock signal generator whose oscillation frequency is variably controlled in response to the output of the error detector; a counter for counting the output of the clock signal generator; and a circuit for producing the comparison signal in response to the count value of the counter. The phase error is detected by integrating the level data of the digitized video signal, and the output of the error detector is replaced with a fixed value when the comparison signal has a predetermined phase. The apparatus is capable of preventing occurrence of a great phase error even at a head switching time or during the vertical blanking interval, so that mislock is preventable and a pull-in action can be executed fast.

Abstract: Apparatus for developing synchronization of an intermediate layer of signal such as the transport or multiplex layer of a multi-layered compressed video signal, includes at the encoding end of the system apparatus for including a time stamp reference, such as a count value from a modulo K counter, and provision for a differential time stamp related to time stamps of a further compressed signal or differential transit times of respective transport packets. Flags are included in transport packets of signal to indicate the presence or absence of the time stamps or differential time stamps. At the receiving end of the system, circuitry examines respective packets for the condition of the flags to locate specific information such as the time stamps and differential time stamps. A counter is responsive to a controlled receiver clock signal and the count value of this counter is sampled at the arrival of transport packets including a flag indicating the presence of a time stamp.

Abstract: For cell multiplexing an original video signal and an original audio signal which are encoded into an encoded video signal and an encoded audio signal, a buffer unit buffers the encoded video signal for read out by a control unit as video data of a common data length. The video data and the encoded audio signal are supplied to processors for inserting additional information, such as a header, therein for production of video and audio cells, which are multiplexed by a cell multiplexer into a cell multiplexed video and audio signal. Preferably, the buffer unit comprises a video buffer for buffering the encoded video signal for read out as read video data, a delay detector for detecting a delay needed to produce the read out data, and a delay information multiplexer for multiplexing, on each read out datum for production of the read out data, delay information indicative of the delay.

Abstract: A cable ready television receiver includes a set back decoder that communicates with the microprocessor in the television receiver via its own microprocessor. A synchronous demodulator in the television receiver is operated normally for unscrambled television signals and is operated to quadrature demodulate scrambled television signals. The quadrature demodulation develops only high frequency video, modulated chroma, FM modulated audio and DC. The demodulator output is applied to the audio circuit and to the AGC circuit in the television receiver. A descrambler in the decoder develops the video signal for application to the video circuitry in the television receiver.

Abstract: A data segment sync signal detector for an HDTV is disclosed including a segment accumulator for separating data corresponding to a segment sync signal from a composite baseband data signal by using a composite baseband data signal of the present segment to a composite baseband data signal of a previously input segment; a quantizer for comparing the output signal of the segment accumulator with predetermined threshold values so as to output level values in a predetermined number of bits, corresponding to a plurality of fixed symbol streams, that is, segment sync signal data; and a segment sync signal pattern detector for detecting the pattern of segment sync signal from the level values expressed in the predetermined number of bits output from the quantizer, thereby obtaining the phase information for respective segments and making respective segment phase pulses according to the phase information.

Abstract: A digital clock generation system provides both a digital composite clock and a digital component clock synchronized with an input synchronization video signal. The digital composite clock is generated from the burst portion of the input synchronization video signal, and the digital component clock is synthesized from the digital composite clock. A frame timing pulse is generated at regular intervals from the composite sync of the input video signal for resetting the digital component clock to establish a defined phase relationship between the digital composite and component clocks according to an offset constant.

Abstract: An integrated circuit device for processing an image signal has an inexpensive structure and an excellent signal processing characteristic. The integrated circuit device (3) formed on one integrated circuit substrate comprises a switch circuit (4), a separator circuit (8) and preamp circuits (5) to (7). The separator circuit (8) has an input terminal which has an input impedance which is sufficiently higher than an output impedance of the switch circuit (4). Receiving an output of the switch circuit (4) at such an input terminal, the separator circuit (8) filters off high-frequency components including the maximum frequency of the image signal and outputs signal components which belong to a frequency band which is related to a synchronization signal. The preamp circuits (5) to (7) amplify and output image signals which are outputted by the switch circuit (4).

Abstract: A first clamp circuit clamps a tip of a synchronization signal of input video signal in accordance with a synchronization signal generated from a synchronization signal generator and outputs a clamped video signal. A level detector detects a level of a tip of a synchronization signal of the clamped video signal. A converter converts the detected level to a reference level signal so that the greater the detected level becomes, the smaller the reference level signal becomes. A second clamp circuit clamps the tip of the synchronization signal of the clamped video signal to the reference level signal and outputs an output video signal. Thus, the second clamp circuit compensates a remaining sag component included in the input video signal accurately.

Abstract: A clamp signal generation-control circuit includes a clamp signal controller for discriminating the existence of a sync on green signal and a separate sync signal supplied from a video card to a monitor to output a control signal according to the discrimination, and a clamp signal generator for automatically changing a generated point of the clamp signal, and a method for controlling the circuit is also provided. The generated point of the clamp signal supplied to the monitor is controlled to automatically shift the clamping position of a video signal, thereby preventing malfunction caused by a nonprofessional user's manipulation, abnormal picture display or the generation of a segment phenomenon. The circuit is adoptable to monitors supplied with various kinds of sync signals.

Abstract: An external color frame is synchronized with a local color frame without producing a pixel position error. A frame synchronizer synchronizes a frame from an external television signal with that of a local television signal. A wide screen oriented high definition television signal is used as the external television signal, the image quality of which is improved by adding a support signal to the main screen signal. A memory is provided to receive and store the external television signal and the external signal is read from the memory after a predetermined time passes when the frame difference between the external and local television signals is at least one frame. In this instance, only the support signal in the readout of the external television signal is corrected by a low pass filter in order to match the pixel position of the support signal to that of the main screen signal.

Abstract: A free running frequency alignment method in a video display having a sync generator comprising a first oscillator having a first frequency and a second oscillator having a second frequency. The first oscillator is phase modulated by the second oscillator which has a free running frequency different from a standard frequency. The free running frequency of the first oscillator is to be controllably aligned to the standard frequency by a method comprising the steps of applying a frequency determining initial control value to the first oscillator and measuring an average free running frequency responsive to the initial control value. An absolute difference frequency is calculated between the average frequency and the standard frequency. The absolute difference frequency is tested for a frequency value less than a predetermined value which signifies an aligned condition. If the difference frequency is less than the predetermined value the alignment is complete.

Abstract: Apparatus for developing synchronization of an intermediate layer of signal such as the transport or multiplex layer of a multi-layered compressed video signal, includes at the encoding end of the system apparatus for including a time stamp reference, such as a count value from a modulo K counter, and provision for a differential time stamp which may be updated by the transit times of respective (e.g., multiplexing) circuits as the signal transits such circuits. At the receiving end of the system a counter is responsive to a controlled receiver clock signal and the count value of this counter is sampled at the arrival of the time stamps embedded in the transport layer. The time stamps and the differential time stamps are retrieved from the signal and combined to form a corrected time stamp. The differences of successive sampled count values of the receiver counter are compared with the differences of corresponding successive corrected time stamps to provide a signal to control the receiver clock signal.

Abstract: To generate a dot clock for a liquid crystal display device from a horizontal sync signal with reduced skew, a phase locked loop (PLL) is divided into three functional parts. The first part generates a particular frequency by supplying voltage from a latch type DAC (digital/analog converter) to a VCO (voltage controller oscillator). A horizontal sync signal is estimated from the dot clock signal that is finally generated and the output value of the DAC is increased or decreased in accordance with the difference between this estimated horizontal sync signal and the actual horizontal sync signal. This increase or decrease correction is made at, for example, the vertical sync timing. The second part achieves synchronization. A signal corresponding to the phase error between the actual horizontal sync signal and the dot clock signal is added to the signal from the DAC to control the phase of the dot clock.

Abstract: In a system which encodes video data in response to an encoding clock, transmits the encoded video data with an encoder clock signal representing the encoding clock frequency, and decodes the video data in response to a decoding clock, system clock accuracy is maintained by adjusting the decoding clock frequency. In order to reduce buffer requirements and to prevent deterioration of video program presentation, the decoding clock frequency is adjusted by slewing only during composite video synchronization periods when composite video decoded from the encoded video stream is not being presented. The preferred video synchronization periods are the vertical blanking interval and the front porch period. Restriction of decoding clock rate adjustment to these periods ensures that decoding clock slew rate limits may be unrestricted, thereby avoiding noticeable effects in the video program presentations.

Abstract: Apparatus for developing synchronization of an intermediate layer of signal such as the transport or multiplex layer of a multi-layered compressed video signal, includes at the encoding end of the system apparatus for including a time stamp reference, such as a count value from a modulo K counter, and provision for a differential time stamp which may be updated by the transit times of respective (e.g., multiplexing) circuits as the to signal transits such circuits. At the receiving end of the system a counter is responsive to a controlled receiver clock signal and the count value of this counter is sampled at the arrival of the time stamps embedded in the transport layer. The time stamps and the differential time stamps are retrieved from the signal and combined to form a corrected time stamp. The differences of successive sampled count values of the receiver counter are compared with the differences of corresponding successive corrected time stamps to provide a signal to control the receiver clock signal.

Abstract: An optical disk format for representing several synchronized signals, e.g., multiple versions of motion pictures and multiple soundtracks. All signals are represented digitally, and the bits are arranged in data blocks. Each data block may contain a variable number of bits for each signal, ranging from none to many (relative to the other signals). This allows each signal to be represented by a variable rate bit stream, without one signal necessarily constraining another as far as bit representation is concerned. Multiple buffers are provided to insure that there are a sufficient number of bits available for each signal as required for immediate needs. When any buffer is full, reading of the data blocks stops temporarily so that no bits are lost.

Abstract: A horizontal line counter (110,115,120) provides a signal (LINE #21) identifying the beginning of video data in a particular horizontal video line. The counter is clocked by multiple clock signals. A first clock signal (HOR PLS) clocks the counter until the line count value equals a known value that is less than the line number of the horizontal line that is to be identified. When the count value equals the known value, clocking by a second clock signal (COMP SYNC) is enabled. Although, the first clock source provides a regular pulse waveform suitable for clocking the counter reliably, transitions on the first clock signal may not accurately indicate the beginning of information within a horizontal line interval. Transitions on the second clock signal accurately indicate the beginning of the desired information.

Abstract: A decoder circuit for receiving a video input signal which includes Manchester coded data bits and a range tone component having a frequency of about 102.6 kilohertz. A phase lock loop circuit detects the presence of the 102.6 kilohertz range tone component and then generates a system clock signal which is phase locked to the range tone component of the video input signal. The system clock signal is provided to a clock generating circuit which generates a clock signal having four phases. The phase lock loop circuit also provides a logic signal which is supplied to a data detecting circuit allowing the data detecting circuit to convert the Manchester coded data bits to digital data bits.

Abstract: A secondary signal is processed and injected into a primary color video signal. The timing of the subsequent transmission of the secondary signal is controlled by timing signals. The timing signals also control the transmission of a carrier burst prior to the transmission of the secondary data signal. This carrier burst is used by a receiver to synchronize with the transmitter, reduce transmission errors and to indicate that a data transmission is to follow.

Abstract: A color signal reproducing circuit comprising a phase correction device receiving a gain-controlled composite color signal, detecting color burst signal in a composite color signal and correcting phase of the color burst signal by using a 3.58 MHz signal, first gate for receiving the gain-controlled composite color signal and passing only a color signal when a color burst pulse in the delayed horizontal synchronizing signal applied from the delay device is at a low level, and mixer for mixing the phase-corrected color burst signal and the color signal from the first gate to produce a phase-corrected composite color signal.

Abstract: A video signal processing apparatus for processing a video signal includes a plurality of series-connected signal processing circuits. A plurality of timing control circuits for respectively controlling the plurality of signal processing circuits in accordance with a reference signal are provided. At least one of the plurality of timing control circuits inputs a timing signal conforming to the reference signal, and delays the passage of the timing signal therethrough by a time interval corresponding to a delay time of the video signal generated by the corresponding signal processing circuit and outputs a delayed timing signal. Consequently, it is possible to minimize a change in the timing control circuits, that is, a change in the overall apparatus, caused by the partial change in the design of the signal processing circuits.

Abstract: A synchronizing signal front end processor for video monitors includes a synchronizing signal subprocessor which responds to computer generated horizontal and vertical rate scan signals to provide alternative scan signal coupling in the event of interruption or abnormalities of the applied scan signals. The processor also includes horizontal and vertical synchronizing signal subprocessors which produce output signals indicative of the polarity and frequency of the applied selected scan synchronizing signals. In addition, the vertical and horizontal sync subprocessors provide respective sync out of range signals during sync interruption or abnormality which are utilized to stabilize the monitor display scanning process while switching to alternative scan synchronizing signal sources.

Abstract: Apparatus for developing synchronization of an intermediate layer of signal such as the transport or multiplex layer of a multi-layered compressed video signal, includes at the encoding end of the system a modulo K counter which is clocked responsive to a system clock, and the count valued is embedded in the signal at the transport layer according to a predetermined schedule. At the receiving end of the system a similar counter is responsive to a controlled receiver clock signal and the count value of this counter is sampled at the arrival of the count values embedded in the transport layer. The differences of successive sampled count values of the receiver counter are compared with the differences of corresponding successive values of the embedded count values in the transport layer to provide a signal to control the receiver clock signal.

Abstract: A method and apparatus for input data clock presence detection which utilizes an up/down counter clocked by a reference clock, which operates at a nominal frequency rate half of the nominal rate of the input data clock, and an R/S flip-flop causing the up/down counter to count up when set, and to count down when reset. The R/S flip-flop is cleared by the reference clock and set by the input data clock. The counter is selected to count up to its maximum number and remain there when continuously clocked up. Similarly, when continuously clocked down, the counter reaches its minimum number (zero) and remains there. So long as the input data clock is present and has the correct rate, after each reference clock pulse resets the flip-flop and prepares the counter to count down, there is at least one input data clock that sets the flip-flop and prepares the counter to count up.

Abstract: Specific clock periods in each machine cycle MC used by a CPU are used for accessing a video RAM synchronized with the operation of the operation of the CPU and the remaining clock periods of the machine cycle MC are used for accessing the video RAM synchronized with horizontal scanning and vertical scanning of television signal. Therefore, accessing synchronized with television signals is also performed in response to clock periods of a machine cycle MC and the video RAM can be made of a single port.

Abstract: A phase control circuit for controlling the relative phase of periodic components of two logic signals having the same frequency, and one of which periodic components has a pulse-duty factor different from 50:50, said circuit includes a signal source which provides a control signal for regulating the relative phase of the periodic components of said logic signals. The control signal has a first value for phase relationships in a predetermined range of values and a second value for phase relationships outside said range of values. A phase lock detector detects the lock status of the periodic components of the logic signals. Another signal source provides a third logic signal having a periodic component having the same frequency as the periodic component of each of the two logic signals and a pulse width substantially wider than that of the two logic signals.

Abstract: In a horizontal deflection system, an nf.sub.H timing signal is generated synchronously with an f.sub.H horizontal synchronizing component in a video signal, where nf.sub.H is a higher frequency than f.sub.H. A first circuit is responsive to the nf.sub.H timing signal for generating an nf.sub.H scan synchronizing signal synchronously with the nfH timing signal. A horizontal deflection stage is operable at nf.sub.H and responsive to the nf.sub.H scan synchronizing signal. A second circuit is responsive to the same nf.sub.H timing signal for generating horizontal blanking pulses. The nf.sub.H timing signal can be generated by a first phase locked loop and a frequency divider. The first circuit responsive to the nf.sub.H timing signal can comprise a second phase locked loop. The second circuit responsive to the nfH timing signal can comprise a driver/inverter. The horizontal blanking pulses are combined with vertical blanking pulses to form a composite blanking signal.

Abstract: An OSD circuit for displaying advertising picture data on the screen of a television receiver is disclosed, and the circuit includes: an oscillator, a first counter, a second counter, a third counter, an F/F circuit, a ROM, and automatic color adjusting circuitry. The oscillator supplies clock signals to the first counter, and the first and second counters supplies horizontal and vertical scanning addresses to the ROM so as for the advertising picture data to be outputted from the ROM. The third counter, supplies a delay signal for displaying of an advertising picture data of a picture scene at a time, thereby inhibiting the output of the ROM for a certain period of time. The F/F circuit prevents a dual display of the advertising picture on the screen, and the ROM stores the advertising picture data separately for main color data, first sub-color data, second sub-color data and brightness data.

Abstract: A color television image display apparatus wherein an image quality control signal is generated with regard to every field of an input video signal in accordance with sampled data obtained therefrom and then is supplied to an image signal processor to execute automatic adjustment of the image quality is equipped with a delay circuit having a delay time substantially equal to the time required for generation of the image quality control signal, and the video signal is supplied via such delay circuit to the video signal processor so that both the image quality control signal and the video signal to be controlled by such image quality control signal are inputted to the video signal processor substantially without a timing difference therebetween.

Abstract: A state memory circuit responsive to a selection signal indicative of either the first television system or the second television system selected according to an external setting operation and adapted to be set to a logical "1" or "0" state when the selection signal indicates that the first television system is selected, the state of the state memory circuit being alternated between "1" and "0" for every signal according to the burst flag pulse when the selection signal selects the second television system, and a timing circuit for outputting the state of the state memory circuit at a timing before a leading edge of the burst flag pulse or after a trailing edge of the burst flag pulse and responds to an even number of burst signals in one frame and generates a color video signal suitable to the first or the second television system according to the selection signal.

Abstract: A single chip video signal processing circuit capable of performing a sync separation and odd/even field detection using an NTSC mode or a PAL mode video signal, the video signal processing circuit includes a sync signal separator for separating the input video signal into a horizontal sync signal and a composite sync signal, a vertical sync signal detector for detecting a vertical sync signal from the composite sync signal, a window pulse generator for generating a window pulse having a different width according to the selection of either the NTSC mode or the PAL mode by combining the detected vertical sync signal with the horizontal sync signal, an odd/even field detector for receiving the window pulse and the vertical sync signal and for detecting the number of pulses of the vertical sync signal within the window pulse interval, and a vertical blanking interval detector for counting a predetermined number of pulses of the horizontal sync signal, the window pulse being used as a RESET pulse for generating a

Abstract: An image signal reproducing apparatus includes a synchronizing signal generator which is configured so as to count the number of clocks of a generated clock signal, generate various kinds of timing signals in accordance with the result of count, compare the phase of the generated timing signal with the phase of an input synchronizing signal, and control a period to count the number of clocks of the clock signal in accordance with the result of comparison. It becomes thereby possible to form various kinds of correct timing signals even if the input synchronizing signal reproduced from a recording medium is deteriorated.

Abstract: In a video signal processing apparatus for correcting time axis errors using a memory, with replacement of a horizontal sync signal in a video signal read out from the memory by a reference horizontal sync signal, data appearing in a vertical flyback period is not lost. A vertical flyback period detecting circuit functioning as an inhibiting means detects the vertical flyback period and produces a detection signal. An AND gate gates the detection signal and a reference horizontal sync signal generated from a sync signal generating circuit, so that a replacement of the horizontal sync signal is inhibited during the vertical flyback period, and an address, a time code and an ID code which have been inserted during the vertical flyback period are not lost.

Abstract: A composite synchronizing signal separation circuit in which separation of the composite synchronizing signal by a digital circuit is realized and such trouble as adjusting the time constant is not needed and a phase shift is reduced: a horizontal interruption receiving circuit 1 which is reset by a timing pulse signal at the time point of 3/4 from the starting time point of one horizontal synchronizing period, and separates and outputs a horizontal synchronizing signal HD from a composite synchronizing signal SYNC; a schedule counter circuit 2 which is reset by the horizontal synchronizing signal HD and outputs count value while counting up to a predetermined value in one horizontal synchronizing period; a timing decoding circuit 3 which decodes the count value and respectively outputs timing pulse signals at the time points of 1/4, 1/2 and 3/4 from the starting time point of one horizontal synchronizing period; and a vertical interruption receiving circuit 4 which samples the composite synchronizing signal

Abstract: An apparatus for synchronizing a terminal equipment such as a TV camera includes an external synchronizing signal generator which includes a switching circuit which generates two frequency signals and alternately transmits these signals to the terminal equipment which is provided with a decoder circuit decoding an alternating rate of the two signals outputted from the synchronizing signal generator, and an internal synchronizing signal generating circuit receiving a decoder circuit and generating a new synchronizing signal on the basis of the decoded signal.

Abstract: An image display device having unit image elements each arranged in a matrix formation and adapted to display a character signal synthesized with or superposed on an image signal further comprises means for matching the dot timing of the character signal and the scanning timing determined by the number of image elements of the image display device so that characters can be clearly displayed against a background image.

Abstract: A video camera in which an output signal from a solid-state image sensor is converted into a corresponding digital signal at a horizontal reading cycle of the output signal, and the digital signal is digital-processed with a first predetermined clock (fs) synchronous with the reading cycle to provide a luminance signal and a color difference signal.

Abstract: Complications of timing recovery in an ATM receiver are overcome by employing a first phase lock loop including a phase comparator, filter, voltage controlled oscillator (VCO) and output counter to lock to systems clock reference (SCR) values which are asynchronously received from a remote ATM transmitter. The SCR values represent the instantaneous values of a system timing clock (STC) at the instant of transmission of the asynchronous SCR values. In the receiver, the output counter is first set to the value of the initial received SCR value so that the derived STC is available for decoding data cells in the initial received packets. Then, so-called Presentation/Decode Time Stamps (PTS/DTS) included in the audio and video data are advantageously employed in conjunction with STC to display properly the received data. Invention, underflow of the receiver data buffers is alleviated by the addition of a "jitter-delay (D.sub.

Abstract: A high resolution video acquisition system is disclosed that provides a rrding capability at extended time with full resolution. Two real time digital scan converters, a synchronizing computer and image frame buffers cooperate to provide two high resolution Red, Green, and Blue 60 hertz video channel outputs for recording systems in digital format and for real time video display. The respective channels are sampled at approximately one frame per second per channel for approximately 2 hours, thereby providing a full resolution extended time recording capability.

Abstract: In a method and apparatus for converting a synchronizing signal received from a controller for controlling a TV camera into a new synchronizing signal, a single frame synchronizing pulse for every two field pulses is generated on the basis of at least a vertical drive signal of the synchronizing signal received from the controller. The new synchronizing pulse which has a level higher than the white level and lower than the black level of a composite video signal generated by the TV camera is injected into a video transmission line connected to the TV camera for synchronizing the latter on the basis of the injected synchronizing pulse.