Abstract: The invention provides an image processing method and device to determine whether the timing signal is abnormal by detecting timing signal related to the image signal output to the display. When the timing signal is abnormal, the display receives no the timing signal related to the image signal. The horizontal synchronous signal and vertical synchronous signal prevent the elements in the display, such as electron gun, from operating with abnormal signals, enhancing display lifetime.

Abstract: A first frame of data is encoded and a first timestamp associated with the first frame of data is generated. The first timestamp includes complete timing information. The first frame of data and the associated first timestamp is transmitted to a destination. A second frame of data is encoded and a second timestamp associated with the second frame of data is generated. The second timestamp includes a portion of the complete timing information. The second frame of data and the associated second timestamp is then transmitted to the destination. Additional frames of data are encoded and additional timestamps associated with the additional frames of data are generated. The majority of the additional timestamps include a portion of the complete timing information.

Abstract: Devices and methods are disclosed for decoding data in a data stream. One embodiment relates to a method of decoding data using an A/V decoder. In this embodiment, timing information is recovered from the input stream. The output rate of an output stream is adjusted using the recovered timing information, where the output stream has a clock that is asynchronous to a time reference of the input stream.

Abstract: A method for driving a display is provided which is capable of reducing current consumption. In the method above, a scanning frequency in a self-emissive display is changed based on a display content to be displayed in the self-emissive display.

Abstract: The invention provides an image display apparatus that efficiently adjusts a video display even when a change takes place in an input signal. The image display apparatus includes a video input device that receives a video signal, a video display that displays an optical image based on an input signal S1 from the video input device, and a video signal adjusting device that adjusts the display setting of the video display based on a signal mode of the input signal S1. The image display apparatus further includes a determining device that causes the video display adjusting device to adjust the display setting of the video display. The determining device includes an apparatus startup detector unit that detects whether a startup of the image display apparatus creates a change in the input signal, and a signal change detector unit that detects the change in the input signal. The determining device determines whether to cause the video display adjusting device to adjust the display setting only when it is needed.

Abstract: An apparatus for synchronizing chroma and luma data includes a first handshake block for luma data, a second handshake block for chroma data, and a means for providing a handshake signal to the first block and to the second block based at least in part on a determination that they are both ready to transfer data, and further for inhibiting provision of the handshake signal based at least in part on a determination that at least one of the first block and the second block is not ready to transfer data.

Abstract: A data transmitter for detecting a reference time stamp for use in reproducing a system clock from a transport packet data of a first transport stream, adding the detected reference time stamp as a header information to the transport packet data, converting the transport packet data and the header information into a second transport stream, and transmitting the second transport stream.

Abstract: Disclosed is a system and that synchronizes utilization of a data transfer with an audio/video stream. Time information contained within an audio/video stream is monitored for a specified time at which a data transfer may be combined with the audio/video stream. Combination includes logical operations, arithmetic operations, and may include screen windowing or other operations. Time required to request and receive a data transfer may be monitored or estimated such that requests for data are issued in advance of utilization of the data, allowing for data transfer time and network access time or other factors. Requests for a data transfer may be processed employing user information such that returned data transfers reflect a characteristic of the user.

Abstract: In order to synchronize two dissimilar video formats, two or more phase locked loop circuits (PLL's) may be used in tandem. A first PLL circuit may be connected to the first video format (Master) and generate an intermediate frequency. A second PLL circuit may use the intermediate frequency as the timebase for generating the pixel clock for the second video format (Slave). One or more Slaves may be connected to the generated pixel clock. The video synchronizing device may be a part of a graphics system, such as a graphics accelerator.

Abstract: A display timing generator is provided for selecting line types and providing synchronization timing signals for video signals. The display timing generator provides programmability for the user to select line types for a frame to be displayed on a display. The line types defining rise and fall times, synchronization shapes, blanking levels and horizontal and vertical timings for providing a desired display format to different display types. A plurality of programmable parameters for pulse width, horizontal timing and voltage amplitude allow a user to define timing variations associated with a given line type. The display timing generator also includes a generic mode for allowing a programmer to select line types for particular groupings of lines.

Abstract: A digital video synchronizer for providing parallel and coordinated synchronization paths for decoded and undecoded video. Processing is added for a parallel path in a synchronization memory that bypasses the comb filter and video decoder circuitry to allow a digitized composite video to pass through unchanged. This parallel path is coordinated with the decoder path to provide features of both a composite video synchronizer and a digital component decoder/synchronizer with time base corrector. A digital encoder transforms component video back into modulated composite video. The digital encoder generates a synchronizing and color burst signal to replace the sync and burst signals of the composite video signal. The synchronized composite and synchronized encoded signals are adjusted in timing, gain and DC offset to match one another so that the signals can be faded, mixed, or multiplexed without detectable differences.

Abstract: Error correcting section holds PTS(n?1) and DTS(n?1) of the frame immediately preceding the current frame and the most recent CPTS as determined to be correct in the past. The time stamp of the current frame is determined to be incorrect if (1) CPTS>PTS(n) which is the current frame or (2) CPTS<PTS(n) and greater than the time interval of time information B_TS(n)?B_TS(n?1) plus a reference time (e.g., the multiple of the standard frame interval 33 msec of moving images using 30 frames per second). If the PTS(n) of the current frame is correct, it is used as reproduction timing and updates the CPTS, using the PTS(n). If, on the other hand, the PTS(n) of the current frame is incorrect, it is not used and the time obtained by adding the CPTS and B_TS(n)?B_TS(n?1) is used as corrected PTS(n).

Abstract: A splicing system includes a splicer for seamlessly splicing togther digitally encoded data streams. In a preferred embodiment, the splicer preferably parses successive splice buffers of data stream data for a splice-out point and a splice-in point, closing an initial group of pictures GOP if needed. The preferred splicer further finds a new data stream real-time program clock reference PCR value for aligning new data stream decode/presentation, and aligns the new data stream start time. Concurrently, the splicer preferably uses a frame table to detect overflow and corrects such overflow by adding null packets, thereby delaying portions of data stream data. The splicer also preferably restores data stream encoding by deleting null packets, and thereby accelerating a portion of data stream data. In a further preferred embodiment, the splicer preferably uses a bit-clock schedule offset to delay or accelerate portions of data stream data.

Abstract: An apparatus and method for time synchronization of a plurality of multimedia streams are described. In one embodiment, the method includes the concurrent capture of multimedia data via a plurality of multimedia platforms. During the concurrent capture of the multimedia data, each of the multimedia platforms receives a synchronization signal from a synchronization generation unit. In response, each platform processes a received synchronization signal to generate a common reference clock signal among each of the platforms. Once the common clock signal is generated, each of the platforms synchronizes captured multimedia data to form multimedia stream data according to the common reference clock signal. As such, the plurality of multimedia platforms are able to perform collaborative signal processing tasks of multimedia streams, including, for example, array signal processing algorithms.

Abstract: A video processing system and method are provided for generating clock and timing signals from an incoming video signal. The system includes a timing reference circuit for generating a reference clock signal, a video format detector coupled to the reference clock signal and to synchronization data derived from the incoming video signal for generating a format signal indicating the format of the incoming video signal, and a clock and timing generator circuit coupled to the format signal and the reference clock signal for generating clock and timing signals that emulate the incoming video signal, and may be locked to the incoming video signal.

Abstract: Methods and systems are provided for synchronizing various time-stamped data streams. The data streams can be synchronized to another data stream or to a point of reference such as a reference clock. In one embodiment, synchronization processing takes place in association with a filter graph comprising multiple filters. The filter graph is configured to process multiple timestamped data streams for rendering the data streams in accordance with data stream timestamps. A synchronization module is provided and is associated with the filter graph queries individual filters of the filter graph to ascertain input timestamp-to-output timestamp mappings. The module computes adjustments that are to be made to output timestamps in order to synchronize the data streams, and then instructs queried filters to adjust their output timestamps in accordance with its adjustment computations.

Abstract: Methods and systems are provided for synchronizing various time-stamped data streams. The data streams can be synchronized to another data stream or to a point of reference such as a reference clock. In one embodiment, synchronization processing takes place in association with a filter graph comprising multiple filters. The filter graph is configured to process multiple timestamped data streams for rendering the data streams in accordance with data stream timestamps. A synchronization module is provided and is associated with the filter graph queries individual filters of the filter graph to ascertain input timestamp-to-output timestamp mappings. The module computes adjustments that are to be made to output timestamps in order to synchronize the data streams, and then instructs queried filters to adjust their output timestamps in accordance with its adjustment computations.

Abstract: In a transport stream decoder, a plurality of synchronization establishment circuits receive a plurality of different transport streams and a plurality of input clocks corresponding thereto, to establish synchronization between the transport streams and the input clocks. A multiple TS time-division multiplexing circuit receives outputs of two FIFO memories, converts a plurality of transport stream signals into time-division multiplexing signals synchronizing with an internal processing clock, and provides an addition of a TS identification signal indicating which one of the transport streams corresponds to each time-division multiplexing signal. Therefore, a TS decoder with suppressed circuit scale can be provided even when different types of transport streams are handled.

Abstract: Methods and apparatus are described for time-correct combination of two data streams, particularly video data streams. In this case, a sync signal of the first video data stream is a horizontal sync signal. In this case, methods and apparatus are provided to combine the two video data streams in a pixel-precise manner, even though time base error, i.e. discontinuities occur in the second video data stream.

Abstract: An optical transmission system for compensating for transmission loss includes a transmitting apparatus for serializing a plurality of n (n is a natural number)-bit channel data received from the outside in response to a predetermined clock signal, converting the serialized channel data and the predetermined clock signal into a current signal whose magnitude changes corresponding to an error detection signal, and outputting optical signals having optical output power corresponding to the magnitude of the current signal, a first optical fiber for transmitting the optical signals, a receiving apparatus for recovering the n-bit channel data and the predetermined clock signal from the optical signals received through the first optical fiber, detecting transmission loss generated when the optical signals are transmitted and received, optically converting the transmission loss, and outputting the optically converted transmission loss as the error detection signal, and a second optical fiber for transmitting the opt

Abstract: The present invention allows routers in a digital communications network, such as the Internet, to be given the time awareness that is necessary for timely transfer of real time signals in the form of digital data packets. Timing information generated at the source of the signal is included in the packets in the form of first and second time stamps, which are used by network routers to establish dispatch deadlines by which the packets must be forwarded to ensure time-faithful reconstruction of the real time signal at the destination. The same timing information can be used at the destination to synchronize the clock for presentation of the real time signal to the source clock. The first and second time stamps (a differential time and a dispatch time) are derived by a transmitter unit (100) from a counter (118) that counts pulses from an oscillator (116) that most advantageously is locked to an integer multiple or a fraction of a universally available time measure.

Abstract: Moving image signal decoder section decodes the moving image bit stream and the time stamp for reproduction transmitted from multiple separator section on a frame by frame basis and stored in input buffer and provides time control section with the time stamp for reproduction that corresponds to the decoded frame and the information on the time stamp in the header of the moving image bit stream, while storing the decoded image data in frame memory. The time control section transmits a request to image output section for outputting image data at the time specified by the time stamp for reproduction as transmitted from the moving image signal decoder section or at the time as determined on the basis of the time stamp of the moving image itself and causes the image data to be read out of the frame memory and displayed on the LCD.

Abstract: A method of synchronising the phase of a local image synchronisation signal generator of a local video data processor in communication with an asynchronous switched packet network to the phase of a reference image synchronisation signal generator of a reference video data processor also coupled to the network, the local and reference processors having respective clocks, the reference and local image synchronisation signal generators generating periodic image synchronisation signals in synchronism with the reference and local clocks respectively comprises the steps of:

Abstract: Detection of synchronization signals of digital broadcasting waves of respective reception systems is periodically carried out, and a relative time difference between synchronization timings of the synchronization signals is grasped. In the case where a synchronization signal can not be detected from the reception system under selection, the relative value is added to or subtracted from the generation timing of a synchronization signal of the other reception system, so that the synchronization timing that could not be detected is presumed.

Abstract: A sampling pulse generator for an electronic endoscope that comprises a CDS circuit, OR circuits, a clock pulse generator, a shift counter, first and second switch groups, EEPROM and a CPU, is provided. The generator cyclically generates clock pulses. The pulses are cyclically counted between 0 and 9 by the counter. The counter has ten output terminals that correspond to each of the count numbers. A signal is only output to a terminal corresponding to the current count number. Each of the first and second switch groups has ten switches that are connected to each of the terminals. With data in the EEPROM, the on-off states of the switches are set by the CPU. The CCD drive pulses are generated by signals from the terminals via OR circuits. The clamp pulse and sample-hold pulse are generated by signals from the switch groups which are set in the on state.

Abstract: A method for clock recovery comprises a series of steps to be performed in a decoder to adaptively estimate the ratio P/S of the frequency of an encoder system time clock and the frequency of a decoder. The steps include performing a series of overlapping trials N which calculate time differentials dP(n), dS(n), respectively) between selected pairs of temporally separated clock references CRs and arrival times STCs. Each trial concludes by calculating an estimated ratio X according to the formula: X(N)=(&Sgr;dP(n))/(&Sgr;dS(n)) A preferred embodiment of the present invention also includes the step of adjusting the decoder clock in accordance with a damped version of the estimate, thereby “recovering” the encoder STC in the decoder.

Abstract: The present invention provides a multi-layered electronic lecturing system, a method and a storage medium to link a multi-layer of an existing electronic lecture content with an additional real-time drawing and sound recording by a lecturer or a trainee, simultaneously reproducing the existing lecture content so that newly added drawings, or sounds can be reproduced synchronously with the existing lecture data.

Abstract: A video signal processor and a video signal processing method which can prevent the length of one period of a clock from being shortened and can output a video signal that is in phase with a reference signal. When a video data signal that has been processed using a first clock signal is processed using a second clock signal, this video signal processor does not utilize as the second clock signal, a clock signal that is in phase with a reference signal but a clock signal that is employed in a later stage signal processor, and interpolates the video data signal by an interpolation circuit so as to make the signal in phase with the reference signal.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples.

Abstract: A method, apparatus, and computer-readable media for recovering a symbol clock signal from an American Television Standards Committee (ATSC) digital television (DTV) signal comprises coherently downconverting the ATSC DTV signal to a baseband signal; delaying the baseband signal; multiplying the baseband signal and the delayed baseband signal; band-pass filtering the symbol clock signal; and generating the symbol clock signal based on the filtered baseband signal.

Abstract: A method of measuring horizontal frequency, which comprises the steps of resetting an 8-bit counter, which counts horizontal synchronous pulses separated from a video signal, at a time point corresponding to an edge of a vertical synchronous signal separated from the video signal, causing a data latch portion, which is operative to latch count data obtained from a 16-bit counter operative to count clock pulses having a predetermined frequency, to latch the count data obtained from the 16-bit counter at a time point corresponding to an edge of a bit output signal obtained from the seventh bit position of the 8-bit counter, detecting a period which corresponds to 128 times a horizontal period of the video signal based on a difference between counted values represented respectively by a couple of count data latched successively by the data latch portion, and measuring horizontal frequency of the video signal by calculating the horizontal frequency on the strength of the period corresponding to 128 times the hori

Abstract: A digital TV receiver and a method for receiving a digital TV signal are disclosed, in which timing recovery and segment synchronizing signal recovery are independently implemented and VSB demodulation is digitally implemented.

Abstract: A signal processing method and apparatus in which a horizontal and/or vertical synchronizing signal related to a received video signal is monitored to determine if a relatively large change has occurred in the respective vertical and/or horizontal time period such that a change in video signal source may have occurred. Upon the detection of such a change, the operation of a phase lock loop (PLL) such as horizontal phase lock loop (HPLL) and/or vertical phase lock loop (VPLL) circuit is adapted as appropriate.

Abstract: A display apparatus having a display part, comprising an amplifying part amplifying an inputted picture signal and transmitting it to the display part; a clock signal generating part generating a clock signal in synchronization with at least one of vertical and horizontal synchronous signals transmitted together with the inputted picture signal; and a controller controlling the amplifying part to adjust an amplification rate so that brightness is alternately changed within a predetermined limit according to at least one of periods of the horizontal and vertical synchronous signals, synchronizing with the clock signal generated from the clock signal generating part. With this configuration, clear and bright moving pictures can be displayed, and the life span of the display apparatus can be lengthened.

Abstract: A system and method for synchronizing signals having respective sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal with an associated sub-carrier. Various aspects may determine a phase of the sub-carrier and store an indication of such phase. Various aspects may generate and store a cropped version of the sampled signal. Various aspects may also store an indication of which samples were cropped from the sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may read a cropped version of a sampled signal and an associated indication of phase. Various aspects may generate a restored sampled signal by adding samples to the read cropped version. Various aspects may, based on the synchronization signal and indication of phase, output the restored sampled signal aligned with a second sampled signal.

Abstract: Disclosed are a data broadcasting system and an operating method thereof that can provide advertisement while a viewer receives data with a delay. A method for operating a data broadcasting system of the present invention includes the steps of: downloading a data service table for a specific application at the client; providing an advertisement and performing a data receiving process at the same time with reference to the data service table; and executing the specific application using data files extracted through the data receiving process.

Abstract: An apparatus for reproducing a system clock provided with a reproducing unit for reproducing a first time reference clock T1, a generating unit for generating a system clock Sck, a generating unit for generating a second time reference clock T2, a synchronization control unit for minimizing, based on the clocks T1 and T2, the deviation between these clocks, a first calculating unit for calculating a difference between counts of the clock T1 counted in a predetermined time interval, and a second calculating unit for calculating a difference between counts of the clock T2 counted in a predetermined time interval, the outputs of the calculation of the differences being input to the synchronization control unit to minimize the deviation between the clocks, whereby it becomes possible to reproduce high quality data even when switching channels from one node to another node when reproducing digital data from a plurality of sending side nodes at a receiving side node.

Abstract: There is disclosed a system and method for recovering a recurring data segment synchronization pattern in the presence of an arbitrary phase rotation of a pilot carrier by detecting and compensating for the amount of the phase rotation. The system comprises a first synchronization pattern detector capable of receiving a real component of a complex signal and detecting a data segment synchronization pattern on the real component, and a second synchronization pattern detector capable of receiving an imaginary component of a complex signal and detecting a data segment synchronization pattern on the imaginary component. There is also disclosed a method for compensating a pilot carrier phase rotation comprising the steps of determining the angle of pilot carrier phase rotation present in a complex signal and rotating the pilot carrier signal through the same angle in the opposite direction.

Abstract: The present invention provides a portable television receiver which comprises an antenna 4 for receiving waves of television broadcast, a transmitting-receiving circuit 12 for detecting the reception condition of the waves of television broadcast before recording, a display 21, a speaker 20, and a main control circuit 14. The main control circuit 14 judges whether the recording is permitted with reference to the detected result of the reception condition of waves of television broadcast. When the recording is not permitted, the message that the recording is not permitted is shown on the display 21, and the speaker 20 produces sound.

Abstract: A timing recovery apparatus and method for a digital TV is disclosed. The timing recovery apparatus includes: a symbol synchronization unit for determining the bandwidth of a timing recovery loop in a plurality of steps according to a convergence degree; and a timing lock detector for detecting a lock using a reference value calculated by the envelope of a timing error, whereby the envelope of the timing error calculated according to a channel state is used as a reference value for thereby preventing a lock error and assuring a rapid and accurate convergence characteristic.

Abstract: There is provided an image signal repeater apparatus with a simple construction, which can prevent the accumulation of jitter even if the image signal repeater apparatuses are connected in multiple stages, and which enables the reception of image signals of various frequencies.

Abstract: In a combined audio and video encoding system, the encoding system receiving a stream of video samples and a stream of audio samples, the encoding system producing an encoded video stream from the video samples and an encoded audio stream from the audio samples, a method for synchronizing between the encoded video stream and the encoded audio stream, the method including the steps of monitoring the encoded video stream and the encoded audio stream, detecting the amount of video data accumulated from the encoded video stream in a given time period, detecting the amount of audio data accumulated from the encoded audio stream in a given time period, increasing the number of audio samples in the audio stream, when the accumulated amount of video data is greater than the accumulated amount of audio data and decreasing the number of audio samples in the audio stream, when the accumulated amount of audio data is greater than the accumulated amount of video data.

Abstract: The invention provides an image display apparatus that efficiently adjusts a video display even when a change takes place in an input signal. The image display apparatus includes a video input device that receives a video signal, a video display that displays an optical image based on an input signal S1 from the video input device, and a video signal adjusting device that adjusts the display setting of the video display based on a signal mode of the input signal S1. The image display apparatus further includes a determining device that causes the video display adjusting device to adjust the display setting of the video display. The determining device includes an apparatus startup detector unit that detects whether a startup of the image display apparatus creates a change in the input signal, and a signal change detector unit that detects the change in the input signal. The determining device determines whether to cause the video display adjusting device to adjust the display setting only when it is needed.

Abstract: A system for handling an input video stream comprises an internal clock generator generating a first clock and a synchronization unit receiving the input video stream having an associated second clock being slower than the first clock. The synchronization unit samples the second clock with the first clock thereby generating a third clock synchronized with the first clock having no signal in case of a data gap. This signal can be used to determine the dwelling time for a charge being applied to a pixel which will be constant even without a buffer memory.

Abstract: In preferred embodiments, a system including a transmitter, a receiver, and a serial link, in which the transmitter is configured to transmit video data, embedded-clock auxiliary data (or auxiliary data derived from embedded-clock auxiliary data), and a video clock over the link to the receiver. The transmitter is configured to extract a sample clock from the auxiliary data without use of a phase-locked loop, and to generate time stamp data in response to the sample clock and the video clock. Typically, the auxiliary data are SPDIF (or other) audio data, and the sample clock changes state in response to codes that occur periodically in the audio data. Other aspects of the invention are a transmitter for use in such a system, a time stamp data generation circuit for use in such a transmitter, and a method for generating time stamp data in response to a stream of embedded-clock auxiliary data and a video clock.

Abstract: Devices and methods are disclosed for decoding data in a data stream. One embodiment relates to a method of decoding data using an A/V decoder. In this embodiment, timing information is recovered from the input stream. The output rate of an output stream is adjusted using the recovered timing information, where the output stream has a clock that is asynchronous to a time reference of the input stream.

Abstract: Devices and methods are disclosed for managing an output of an output stream. One embodiment relates to a method of tracking an output of an A/V decoder. In this embodiment, indication of an output stream time reference and a location of at least one output sample are received. The received time reference is compared to the output sample and the output sample rate of the A/V decoder is adjusted.

Abstract: In order to maintain continuity before and after interruption of a streaming broadcast, a receiving apparatus according to the present invention includes: a reception unit which receives data on a stream broadcast; a memory which is capable of storing a predetermined amount of the received data on a stream broadcast; a data processing unit which processes the data on a stream broadcast to generate video data for the stream broadcast; a video output unit which outputs the video data to a display apparatus; and a detection unit which detects interruption point data indicating a position where the stream broadcast should be interrupted out of the received data on a stream broadcast; when an abnormality is detected, the output of the video data is stopped at a position instructed in the interruption point data detected by the detection unit.

Abstract: An integrated receiver with multiple, independently synchronized clock signals for multiple channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. An integrated circuit that services two satellite programs must generate and distribute corresponding time domain clocks to the various components of the integrated circuit. The transport block that receives one or more satellite signals from a demodulating block will extract program clock recover values from each signal being decoded and use these values to produce an error signal or control word that serves as an input to a clock generator. Based upon this input, the clock circuit will produce a corresponding time domain clock for each channel serviced by the integrated circuit. The output of the clock circuit is distributed to the various processing blocks within the integrated circuit that operate upon channel content received and processed by the transport block.

Abstract: A receiver is constructed so that it detects a short-break of a digital broadcasting wave by the absence of a synchronizing code or by a transmission control signal multiplexed with the broadcasting wave and, according to the short-break detection signal, holds data and state information (program arrangement, and reference time information) obtained by an antenna and converter (1), tuner and digital decoding portion (2), an error correction code decoding portion (3), a stream multiplexed signal separating portion (4), an audio/video decoding portion (5) and the other components and performs a process for optimally changing characteristics of closed loops for establishing synchronization.