Abstract: In memory component having a write-timing calibration mode, control information that specifies a write operation is received via a first external signal path and write data corresponding to the write operation is received via a second external signal path. The memory component receives multiple delayed versions of a timing signal used to indicate that the write data is valid write data, and outputs signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay interval between outputting the control information on the first external signal path and outputting the write data on the second external signal path.

Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.

Abstract: A semiconductor device includes a test circuit that generates a pulse signal from a timing signal. The test circuit outputs the pulse signal and a first set of address signals in response to a first type transition of the timing signal. The test circuit outputs the pulse signal and a second set of address signals in response to a second type transition of the timing signal. The second set of address signals is different from the first set of address signals.

Abstract: A semiconductor memory device includes data transmission devices for transmit data in synchronization with each other. The semiconductor memory device includes a plurality of data transferring unit, a first control unit, a multiplexing unit, and a second control unit. The plurality of data transferring unit transfers data to a plurality of global lines. The first control unit controls the plurality of data transferring unit in response to a column select signal to select a column of a memory cell. The multiplexing unit multiplexes the data transferred to the plurality of global lines. The second control unit controls the multiplexing unit, wherein the second control unit synchronizes the column select signal with a column address signal having a column address information of the memory cell.

Abstract: An anti-fuse circuit includes an anti-fuse coupled to a sensing node, a driving unit configured to rupture the anti-fuse in response to a rupture enable signal, an anti-fuse status detecting unit configured to output an anti-fuse status detecting signal in response to a voltage at the sensing node corresponding to a rupture status of the anti-fuse, and a sensing current supplying unit configured to supply sensing current to the sensing node in response to a rupture sensing signal.

Abstract: A semiconductor memory device may include a mode-register reading controller and a mode register. The mode-register reading controller generates a control signal for loading data into an input/output line in response to an enable signal, during a mode-register reading operation. The control signal is generated in response to a mode-register read signal when there is a reset command is input. The mode register loads the data into the input/output line in response to the control signal.

Abstract: A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully.

Abstract: A semiconductor device includes a reset sequence circuit, a latch circuit, and a reset control circuit. The reset sequence circuit is activated by receiving an externally input signal when a reset operation is started and outputs a first trigger signal. The latch circuit is capable of holding selection information on circuits capable of being reset. The selection information is externally input. The reset control circuit outputs a reset signal on the basis of the selection information held in the latch circuit in response to a power-on reset signal and the first trigger signal output from the reset sequence circuit.

Abstract: An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal.

Abstract: A semiconductor memory device includes a burst termination control unit and a data output control unit. The burst termination control unit generates a termination control signal, a read command, a write command and a mode resister read command. The data output control unit stops a data output operation in response to the termination control signal.

Abstract: In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.

Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.

Abstract: A semiconductor memory apparatus may include a bonding pad; a control signal pad; and an operation mode signal generation unit configured to generate a plurality of operation mode signals in response to a bonding signal inputted through the bonding pad and a control signal inputted through the control signal pad.

Abstract: Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.

Abstract: A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

Abstract: A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit. The buffer unit provides data of an internal buffer input line to an external buffer output line. The delay control unit generates a buffer enable signal corresponding to a received reference control signal. The buffer unit blocks the provision of the data to the buffer output line in response to a deactivation of the buffer enable signal. The buffer enable signal remains in an activated state when the period of the reference control signal is shorter than a reference period. The data output buffer may be included in a semiconductor memory device.

Abstract: Various embodiments of a semiconductor memory apparatus and a related driving method are disclosed. According to one exemplary embodiment, a semiconductor memory apparatus may include a switching unit and a switching control unit. The switching unit couples or decouples a cell plate voltage line to or from a cell plate electrode in response to a control signal. The switching control unit is configured to enable the control signal at a first timing and disable the control signal at a second timing.

Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: Apparatus and methods are provided for accessing memory elements. An exemplary memory element includes an array of memory cells and a control module. Each memory cell of the array is coupled to an access line, wherein the control module is configured to assert a first signal for a write duty cycle on the access line to enable writing to a first memory cell of the array of memory cells, and the control module is configured to assert a second signal for a read duty cycle on the access line to enable reading from the first memory cell. The write duty cycle and the read duty cycle are each selected from a plurality of possible duty cycles. In an exemplary embodiment, the read duty cycle and the write duty cycle are chosen to optimize a performance parameter for the memory element.

Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines whether to execute a command unaccompanied by an address, by referring to a history of commands.

Abstract: A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.

Abstract: A semiconductor memory device includes a voltage detector configured to detect a level of an external power supply voltage and an internal voltage generator configured to generate an internal voltage in response to an active signal and drive an internal voltage terminal with a driving ability corresponding to an output signal of the voltage detector. A method for operating the semiconductor memory device includes detecting a level of an external power supply voltage, based on a first target level, to output a detection signal; and generating an internal voltage in response to an active signal, and driving an internal voltage terminal with a driving ability corresponding to the detection signal.

Abstract: A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface for connecting to the at least one discrete memory device, and a global input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

Abstract: A semiconductor device includes a data input/output circuit connected to the memory cell array via a sense circuit, and an access control circuit that controls access to the memory cell array. The access control circuit includes: a first signal unit outputting a first signal for activating or inactivating a word line; a second signal unit outputting a second signal for activating or inactivating a bit line and the sense circuit; a third signal unit outputting a third signal for starting or stopping a supply of an overdrive voltage to the sense circuit; and a fourth signal unit outputting a fourth signal for inactivating the word line. The period during which the third signal remains activated is determined in accordance with the magnitude of an external voltage. In the fourth signal unit, the timing to generate the fourth signal is determined independently of the magnitude of the external voltage.

Abstract: Provided is a circuit for controlling a data bus connecting a bitline sense amplifier to a data sense amplifier in accordance with a variation of an operating frequency of a memory device, being comprised of a pulse width adjusting circuit for varying a pulse width of an input signal in accordance with the operating frequency of the memory device after receiving the input signal, a signal transmission circuit for buffing a signal outputted from the pulse width adjusting circuit, and an output circuit for outputting a first signal to control the data bus in response to a signal outputted from the signal transmission circuit.

Abstract: A memory system includes an array of X memory cells that each includes Y storage regions. The system also includes a read module that receives a first read signal that includes a first read signal data component and a first read signal interference component from a first one of the Y storage regions. The read module also receives a second read signal from a second one of the Y storage regions. The first interference component includes interference from the second one of the Y storage regions. The system also includes a data detection module that recovers the first read signal data component from the first read signal based on the second read signal and one or more of M noiseless signal estimates. M and X are integers greater than or equal to one, and Y is an integer greater than or equal to two.

Abstract: Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the memory cell, and a first line configured to transfer information to and from the memory cell. The control signal has a first level during a first time interval and a second level during a second time interval of a memory operation. The apparatus and methods also include a module configured to reduce difference between a value of a voltage on the second line and a value of a voltage on a node of the device during a first time portion of the second time interval. Additional apparatus and methods are disclosed.

Abstract: A method may comprise executing a read operation to access a memory array by performing a preactive command to include a row-address-write operation and a bitline precharge and column selection operation and performing an activate command including a column-address-write operation and a row-decode-selection operation.

Abstract: The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus. A second control line serially connects a second group of devices on both the front and back faces so that the second group of devices commonly contribute multiple bits to a data bus.

Abstract: The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

Abstract: A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.

Abstract: A semiconductor memory apparatus includes a shared pad which is configured to output a read operation control signal in a read operation and receive a write operation control signal in a write operation.

Abstract: Provided are a memory circuit having a small circuit scale and a voltage detection circuit including the memory circuit. An NMOS transistor (21) is in an off state during loading and writing and is in an on state during reading. An NMOS transistor (22) is turned on when a high level input is received and turned off when a low level input is received. An NMOS transistor (23) is in the off state during loading and writing and is in the on state during reading. A PMOS transistor (26) is in the on state during loading and is in the off state during writing and reading. A PMOS transistor (27) is turned off when the high level input is received during loading, is turned on when the low level input is received during loading, and is in the on state during writing and reading.

Abstract: A semiconductor memory apparatus includes an internal circuit configured to be driven by current flowing between first and second voltage nodes, and a current control unit configured to control an amount of the current in response to an operational-speed information signal.

Abstract: A flash memory device includes a chip disable fuse circuit that has a fuse and that outputs a chip disable signal when the fuse is cut out, and a ready/busy control circuit that forcibly activates a ready/busy signal representing an internal operational state in response to the chip disable signal and externally outputs the ready/busy signal through a ready/busy output pin.

Abstract: Non-volatile memory devices including on-die termination circuits connected to an input/output circuit and an on-die termination control logic detecting a preamble of a strobe signal based on a command and a control signal and activating the on-die termination within the preamble period.

Abstract: A semiconductor memory device includes a memory cell array, an output driver having a pseudo-open drain (POD) structure and providing read data from the memory cell array in a de-emphasis mode, and control logic controlling the output driver in response to a read command to activate the de-emphasis mode. The control logic activates the de-emphasis mode only during an output period during which the read data is output by the output driver.

Abstract: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a column control signal generator configured to generate a column control signal for a pair of bit lines corresponding to a data mask during a data mask operation; and a bit line sense amplifier configured to sense and amplify a voltage difference between the pair of bit lines and electrically couple the pair of bit lines to a pair of segment input/output lines in response to the column control signal.

Abstract: A semiconductor memory device includes a memory block configured to store a data inputted/outputted through a data transfer line, a data output block configured to output the data loaded on the data transfer line in response to a source clock, wherein the data output block is controlled to be coupled with the data transfer line in response to a write operation signal, a write operation signal generation block configured to generate the write operation signal in response to an operation selection signal and a reference clock lagging behind the source clock by a set time, and a data input block configured to load the data on the data transfer line in response to the write operation signal.

Abstract: A synchronous type semiconductor storage device includes an array unit which includes a cell array and sense amplifiers. The synchronous type semiconductor storage device includes a read/write pulse generator which generates a read pulse signal and a write pulse signal according to a clock signal, the clock signal defining one cycle time of a read operation and a write operation with respect to the array unit as one cycle. The synchronous type semiconductor storage device includes a secondary amplifier which is activated according to the read pulse signal to read out data stored in the sense amplifiers through the read/write line. The synchronous type semiconductor storage device includes a write driver which is activated according to the write pulse signal to write data in the sense amplifiers through the read/write line.

Abstract: A semiconductor memory device includes a pattern data generator configured to generate certain pattern data in a training operation mode, and an output driver configured to drive the pattern data to output training data with a slew rate corresponding to an external command in the training operation mode.

Abstract: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a redundancy signal generation unit configured to compare mat information set by fuse cutting with address information inputted from outside and generate a plurality of redundancy signals; a mat designation signal generation unit configured to generate a plurality of mat designation signals in response to the plurality of redundancy signals and a plurality of mat address signals; and a mat control signal generation group configured to enable one of the mat control signals in response to the plurality of mat designation signals.

Abstract: Circuitry for determining timing characteristics, for example, access time, setup time, hold time, recovery time and removal time, of as-manufactured digital circuit elements, such as latches, flip-flops and memory cells. Each element under test is embodied in variable-loop-path ring oscillator circuitry that includes multiple ring-oscillator loop paths, each of which differs from the other(s) in terms of inclusion and exclusion of ones of a data input and a data output of the element under test. Each loop path is caused to oscillate at each of a plurality of frequencies, and data regarding the oscillation frequencies is used to determine one or more timing characteristics of the element under test. The variable-loop-path ring oscillator circuitry can be incorporated into a variety of test systems, including automated testing equipment, and built-in self test structures and can be used in performing model-to-hardware correlation of library cells that include testable as-manufactured digital circuit elements.

Abstract: A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal for selecting one of the first SRAM cells to be read/written the data and a second control signal for selecting one of the second SRAM cells to be read/written the potential difference, a sense amplifier circuit that amplifies a potential difference of a read signal output from a bit line pair of the second SRAM cell selected according to the second control signal, and a write driver circuit that outputs a write signal to the bit line pair of the second SRAM cell selected according to the second control signal, and the write signal has a potential difference between bit lines larger than the read signal.

Abstract: plurality of core chips to which chip identification information different from each other is allocated and an interface chip are layered, the plurality of core chips are commonly connected to the interface chip through a first current path including at least a through silicon via, the interface chip serially supplies an enable signal to the plurality of core chips through the first current path, and the plurality of core chips are activated based on a logic level of a bit corresponding to the chip identification information among a plurality of bits configuring the enable signal. The present invention can reduce the number of through silicon vias required to supply an enable signal.

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.

Abstract: A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.

Abstract: Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled to the data bus. The data capture circuit receives a data signal relative to a write strobe signal and captures a first data digit of the data signal responsive to a first edge of the write strobe signal and at least a second data digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each of the data digits of the data signal in substantially the same manner as the data capture circuit, and also generates a latch control signal indicative of when each data bits is latched. The latch control signal is provided to a write control circuit coupled to the feedback capture circuit and the data capture circuit.