Abstract: According to an embodiment, a transmitter is described comprising an input configured to receive a plurality of symbols to be transmitted and a timing circuit configured to associate each symbol with a symbol transmission period of a predefined sequence of symbol transmission periods, wherein the symbol transmission periods of the sequence of symbol transmission periods are at least partially different.

Abstract: A device for controlling a clock signal generator includes a processor (101) for forming at least two mutually different control quantities on the basis of reception moments of timing messages such as time stamps, where the reception moments are expressed as time values based on a first clock signal and the timing messages are transmitted in accordance with a second clock signal. The processor also calculates a weighted sum of the control quantities, and controls the clock signal generator with the weighted sum so as to synchronize the first clock signal and the second clock signal. The control quantities may represent, for example, a filtered value of observed phase-errors, a phase-error corresponding to a minimum observed transfer delay, and phase-errors corresponding to a given portion of the delay distribution. Using the weighted sum of the mutually different control quantities improves the utilization of the information content of the timing messages.

Abstract: Disclosed are embodiments for an intermediary signal conditioning device with an input adaptable detection mode. In one embodiment, an intermediary signal conditioning device has a control module, an input module, and an output module. The input module and the control module are for receiving an input signal. The control module is configured to interrupt the output module within a duration of time to allow at least a minimum pulse length of the input signal to be output as an output signal from the output module. The intermediary signal conditioning device is configured to condition the input signal for retransmission as the output signal.

Abstract: A differential transmission circuit comprises a sending unit that generates a pair of differential signals from an input signal, and sends the differential signals; a receiver that receives the differential signals sent by the sending unit; and a transmission path that transmits the differential signals from the sending unit to the receiver, wherein the sending unit has a selector that selects one of the input signal and a signal obtained by inverting a polarity of the input signal, and generates the differential signals from the signal selected by the selector.

Abstract: A transmission apparatus, a signal sending apparatus, and a signal receiving apparatus, and a transmission method, a signal sending method, and a signal receiving method capable of solving a problem of metastability and suppressing a delay of a signal when sending and receiving apparatuses having different operation clock frequencies send/receive the signal representative of control information, for example. Included are a sending part that operates in synchronization with a first clock having a first period to output a transmission signal having a signal level that is inverted in response to an input of a first pulse signal corresponding to the first period and a receiving part that operates in synchronization with a second clock having a second period to output a second pulse signal corresponding to the second period in response to inversion of a signal level of the transmission signal.

Abstract: A multi-stage receiver including, in one embodiment, a sequence of processing stages. At least one of the processing stages includes a first processing block, a delay block, and a second processing block. The first processing block is adapted to receive an input signal and generate from the input signal one or more processing parameters. The delay block is adapted to generate a delayed signal. The second processing block is adapted to apply the one or more processing parameters to the delayed signal to generate an output signal. The delay block compensates for one or more processing delays associated with the generation of the one or more processing parameters by the first processing block.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: A frequency response signal transmitting device for frequency response measurement includes: a first oscillator unit configured to generate a clock signal; a clock and data recovery (CDR) unit configured to remove a jitter component of the clock signal; a pulse signal generation unit configured to receive an output signal of the CDR unit and generate a pulse signal repeated at a predetermined period; and an optical signal transmission unit configured to receive the output signal of the CDR unit and apply the received signal to an optical cable.

Abstract: A signal source synchronization circuit includes: a first TDC circuit that measures a first path delay time which is a time difference between an input time of a trigger signal to a first input terminal and an input time of the trigger signal to a second input terminal; and a second TDC circuit that measures a second path delay time which is a time difference between an input time of the trigger signal to a first input terminal and an input time of the trigger signal to a second input terminal, wherein a first phase shifter adjustment circuit sets a phase adjustment amount corresponding to the first path delay time in a first phase shifter, and a second phase shifter adjustment circuit sets a phase adjustment amount corresponding to the second path delay time in a second phase shifter.

Abstract: The present invention provides a method and an apparatus for generating secondary synchronization signals, wherein the method comprises steps of: determining a value of iteration times M according to a total number N of cell ID groups or a cell ID group index NID(1), wherein M is a natural number; calculating to obtain M cyclic shift accumulation parameters qk (k=0, 1 . . . M?1) through M times of iterations; calculating a common cyclic shift factor m? through q0; calculating a first cyclic shift value m0 and a second cyclic shift value m1 according to m?; and generating the secondary synchronization signals according to m0 and m1. The present invention solves the problem that the method for generating the secondary synchronization signals in related arts cannot support a greater number of cell ID groups.

Abstract: Disclosed is an apparatus and method for detecting a code. The code detecting apparatus may include a detector to detect symbol synchronous timing information associated with a PSS code from a first signal received during a predetermined first period, a compensator to extract and buffer the PSS code and the SSS code based on the symbol synchronous timing information detected from a second signal received during a predetermined second period, and compensate for a frequency offset with respect to the buffered PSS code, and a processor to re-detect the symbol synchronous timing information based on the PSS code in which the frequency offset is compensated for, and extract the buffered SSS code using the re-detected symbol synchronous timing information.

Abstract: A medical device communication system includes a receiver adapted to receive radio frequency (RF) signals and configured to operate in a first mode to poll for an RF signal for a first time interval to detect an element of a valid input signal during the first time interval. In response to detecting the element of a valid input signal in the first time interval, the receiver operates in a second mode to poll for the RF signal for a second time interval to analyze the RF signal over the second time interval to detect a valid modulation of the RF signal. In response to detecting a valid modulation of the RF signal during the second time interval, the receiver is enabled to establish a communication session with a transmitting device.

Abstract: In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.

Abstract: Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.

Abstract: A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronisation stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.

Abstract: In one embodiment, an apparatus may include a de-serializer to convert serial data to parallel data, and a counter to provide an update signal based on a bit count of the serial data. The apparatus may further include a synchronizer to provide a synchronization signal when a target clock signal is synchronized with the update signal. The apparatus may further include an output unit to provide a validation indicator in response to the synchronization signal.

Abstract: An apparatus for acquiring synchronization in a multi-channel system includes a signal reception unit for receiving information about repetition patterns of signal streams for each channel and receiving the signal streams and data from the channel, an estimated synchronization point tracking unit for determining a estimated synchronization point for the channel from a point of time where the repetition patterns are ended by tracking a period where the signal streams are repeated based on the repetition patterns, and a synchronization acquisition unit for searching, based on the estimated synchronization point related to the channel, for a point where the repetition of the signal stream is ended or a point where new signal streams are started and acquiring a synchronization point based on the point.

Abstract: A method of feedforward phase recovery on a data stream is described. Phase estimation base points are calculated, at a phase detector, for each block of the received data stream. A current phase, at a phase interpolator, between two phase estimation base points. Data stream delays within the phase detector are matched with delays within the phase interpolator.

Abstract: Certain aspects of the present disclosure provide techniques for reducing the amount of storage needed for detecting a primary synchronization signal (PSS). According to certain aspects, a user equipment may store a limited number of samples corresponding to the strongest peaks per PSS index and perform PSS detection based on an analysis of the limited number of stored samples.

Abstract: A source device includes: a low-speed data supply section configured to supply, as low-speed data, data generated in synchronization with a low clock signal out of clock signals having different frequencies, the low clock signal having a frequency lower than a predetermined value; a high-speed data supply section configured to supply, as high-speed data, data generated in synchronization with a high clock signal out of the clock signals, the high clock signal having a frequency higher than that of the low clock signal; a dividing section configured to divide the low-speed data into a predetermined number of pieces of data in accordance with a ratio between the frequencies of the high and low clock signals; and a data transmitting section configured to store the high-speed data and the divided pieces of low-speed data in data having a predetermined data size, and to transmit the stored data.

Abstract: A sampling phase selection method for a data stream is provided, wherein the data stream has a variable data rate in a fixed time period. The method comprises generating a calibration signal, wherein the time interval of the calibration signal is longer than the fixed time period of the data stream, generating a first clock sequence and a subsequent second clock sequence, wherein the first and the second clock sequence are composed of a plurality of continuous clock phases and the number of the clock phases of the first clock sequence are the same as that of the clock phases of the second clock sequence, selecting one of the phases of the first and the second clock sequence, in turn, to provide a sampling phase, performing a plurality of samplings on the data stream to generate a flag signal, and selecting a final sampling phase according to the flag signals with different sampling phases.

Abstract: An apparatus includes Radio Frequency (RF) circuitry and baseband circuitry. The RF circuitry is configured to receive strobe messages that are based on a system clock over a digital interface, and to communicate synchronously with the system clock based on the received strobe messages in accordance with a Radio Access Technology (RAT) that is selected from among multiple different RATs. The baseband circuitry is configured to generate the strobe messages, to delay the strobe messages by a delay that depends on the selected RAT, and to send the delayed strobe messages to the RF circuitry over the digital interface.

Abstract: Systems and methods for discrete signal synchronization based on a known bit pattern are described. In one aspect of the present subject matter, a discrete signal synchronization system is configured to synchronize a preprocessed discrete signal with a modified discrete signal. The system comprises a processor and a synchronization module coupled to the processor. The synchronization module comprises an extraction module and comparison module. The extraction module determines a bit pattern from the modified discrete signal using Discrete Wavelet Transformation (DWT) and Singular Value Decomposition (SVD). The comparison module compares the determined bit pattern with a known bit pattern of the preprocessed discrete signal and records a time point at which the determined bit pattern matches with the known bit pattern of the preprocessed discrete signal as a synchronization point.

Abstract: A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to marry up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.

Abstract: The invention relates according to a first aspect to a device (1) for reconstructing a clock signal from a baseband serial signal (NRZ-D), comprising: —a pulse generating circuit (2) adapted for generating pulses at each transition, rising or falling, of the baseband serial signal (NRZ-D); —a phase-locked loop (5) comprising a voltage-controlled oscillator (6) which generates an oscillator output signal (VCO-S) and a filter (7) delivering a setpoint signal (VCO-E) to the oscillator (6), the phase-locked loop (5) furthermore comprising a breaker (8) interposed between the oscillator (6) and the filter (7), the switching of which is controlled by the output (Cde-S) of the pulse generating circuit (2), and in that the filter (7) is a low-pass filter, such that: —in the presence of a pulse generated by the pulse generating circuit (2), the breaker (8) is closed and the filter (7) then averages the oscillator output signal (VCO-S) passing through the breaker so as to deliver the setpoint signal (VCO-E) to the osci

Abstract: Various systems and methods for comparing media signals are disclosed. In some embodiments, media signals are compared by identifying characteristic features in the respective signals and then analyzing the characteristic features to determine if the signals contain corresponding content. In other embodiments, the characteristic features are analyzed to determine the extent to which the signals are synchronized in time.

Abstract: An apparatus for synchronizing audio data and visual data and a method therefor are provided. The apparatus includes a splitter, a synchronization unit coupled to the splitter, an audio control unit coupled to the splitter and the synchronization unit, and a visual data processing unit coupled to the splitter and the synchronization unit. The splitter receives an application layer data frame including audio data and visual data and splits the visual data from the audio data. The synchronization unit receives audio timing information of the audio data and acquires synchronization information according to the audio timing information and external timing information. The audio control unit receives and temporarily stores the audio data and outputs the audio data according to the synchronization information. The visual data processing unit analyzes and temporarily stores the visual data and outputs the visual data together with the audio data according to the synchronization information.

Abstract: A system including an input module, a first gain module, a second gain module, and a preamble estimation module. The input module is configured to receive an input signal from a station. The input signal includes (i) a first preamble sequence, and (ii) subcarriers. The first gain module is configured to, based on the input signal, generate first channel gain values. Each of the first channel gain values is for a respective one of the subcarriers. A second gain module is configured to, based on the first channel gain values, generate second channel gain values. A preamble estimation module is configured to estimate the first preamble sequence based on (i) the first channel gain values, and (ii) the second channel gain values.

Abstract: A communication apparatus having a first and second wireless communications modules is provided. The first wireless communications module includes a receiving unit receiving RF signals from an air interface, a signal processing module performing frequency down conversion on the RF signals to generate baseband signals according to a clock signal, and a processor processing the baseband signals. The processor further detects an ON/OFF status of the second wireless communications module to obtain a detection result and compensates for frequency drift of the clock signal according to the detection result.

Abstract: According to one embodiment, a channel phase estimation apparatus includes a phase memory, subtractor, multiplier, and adder. The phase memory is configured to store a first phase estimation value up to a (k?1)-th (for k=1, 2, . . . , K) symbol. The subtractor is configured to calculate a difference value between a phase value of one carrier of a k-th symbol and the first phase estimation value. The multiplier is configured to multiply the difference value by a weight. The adder is configured to add a value output from the multiplier and the first phase estimation value to output a second phase estimation value up to the k-th symbol.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of clock distribution. For example, a device may include a plurality of wireless communication units including at least a first wireless communication unit, which includes a first clock source to generate a first clock signal, and a second wireless communication unit, which includes a second clock source to generate a second clock signal, wherein the plurality of wireless communication units are to switch between commonly using the first clock signal as a common master clock signal and commonly using the second clock signal as the common master clock signal.

Abstract: A signal delay estimator includes an adjustable delay element for delaying a first signal to obtain a delayed first signal, a delay amount estimator for estimating a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal, and a leading signal determiner for determining whether the delayed first signal leads the second signal or vice versa, and for generating a corresponding binary signal. A selective inverter is provided for selectively inverting the delay amount depending on the binary signal. The signal delay estimator also includes a feedback element to the adjustable delay element for controlling a delay based on an output of the selective inverter. Another exemplary signal delay estimator includes a closed control loop with an adjustable delay element and separate first and second processing paths for absolute delay amount and delay direction, respectively.

Abstract: It is disclosed a network element for a communication network configured to synchronize its local clock to a reference clock signal. The network element comprises: a main board comprising an internal module configured to support an internal synchronization transport protocol, and a connector connected to the internal module; and a pluggable module configured to be removably connected to the connector. The pluggable module is configured to, when connected to the connector: exchange external synchronization information with a further network element, the external synchronization information being formatted according to an external synchronization transport protocol different from the internal synchronization transport protocol; exchange with the internal module internal synchronization information formatted according to the internal synchronization transport protocol; and interface the internal synchronization transport protocol and the external synchronization transport protocol.

Abstract: Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.

Abstract: A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.

Abstract: A signal delay estimator includes an adjustable delay element for delaying a first signal to obtain a delayed first signal, a delay amount estimator for estimating a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal, and a leading signal determiner for determining whether the delayed first signal leads the second signal or vice versa, and for generating a corresponding binary signal. A selective inverter is provided for selectively inverting the delay amount depending on the binary signal. The signal delay estimator also includes a feedback element to the adjustable delay element for controlling a delay based on an output of the selective inverter. Another exemplary signal delay estimator includes a closed control loop with an adjustable delay element and separate first and second processing paths for absolute delay amount and delay direction, respectively.

Abstract: A sequence generation method for allowing a reception end to effectively detect a sequence used for a specific channel of an OFDM communication system, and a signal transmission/reception method using the same are disclosed. During the sequence generation, an index is selected from among the index set having the conjugate symmetry property between indexes, and a specific part corresponding to the frequency “0” is omitted from a transmitted signal. In addition, a reception end can calculate a cross-correlation value between a received (Rx) signal and each sequence using only one cross-correlation calculation based on the conjugate symmetry property.

Abstract: Techniques for de-modulating a high-supply-domain differential signal and a common-mode clock in a front-end receiver are described herein. In one embodiment, a method for receiving a signal comprises receiving the signal via a receiver input, the received signal comprising a differential signal and a common-mode clock signal. The method also comprises shifting the received signal from a first voltage range to a second voltage range that is lower than the first voltage range, and providing the shifted received signal on a first level-shifted signal line and a second level-shifted signal line. The method further comprises sensing voltage differences between the first and second level-shifted lines to recover the differential signal, and sensing common-mode voltages on the first and second level-shifted signal lines to recover the common-mode clock signal.

Abstract: A compensating device for detecting and compensating for a sampling clock offset in a receiver. An SCO detector includes multiple calculation paths and a controller. Each calculation path receives a time domain signal and a hypothetic offset, calculates correlation coefficients between the time domain signal and a delayed version of the time domain signal according to a predetermined delay and the hypothetic offset, calculates correlation coefficient sums according to the correlation coefficients, and extracts a maximum correlation coefficient sum for the hypothetic offset from the correlation coefficient sums. The controller is coupled to the calculation paths for providing different hypothetic offsets to each calculation path and detects the SCO according to the maximum correlation coefficient sums obtained from the calculation paths. An SCO compensator receives the SCO and compensating for the SCO on a signal generated in a signal processing path of a receiver.

Abstract: Aspects of the disclosure provide methods and apparatuses that use counter based phase signaling to transmit digital data. The counter based phase signaling uses a reduced number of transitions to transmit a large number of bits. A method of counter based phase signaling includes transmitting a reference transition to start multiple-bit data block transmissions from a transmitter module to a receiver module, starting a first counter to count in accordance with a first clock of the transmitter module, and transmitting a first data transition corresponding to transmitting a first multiple-bit data block from the transmitter module to the receiver module when a counted number by the first counter corresponds to the first multiple-bit data block. The first clock has a same frequency as a second clock in the receiver module.

Abstract: Some of the embodiments of the present disclosure provide a method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain. Other embodiments are also described and claimed.

Abstract: Systems and methods are described including receiving a clock signal, using rational clock divider (RCD) logic to generate a lower frequency clock signal in response to the received clock signal, and using the second clock signal to drive software timer logic and generate media timestamps.

Abstract: A tracking method and apparatus of a communication system to prevent a timing difference and bit error rate performance degradation caused by unstable characteristics of a plurality of circuit devices are provided. The tracking method and apparatus include sampling signals received at receiving antennas, tracking sample values resulting from the sampling of the signals, and combining the tracked sample values.

Abstract: Circuits and techniques for operating an integrated circuit (IC) are disclosed. A disclosed circuit includes a divider circuit that is operable to receive a first signal at a first speed and output a second signal at a second speed based on the first signal. A recovery circuit is coupled to the divider circuit. The recovery circuit is operable to determine the frequency of the second signal and is further operable to generate a first ready signal and a recovered clock signal based on the second signal. A phase aligner circuit, operable to align a phase of the second signal with a phase of the recovered clocks signal based on the first ready signal, is coupled to the recovery circuit.

Abstract: A high sensitivity GPS receiver includes an acquisition engine and a tracking engine. The acquisition engine processes GPS satellite data at data rate that is substantially equal to twice the coarse acquisition (CA) code chip rate. This data rate advantageously enables the acquisition engine to process GPS satellite data with relatively less hardware area than traditional GPS acquisition approaches. In one embodiment, the high efficiency acquisition engine may be over-clocked, thereby allowing different phases of a CA code to be correlated quickly. The tracking engine can advantageously process GPS satellite data at a data rate that does not have an integer relationship to the CA code chip rate.

Abstract: An audio data receiving apparatus includes a receiving unit configured to receive audio data sampled in accordance with a first clock signal; a synchronization unit configured to generate a second clock signal that is synchronized with the first clock signal by extracting clock components contained in the audio data; a demodulator configured to demodulate the audio data in accordance with the second clock signal; an oversampling unit configured to oversample the audio data demodulated by the demodulator by using a frequency higher than a frequency of the second clock signal; a clock generator configured to generate a third clock signal having a frequency nearly equal to the first clock signal; and a data output unit configured to output the audio data oversampled by the oversampling unit in accordance with the third clock signal generated by the clock generator.

Abstract: The present invention relates to a phase error estimator, a coherent receiver and a phase error estimating method. The phase error estimator estimates a phase error in an inputted base band electric signal and feeds back said phase error; said phase error estimator comprises: a pre-decider, for judging a phase of data in said base band electric signal in accordance with said feedback phase error; a phase error complex value extracting section, for extracting a real part and an imaginary part of the phase error in accordance with the judgment result of said pre-decider; a phase error determining section, for determining said phase error in accordance with the real part and the imaginary part of the phase error extracted by the phase error complex value extracting section; and a time delay feeding back section, for delaying said phase error by N number of symbols and feeding back the delayed phase error to said pre-decider, wherein N is an integer greater than 1.

Abstract: A data communication system comprises a transmitting device which transmits data and a receiving device which receives the data. The transmitting device comprises a clock generating circuit and a transmitting unit. The clock generating circuit generates a clock having a temperature characteristic in that a clock frequency varies with temperature. The transmitting unit transmits data generated in synchronization with the clock to the receiving device. The receiving device comprises a receiving unit, a detecting unit, a storage unit, and a calculating unit. The receiving unit receives the data. The detecting unit detects the clock frequency from the data. The storage unit stores temperature characteristic information regarding the temperature characteristic of the clock frequency. The calculating unit calculates a temperature corresponding to the clock frequency based on the clock frequency and the temperature characteristic information.

Abstract: A receiving apparatus includes a symbol timing detection unit, a Fourier transform unit, a first symbol timing correction unit, and an interpolation synthesis unit. The symbol timing detection unit is configured to detect a Fourier transform start position from a received transmitting signal of a symbol unit, the Fourier transform unit is configured to perform a Fourier transform using the detected Fourier transform start position. The first symbol timing correction unit is configured to calculate and correct an amount of change between the Fourier transform start position of a reference symbol and the detected Fourier transform start position, and the interpolation synthesis unit is configured to perform an interpolation synthesis of a plurality of delay profiles corresponding to a plurality of symbols including the reference symbol and a symbol in which the amount of change is corrected.

Abstract: A method of synchronizing a compound Super Speed USB device, comprising: providing data communication between a host computing device and the compound Super Speed USB device across the Super Speed USB communication channel; establishing a Super Speed USB communication channel to a Super Speed USB function of the compound USB device; establishing a non-Super Speed synchronization channel to a non-Super Speed USB function of the compound USB device; and synchronizing a local clock of the compound USB device to a periodic data structure within a data stream in the non-Super Speed synchronization channel so that the local clock can enable synchronous operation of the compound USB device with one or more comparable USB devices.