Abstract: A data alignment method is provided by iteratively increasing the delay of each data input line of a system component until a test signal transmitted on each data input line is received at the system component at substantially a predetermined time.

Abstract: Disclosed is a method and system to help facilitate transition from broadcast to unicast. A broadcast server provides a copy of session content to a unicast gateway, and a content-synchronizer keeps track of which UEs are broadcast recipients and what the progress of the broadcast is over time. In response to unicast attachment of a UE with the unicast gateway, as when the UE moves from broadcast coverage to unicast coverage, the unicast server determines based on information from the content synchronizer (i) that the UE is a broadcast recipient and (ii) the progress of the broadcast so far. The unicast gateway then begins transmitting to the UE the media content received from the broadcast server, starting at a point in the media content based on the determined progress. This process may thereby help to facilitate a seamless transition from broadcast to unicast, with at most a brief interruption.

Abstract: Provided is a data synchronization apparatus. The data synchronization apparatus includes a signal conversion block converting individual serial digital signals into parallel digital signals in response to a load signal and converting the parallel digital signals into synchronized serial digital signals in response to a synchronization load signal which does not overlap the load signal, a clock/load signal generator outputting a reference load signal for generating the synchronization load signal to the signal conversion block, a multiplexer multiplexing the synchronized serial digital signals, and a first serial-to-parallel (S/P) converting the multiplexed signal into parallel signals.

Abstract: A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.

Abstract: Method for controlling a bus system having at least two users, a first user repeatedly transmitting a reference message in at least one predeterminable time interval over the bus system, the reference message being triggered by time trigger information when the time information reaches a time mark assigned to the trigger information, wherein the time mark is altered at least once in such a way that when the time information reaches the altered time mark, time shifting of the trigger information occurs.

Abstract: A multi-channel audio signal converting device using a time-varying digital filter, an electronic system including the same, and a method of converting an audio signal using the time-varying digital filter are provided. The multi-channel audio signal converting device includes a first signal channel and a second signal channel configured to perform analog-to-digital conversion or digital-to-analog conversion using a first clock signal; and a first time-varying filter configured to synchronize a digital audio signal synchronized with a second clock signal different from the first clock signal with the first clock signal and to input the digital audio signal to the second signal channel when digital-to-analog conversion is performed or to synchronize an output signal of the second signal channel with the second clock signal when analog-to-digital conversion is performed.

Abstract: Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die generates a forwarded signal, synchronous to the forwarded clock that identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge. A phase locked loop (PLL) on a second die is coupled to receive the reference clock signal, the PLL to generate a local clock signal. A circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock.

Abstract: Disclosed in some examples is a user-equipment including a transceiver; one or more processors configured to: provide a first mobile personality associated with a first mobile application executing on the one or more processors; provide a second mobile personality associated with a second mobile application executing on the one or more processors; and provide a first virtual mobile device associated with the first mobile personality and a second virtual mobile device associated with the second mobile personality, wherein the first and second virtual mobile devices provide independent connectivity to the first and second mobile applications via the transceiver.

Abstract: Initialization in multiple clock domains. A first die having a master initialization component generates initialization commands. A local initialization agent on the first die is coupled to receive the initialization commands. The local initialization agent manages initialization of one or more components on the first die. A remote initialization agent on a second die is coupled to receive the initialization commands. The remote initialization agent manages initialization of one or more components on the second die. The master initialization component receives acknowledgement messages from the local initialization agent and the remote initialization agent to manage conflicts and dependencies between the local initialization agent and the remote initialization agent and synchronizes events in multiple clock domains that share a reference clock signal by signaling in the reference clock domain.

Abstract: Disclosed is a system and method for monitoring PCIe packets between clock domains. An interrupt is set to a root complex or external hardware based on the detection of malformed, and illegal, packets.

Abstract: A method and a mobile device are adapted to transmit data through short-range communication based on movement of the mobile device. External mobile devices near the mobile device are searched. Location information for each external mobile device found near the mobile device is acquired. Data to be transmitted is set. The movement of the mobile device is recognized. At least one target mobile device is set to receive data, based on the movement of the mobile device and the acquired location information of the found external mobile devices. And the data is transmitted to the at least one target mobile device.

Abstract: Each of nodes in a communication system includes a pull-up circuit connected between a power source and a transmission line and a switching portion connecting and disconnecting the transmission line and a ground line. One of the nodes is a master node, and the others of the nodes are slave nodes. The driver circuits are driven so that the master node constantly outputs the transmission code of logic 1 and the slave node outputting the transmission code of logic 0 extends the width of the low level of the transmission code of logic 1 on the transmission line. The master node further includes a current limiting section limiting an electric current that flows to the transmission line via the pull-up circuit based on at least a signal level of the transmission line.

Abstract: A method according to one embodiment includes receiving a serialized data stream; detecting rising and falling edges in the serialized data stream; correlating the rising and falling edges to data values using a clock signal that is not derived from the serialized data stream; and converting the serialized data stream to a parallel data stream. In a further embodiment a system includes a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a serialized data stream; detect rising and falling edges in the serialized data stream; correlate the rising and falling edges to data values using a clock signal that is not derived from the serialized data stream; and convert the serialized data stream to a parallel data stream.

Abstract: A phase shift circuit may include a ramp generation unit charging or discharging a capacitor connected to a switch device to generate a ramp signal, a reference signal generation unit generating a predetermined reference signal from the ramp signal, and a comparison unit comparing the ramp signal with the reference signal to generate a clock signal, wherein at least one of the reference signal generation unit and the comparison unit changes a negative or positive value of offset components included in the reference signal or the ramp signal within every operating period of the switch device.

Abstract: A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases, wherein any two phases of the set of phases are different from each other; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital weighting control signals, wherein the phase shift corresponds to the set of digital weighting control signals, and the set of digital weighting control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital weighting control signals.

Abstract: In the field of the broadcasting of digital services intended for terminals retrieving these services, the concern is with the problem of synchronization in the context of a network transmitting on a single modulation frequency and the reliability of the broadcasting channel by redundancy of equipment. The present invention proposes a broadcasting system having a duplicated formatting module. This system enables a modulator to switch between the two streams generated by the two formatting modules without becoming desynchronized. These formatting modules are synchronized with each other in order to generate synchronized streams. Thus, when a modulator is caused to switch from a first stream generated by one of the formatting modules onto a second stream generated by a second formatting module, this switching can be effected without requiring a resynchronization step.

Abstract: An apparatus for detecting an in-vehicle network attack, is configured to cumulatively count packets for each device that has a respective ID and is connected to an in-vehicle network bus. The apparatus is configured to cumulate a check value every time the packets are cumulatively counted to calculate a cumulated value, and determine that an attack is conducted when an average cumulated value obtained by dividing the cumulated value by a cumulative counted value does not exceed a first threshold value.

Abstract: Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.

Abstract: A radio communication system, including: a base station apparatus; and a terminal apparatus, wherein the base station apparatus and the terminal apparatus transmits to or receives from the terminal apparatus and the base station apparatus respectively a radio signal by using a plurality of frequency bands as a transmission frequency or a reception frequency, the base station apparatus includes a transmission unit which transmits a synchronization signal or a reference signal in each frequency band of the plurality of frequency bands, and the terminal apparatus includes a synchronization control unit which selects at least one synchronization signal or reference signal from the plurality of synchronization signals or reference signals transmitted from the base station apparatus and performs synchronization control based on the selected synchronization signal or reference signal.

Abstract: A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).

Abstract: Systems and methods for acquiring seismic data are described, one system comprising one or more seismic sources, a plurality of sensor modules each comprising a seismic sensor configured to sample analog seismic data, each module comprising a comparing unit comprising software; wherein the software in each module tests clock quality by running a sigma-delta modulator from two different clock sources in the node and compares a noise-floor of the modulator when using the different clocks.

Abstract: A communication system performs communication using a pulse width modulation code as a transmission code. The communication system includes a plurality of nodes that are connected via a transmission line to be capable of communicating with each other. Each of the nodes including a driver circuit. The driver circuit includes a transistor that enables and blocks conduction between the transmission line and a ground line. The plurality of nodes includes a master node and a slave node. The master node is one of the plurality of nodes. The slave node is at least one node other than the master node among the plurality of nodes. The master node includes a limiter that restricts, when the transistor of the driver circuit is turned off, changes in a conductive state of the transistor.

Abstract: The present patent application improves DARP by allowing multiple users on one time slot (MUROS). It comprises means and instructions for signaling training sequence set information to a remote station, comprising receiving signaling from a remote station indicating if a new set of training sequences is supported, and using a channel description to signal the training sequence set to be used by the remote station for a communication channel being established. Other aspects, embodiments, and features are also claimed and described.

Abstract: Instead of performing a complete frequency scan and a subsequent cell scan on detected candidate frequencies, according to the method for searching for a PLMN as disclosed herein, the frequency scan is interrupted for performing an immediate cell scan based on inspection results for a specific candidate frequency obtained during the frequency scan. During the cell scan, the bandwidth among other parameters of the cell may be detected. Based on the detected bandwidth, certain candidate frequencies falling into the detected bandwidth can be skipped when resuming the frequency scan.

Abstract: Embodiments of the present disclosure provide a synchronization method, device, and system, and relate to the field of communications, so that a device deployment cost may be reduced and the stability of device synchronization may be improved. The method includes: acquiring, by a switching node, synchronization time from a main control node; and sending, by the switching node, the synchronization time to each controlled node that is connected to the switching node, so as to perform time synchronization between each controlled node and the main control node.

Abstract: Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resin ling from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.

Abstract: A system is described for maintaining synchrony of operations among a plurality of devices having independent clocking arrangements. A task distribution device is to distribute tasks to a synchrony group comprising a plurality of devices to perform tasks distributed by the task distribution device in synchrony. The task distribution device distributes each task to synchrony group members over a network. Each task is associated with a time stamp that indicates a time, relative to a clock maintained by the task distribution device, at which synchrony group members are to execute the task. Each synchrony group member periodically obtains from the task distribution device an indication of current time indicated by its clock, determines a time differential between the task distribution device's clock and its respective clock and determines there from a time at which, according to its respective clock, the time stamp indicates that it is to execute the task.

Abstract: Aspects of the present disclosure are directed to communications between devices. As consistent with one or more embodiments, a local device has a first clock, a low-frequency (LF) transmitter and a high-frequency (HF) transceiver. A remote device includes a second clock, a LF receiver and a HF transceiver. An LF signal is transmitted from the local device to the remote device and used to synchronize the second clock. The first clock is synchronized based on an HF signal transmitted to the local device using the synchronized second clock and a first predetermined time delay relative to receipt of the LF signal. The second clock is re-synchronized based on a second HF signal transmitted to the remote device using the first clock and a second predetermined time delay relative to receipt of the first HF signal, while accounting for a trip time for communicating one or both of the HF signals.

Abstract: An interleaver (ER) is dedicated to interleaving of interleaving units representing a selected number of services grouped into periodic frames within a long period time interleaving radio communication network. The said interleaver (ER) comprises processing means (MT1) responsible for decomposing each frame into a chosen number of group(s) of service of constant respective durations, and then for distributing the interleaving units of each group into so-called spreading time intervals of constant respective durations spaced apart within a time interleaving period according to a period equal to the period of the frames.

Abstract: A control/monitor signal transmission system that employs a transmission synchronization scheme in which a master station connected to a single control unit and a plurality of slave stations corresponding to a plurality of controlled apparatuses synchronize with each other through a transmission clock and data is transmitted therebetween over a common data signal line, a transmission line disconnection detection method that enables a disconnection of a transmission line to be detected precisely; and a slave station that is used for this method. A continuous pulse signal that the master station outputs to the common data signal line is provided with a management data region that includes a plurality of pulse signals and that differs from a control/monitor data region including data of a control data signal and data of a monitor data signal.

Abstract: A time information obtaining device and a radio-controlled timepiece are shown. According to one implementation, the time information obtaining device includes a receiving section, a code identifying section, a decoding section, and a consistency confirming section. The consistency confirming section confirms consistency of time information. The consistency confirming section generates the selected code string using the following: (i) a matching selected code string portion in which, for a code string portion including a code which may change according to the time information, a type of code is selected based on a degree of match between an identified code string and a model code string; and (ii) a majority selected code string portion in which, for a portion other than the above, a type of code is selected by majority determination among the codes identified to be a same position.

Abstract: A method of managing timing alignment (TA) functionality in multiple component carriers for a communication device of a wireless communication system, which includes separately managing TA functionality of a plurality of component carriers or jointly managing TA functionality of component carriers belonging to the same cell.

Abstract: An apparatus for aligning non-synchronous input data streams received in the apparatus, the apparatus comprising an analog to digital converter arrangement for digitizing the data streams into a plurality of sequences of samples; and a synchronization processing arrangement for generating alignment pulses for each sequence of the plurality of sequences of samples, for arranging each sequence of samples with respect to the alignment pulses for the sequence and for synchronization the delivery of said plurality of sequences of samples to a common processor with respect to the respective alignment pulses. The synchronization processing arrangement may comprise a processing chain for each antenna feed of said plurality of antenna feeds and each processing chain may comprise an alignment pulse generator for generating an alignment pulse for the sequence of samples corresponding to the processing chain. The input data streams may be received by a plurality of antenna feeds.

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract: A method and apparatus is disclosed to process a received single stream communication signal and/or a multiple stream communication. A communications receiver is configured to receive the received communication signal. A communications receiver determines whether the received communication signal includes a single stream communication signal or a multiple stream communication signal. The communications receiver determines whether a received communication signal complies with a known single stream communications standard. The communications receiver determines whether the received communication signal complies with a known multiple stream communications standard. The communications receiver decodes the received communication signal according to the known single stream communications standard upon determining the received communication includes the signal single stream communication signal.

Abstract: A method is described for synchronizing a clock of a client in a packet based communication network with respect to a reference time provided by a timeserver. Packets containing at least one timestamp indicating a sending time of the packet are sent from the timeserver and received at the client. Upon arrival of each packet at the client, the arrival time is determined and the delay between the timestamp and the arrival time is also determined for a first plurality of packets. A first variation of the delays of these packets is calculated and based on this calculation a first observation frame is defined whose size depends on the first variation of the packet delays. The first observation frame comprises a second plurality of delays associated with the first plurality of delays. Further, a first representative delay based on the second plurality of delays is determined.

Abstract: Embodiments provide systems and methods for aligning the supply voltage signal applied to a power amplifier (PA) with the radio frequency (RF) output signal of the PA in a wireless device. The RF output signal is generated by applying a transmit signal to a transmit path of the wireless device. The supply voltage is generated by applying an envelope tracking (ET) signal, based on the transmit signal, to an envelope tracking (ET) path of the wireless device. Embodiments operate by estimating the delays of the ET path and the transmit path, and then controlling a relative delay between the transmit signal and the ET signal accordingly. In an embodiment, estimation of the delays of the ET path and the transmit path is done by correlating respective signals of each path.

Abstract: An echo cancellation device relies on the known characteristics of the sync frame to monitor, update in an off-line fashion and determine the accuracy of an echo canceller in, for example, a modem, such as an ADSL modem. Specifically, time domain samples are read from the transmit (Tx) and receive (Rx) paths of the modem. These samples are stored in memory. When the sync frame has received a predetermined number of the same Tx samples and Rx samples, the samples are stored. Running averages, over the sync frames, of the TX and RX samples are maintained. These averages are subtracted from a sync frame of samples, to allow LMS updating of the echo canceller taps, free of extraneous signals. Updating, i.e., tracking of changes in the echo channel, is done for the echo canceller in an off-line fashion. The coefficients for the in-line version are updated, while the off-line version is updated over several sync frames. Periodically, the performance of the off-line version is compared with the in-line version.

Abstract: A signal synchronizing device includes a trigger module for capturing an input signal according to a first clock signal which corresponds with the input signal so as to generate a trigger signal, a storage unit for forming a first pulse signal by pulling an output thereof to a first logic level according to the trigger signal, and by pulling the output thereof to a second logic level according to a feedback reset signal, and a synchronizing module for performing synchronous transfer according to the first pulse signal so as to output an output signal corresponding with frequency of a second clock signal, and for generating the feedback reset signal according to the output signal.

Abstract: Testing a digital system includes calculating a first ratio of a first clock frequency for a first clock domain and a second clock frequency for a second clock domain different from the first clock domain using a processing device and calculating a first offset between a first timer in the first clock domain and a second timer in the second clock domain. Using an expression dependent upon the first offset and the first ratio, event data from at least one of the first clock domain or the second clock domain is converted to a common clock domain.

Abstract: A method, system and apparatus to provide a solution of PLL locking issue in the daisy chained memory system. A first embodiment uses consecutive PLL on based on locking status of backward device on the daisy chained memory system with no requirement of PLL locking status checking pin. A second embodiment uses Flow through PLL control with a locking status pin either using an existing pin or a separated pin. A third embodiment uses a relocking control mechanism to detect PLL relocking from the device. A fourth variation uses flag signal generation to send to the controller.

Abstract: In a data recovery circuit, a sampling circuit is configured to sample data using a plurality of sampling clock signals having different phases relative to one another and to output a plurality of sampled data. A recovery data generation circuit is configured to perform a logic operation on the plurality of sampled data and to generate a plurality of intermediate recovery data according to a result of the logic operation. A recovery circuit is configured to check the plurality of intermediate recovery data for existence of an error and to output intermediate recovery data that is error-free, among the plurality of intermediate recovery data, as recovery data.

Abstract: A transceiver with non-deterministic delay characteristics is analyzed and adjusted to provide a transceiver with deterministic delay characteristics. The transceiver may be implemented with a variety of device types to support high bandwidth operation over a wide range of frequencies. Deterministic behavior allows use of the transceiver in source synchronous interfaces. The transceiver may also be dynamically analyzed and adjusted during operation as operation frequency changes.

Abstract: An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a frequency of a second clock (ck fast) in the second clock domain (bus_fast). The arrangement is configured to transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast), detect whether a predetermined transition occurs in the first clock (ck slow) within a predetermined period of time, using detecting means (2) clocked by the second clock (ck fast), and transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast) again if the detecting means (2) detects the predetermined transition in the first clock (ck slow) within the predetermined period of time.

Abstract: Power consumption when reception is carried out in response to a reception instruction by a user is reduced in a satellite radio-controlled wristwatch.

Abstract: A modem and a method of placing a modem in an online data state. In one embodiment, the modem includes: (1) a digital interface configured to receive, via an AT channel thereof, a standard AT command directing an AT channel of the modem to exit a command state and enter an online data state and (2) a command processor coupled to the digital interface and configured to: extract channel designation data received as a standard parameter of the standard AT command, cause a channel designated by the channel designation data and separate from the AT channel to enter the online data state, and allow the AT channel to remain in the command state.

Abstract: A method performed by a device for performing synchronization between devices for a Device-to-Device (D2D) communication is provided. The method includes setting, according to a process of the device, the device to a group of devices for performing a dynamic switching; outputting a synchronization signal corresponding to the set group as a signal for setting synchronization in a physical layer; controlling, upon receiving another synchronization signal from another device, the outputting of the synchronization signal by applying a time offset according to a relation between the set group that includes the device and the group that includes the another device; and setting, if the synchronization signal and the another synchronization signal are converged, synchronization of the device based on a time point where the synchronization signal is output.

Abstract: An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock, and uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.

Abstract: A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the system time is determined from an output clock signal of the system clock generator by counting, in which the system clock generator is deactivated in a sleep mode, in which an output clock signal of a sleep clock generator is blanked as a function of an output signal of a modulo divider in the sleep mode, and the system time is determined by counting, wherein an output frequency of the output clock signal of the sleep clock generator is a non-integer multiple of a symbol frequency, in which the modulo divider divides the output clock signal of the sleep clock generator by a division factor, and in which the division factor of the modulo divider is produced by changing between at least two integer divisor values.

Abstract: A multi-port information communication system includes a reference clock signal generator configured to generate a reference clock signal. The system also includes a phase controller configured to generate a plurality of information communication clock signals based on the reference clock signal by staggering a phase of each of the information communication clock signals. The phase controller includes a delay-locked loop configured to generate a plurality of delay-locked loop signals based on the reference clock signal, and a plurality of time delay elements. Each time delay element is configured to produce a respective one of the information communication clock signals by adding a respective delay to a respective one of the delay-locked loop signals. The system includes information communication devices each including a respective transmitter. Each of the transmitters is configured to operate in response to a respective one of the information communication clock signals.