And Additional Electrical Device Patents (Class 438/200)
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Patent number: 8962368Abstract: The present invention relates to a CMOS compatible MEMS microphone, comprising: an SOI substrate, wherein a CMOS circuitry is accommodated on its silicon device layer; a microphone diaphragm formed with a part of the silicon device layer, wherein the microphone diaphragm is doped to become conductive; a microphone backplate including CMOS passivation layers with a metal layer sandwiched and a plurality of through holes, provided above the silicon device layer, wherein the plurality of through holes are formed in the portions thereof opposite to the microphone diaphragm, and the metal layer forms an electrode plate of the backplate; a plurality of dimples protruding from the lower surface of the microphone backplate opposite to the diaphragm; and an air gap, provided between the diaphragm and the microphone backplate, wherein a spacer forming a boundary of the air gap is provided outside of the diaphragm or on the edge of the diaphragm.Type: GrantFiled: July 24, 2013Date of Patent: February 24, 2015Assignee: Goertek, Inc.Inventor: Zhe Wang
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Publication number: 20150035072Abstract: A method includes forming a first gate oxide in a first region and in a second region of a wafer. The method further includes performing first processing to form a second gate oxide in the second region. The second gate oxide has a different thickness than the first gate oxide. The method also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region. The first device corresponds to a first radio frequency (RF) band and the second device corresponds to a second RF band that is different from the first RF band.Type: ApplicationFiled: August 5, 2013Publication date: February 5, 2015Applicant: QUALCOMM IncorporatedInventors: Ranadeep Dutta, Choh Fei Yeap
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Patent number: 8921190Abstract: A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.Type: GrantFiled: April 8, 2008Date of Patent: December 30, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Alvin J. Joseph, Stephen E. Luce, John J. Pekarik, Yun Shi
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Publication number: 20140367791Abstract: A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an opposite conductivity type of the first conductivity type which is formed at a second region and is electrically connected to a second power supply line, a third well in the second conductivity type which is integrally formed with the second well at a third region adjacent to the second region, a fourth well in the first conductivity type integrally formed with the first well at a fourth region adjacent to the first region, a fifth well in the first conductivity type which is formed at the third region to be shallower than the third well, and a sixth well in the second conductivity type which is formed at the fourth region to be shallower than the fourth well, are included.Type: ApplicationFiled: June 3, 2014Publication date: December 18, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Akira Katakami
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Publication number: 20140335669Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.Type: ApplicationFiled: June 17, 2014Publication date: November 13, 2014Inventors: Daniel R. Shepard, Mac D. Apodaca, Thomas Michael Trent, James Juen Hsu
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Patent number: 8883624Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.Type: GrantFiled: March 28, 2014Date of Patent: November 11, 2014Assignee: Cypress Semiconductor CorporationInventor: Krishnaswamy Ramkumar
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Publication number: 20140319616Abstract: At least one MOS transistor is produced by forming a dielectric region above a substrate and forming a gate over the dielectric region. The gate is formed to include a metal gate region. Formation of the metal gate region includes: forming a layer of a first material configured to reduce an absolute value of a threshold voltage of the transistor, and configuring a part of the metal gate region so as also to form a diffusion barrier above the layer of the first material. Then, doped source and drain regions are formed using a dopant activation anneal.Type: ApplicationFiled: April 17, 2014Publication date: October 30, 2014Applicant: STMICROELECTRONICS (CROLLES 2) SASInventors: Sylvain Baudot, Pierre Caubet, Florian Domengie
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Patent number: 8871603Abstract: The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction.Type: GrantFiled: May 3, 2012Date of Patent: October 28, 2014Assignees: Texas Instruments Deutschland GmbH, Texas Instruments IncorporatedInventors: Christoph Andreas Othmar Dirnecker, Leif Christian Olsen
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Publication number: 20140273366Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region.Type: ApplicationFiled: April 11, 2013Publication date: September 18, 2014Inventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, Chi-Yuan Chen, Kuo-Yin Lin, Wan-Chun Pan, Ming-Liang Yen, Ching-Wei Tsai, Kuo-Cheng Ching, Huicheng Chang, Chih-Hao Wang
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Patent number: 8796729Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.Type: GrantFiled: November 20, 2012Date of Patent: August 5, 2014Assignee: Analog Devices, Inc.Inventors: David J Clarke, Javier Alejandro Salcedo, Brian B Moane, Juan Luo, Seamus Murnane, Kieran K Heffernan, John Twomey, Stephen Denis Heffernan, Gavin Patrick Cosgrave
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Patent number: 8796782Abstract: A polysilicon film that serves as a resistance element is formed. The polysilicon film is patterned to a predetermined shape. CVD oxide films covering the patterned polysilicon film are etched thereby removing the portion of the CVD oxide film where the contact region is formed, leaving the portion covering the portion of the polysilicon film that serves as the resistor main body. BF2 is implanted by using the portions of the remaining CVD oxide films covering the polysilicon film as an implantation mask thereby forming a high concentration region in the contact region.Type: GrantFiled: July 20, 2012Date of Patent: August 5, 2014Assignee: Renesas Electronics CorporationInventor: Takayuki Igarashi
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Publication number: 20140206160Abstract: A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.Type: ApplicationFiled: March 20, 2014Publication date: July 24, 2014Inventors: Anthony I. Chou, Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher
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Patent number: 8759875Abstract: A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The first and second gates form a gate-all-around transistor of the memory cell.Type: GrantFiled: December 7, 2012Date of Patent: June 24, 2014Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Ping Zheng, Eng Huat Toh, Yuan Sun
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Patent number: 8748246Abstract: A transistor includes a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. An independent work function adjustment process implants Group IIIa series dopants into a gate polysilicon layer of a PMOS transistor and implants lanthanide series dopants into a gate polysilicon layer of a NMOS transistor.Type: GrantFiled: December 10, 2010Date of Patent: June 10, 2014Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael Pas
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Patent number: 8710569Abstract: A semiconductor device includes a semiconductor substrate including a DRAM portion and a logic portion thereon, an interlayer film covering the DRAM portion and logic portion of the semiconductor substrate, and plural contact plugs formed in the interlayer film in the DRAM portion and the logic portion, the plural contact plugs being in contact with a metal suicide layer on a highly-doped region of source and drain regions of first, second and third transistors in the DRAM portion and the logic portion, an interface between the plural contact plugs and the metal silicide layer being formed at a main surface in the DRAM portion and the logic portion.Type: GrantFiled: January 5, 2012Date of Patent: April 29, 2014Assignee: Renesas Electronics CorporationInventors: Ken Inoue, Masayuki Hamada
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Patent number: 8697512Abstract: Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.Type: GrantFiled: December 14, 2010Date of Patent: April 15, 2014Inventors: Kleanthes G. Koniaris, Robert Paul Masleid, James B. Burr
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Publication number: 20140087531Abstract: A method of making a transistor includes etching a first side of a gate, the gate including an oxide layer formed over a substrate and a conductive material formed over the oxide layer, the etching removing a first portion of the conductive material, implanting an impurity region into the substrate such that the impurity region is self-aligned, and etching a second side of the gate to remove a second portion of the conductive material.Type: ApplicationFiled: December 2, 2013Publication date: March 27, 2014Applicant: Volterra Semiconductor CorporationInventor: Marco A. Zuniga
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Patent number: 8669156Abstract: Provided is a method of manufacturing a semiconductor circuit device including a MOS transistor and a capacitor element in which a gate electrode of a MOS transistor is formed of a first polysilicon film, a capacitor is formed of the first polysilicon film, a capacitor film, and a second polysilicon film, reduction in resistance of a normally-off transistor and reduction in resistance of a lower electrode of the capacitor are simultaneously performed, and reduction in resistance of an N-type MOS transistor and reduction in resistance of an upper electrode of the capacitor are simultaneously performed.Type: GrantFiled: March 11, 2011Date of Patent: March 11, 2014Assignee: Seiko Instruments Inc.Inventor: Kazuhiro Tsumura
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Publication number: 20140048876Abstract: A semiconductor device includes a high breakdown voltage DMOS transistor formed on a first conductivity type semiconductor substrate. The semiconductor device includes: a DMOS second conductivity type well; a DMOS first conductivity body region; a DMOS second conductivity type source region; a DMOS second conductivity type drain region; a LOCOS oxide film formed between the DMOS second conductivity type drain region and the DMOS first conductivity type body region; and a DMOS gate insulating film formed in succession to the LOCOS oxide film to cover a DMOS channel region between the DMOS second conductivity type source region and the DMOS second conductivity type well, wherein the DMOS gate insulating film includes a first insulating film which is disposed outside the DMOS channel region and a second insulating film which is disposed in the DMOS channel region and is thinner than the first insulating film.Type: ApplicationFiled: August 15, 2013Publication date: February 20, 2014Applicant: ROHM CO., LTD.Inventor: Yushi SEKIGUCHI
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Publication number: 20140035033Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region.Type: ApplicationFiled: May 2, 2013Publication date: February 6, 2014Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Min Gyu LIM, Jung Hwan LEE, Yi Sun CHUNG
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Patent number: 8642426Abstract: It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit.Type: GrantFiled: June 27, 2012Date of Patent: February 4, 2014Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 8637359Abstract: FinFET devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided having an active layer on an insulator. A plurality of fin hardmasks are patterned on the active layer. A dummy gate is placed over a central portion of the fin hardmasks. One or more doping agents are implanted into source and drain regions of the device. A dielectric filler layer is deposited around the dummy gate. The dummy gate is removed to form a trench in the dielectric filler layer. The fin hardmasks are used to etch a plurality of fins in the active layer within the trench. The doping agents are activated. A replacement gate is formed in the trench, wherein the step of activating the doping agents is performed before the step of forming the replacement gate.Type: GrantFiled: June 10, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Wilfried Ernst-August Haensch
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Patent number: 8609483Abstract: Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly contained within a core n-well using a baseline CMOS process flow.Type: GrantFiled: June 28, 2010Date of Patent: December 17, 2013Assignee: Texas Instruments IncorporatedInventors: Kamel Benaissa, Greg C. Baldwin
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Publication number: 20130328124Abstract: A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.Type: ApplicationFiled: June 6, 2012Publication date: December 12, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher
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Publication number: 20130313651Abstract: An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.Type: ApplicationFiled: May 22, 2012Publication date: November 28, 2013Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
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Patent number: 8592280Abstract: Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a field effect transistor device comprises the following steps. A substrate is provided having a silicon layer thereon. A fin lithography hardmask is patterned on the silicon layer. A dummy gate structure is placed over a central portion of the fin lithography hardmask. A filler layer is deposited around the dummy gate structure. The dummy gate structure is removed to reveal a trench in the filler layer, centered over the central portion of the fin lithography hardmask, that distinguishes a fin region of the device from source and drain regions of the device. The fin lithography hardmask in the fin region is used to etch a plurality of fins in the silicon layer. The trench is filled with a gate material to form a gate stack over the fins.Type: GrantFiled: August 20, 2009Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Wilfried Haensch, Katherine Lynn Saenger
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Patent number: 8574974Abstract: Forming a photoresist on a region other than a region on a trench gate electrode for a mask, a third gate insulating film on the trench gate electrode is etched and removed. After that, a non-doped polycrystalline silicon layer is formed on second and third gate insulating films and also on the trench gate electrode, and, N-type and P-type high concentration impurities are introduced by an ion implantation with the use of separate masks on the polycrystalline silicon layer of NMOS transistors and PMOS transistors with a low breakdown voltage and a high breakdown voltage. Then, a second gate electrode is formed by anisotropic etching. With the steps as described above, a first gate electrode inside the trench and the second gate electrode to be used in the lateral MOS transistor are laminated, to thereby reduce fluctuations due to the etching.Type: GrantFiled: December 20, 2012Date of Patent: November 5, 2013Assignee: Seiko Instruments Inc.Inventor: Yukimasa Minami
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Publication number: 20130288439Abstract: A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.Type: ApplicationFiled: June 21, 2013Publication date: October 31, 2013Inventors: Wei XIA, Xiangdong Chen
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Publication number: 20130234248Abstract: A manufacturing method of a semiconductor device including a DMOS transistor, an NMOS transistor and a PMOS transistor arranged on a semiconductor substrate, the DMOS transistor including a first impurity region and a second impurity region formed to be adjacent to each other, the first impurity region being of the same conductivity type as a drain region and a source region of the DMOS transistor, forming to enclose the drain region, and the second impurity region being of a conductivity type opposite to the first impurity region, forming to enclose the source region, the manufacturing method of the semiconductor device comprising forming the first impurity region and one of the NMOS transistor and the PMOS transistor, and forming the second impurity region and the other of the NMOS transistor and the PMOS transistor.Type: ApplicationFiled: February 25, 2013Publication date: September 12, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Nobuyuki Suzuki, Satoshi Suzuki, Masanobu Ohmura
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Patent number: 8530288Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.Type: GrantFiled: September 12, 2012Date of Patent: September 10, 2013Assignee: Micron Technology, Inc.Inventor: Kunal R. Parekh
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Patent number: 8502320Abstract: A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.Type: GrantFiled: September 30, 2011Date of Patent: August 6, 2013Assignee: Broadcom CorporationInventors: Wei Xia, Xiangdong Chen
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Patent number: 8492219Abstract: In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.Type: GrantFiled: June 4, 2012Date of Patent: July 23, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Toshinori Numata, Yukio Nakabayashi
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Patent number: 8487316Abstract: An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.Type: GrantFiled: October 28, 2010Date of Patent: July 16, 2013Assignee: IMECInventors: Kai Cheng, Stefan Degroote
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Patent number: 8482078Abstract: A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.Type: GrantFiled: May 10, 2011Date of Patent: July 9, 2013Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
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Patent number: 8476130Abstract: A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.Type: GrantFiled: July 12, 2011Date of Patent: July 2, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Tea-Kwang Yu, Byung-Sup Shim, Yong-Kyu Lee, Bo-Young Seo, Yong-Tae Kim
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Patent number: 8476129Abstract: A method and structure for fabricating sensor(s) or electronic device(s) using vertical mounting with interconnections. The method includes providing a resulting device including at least one sensor or electronic device, formed on a die member, having contact region(s) with one or more conductive materials formed thereon. The resulting device can then be singulated within a vicinity of the contact region(s) to form one or more singulated dies, each having a singulated surface region. The singulated die(s) can be coupled to a substrate member, having a first surface region, such that the singulated surface region(s) of the singulated die(s) are coupled to a portion of the first surface region. Interconnections can be formed between the die(s) and the substrate member with conductive adhesives, solder processes, or other conductive bonding processes.Type: GrantFiled: February 18, 2011Date of Patent: July 2, 2013Assignee: Mcube Inc.Inventors: Dave Paul Jensen, Hong Wan, Jon Ewanich
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Patent number: 8471334Abstract: According to one embodiment, a semiconductor device includes a channel formation region of first conductivity type, a first offset region of second conductivity type, a first insulating region, a first liner layer, a first semiconductor region of second conductivity type, a second semiconductor region of second conductivity type, a gate insulating film, and a gate electrode. The first liner layer is provided between the first offset region and the first insulating region. The first semiconductor region of second conductivity type is provided on the side opposite to the channel formation region sandwiching the first insulating region therebetween and having impurity concentration higher than that of the first offset region. The second semiconductor region of second conductivity type is provided on the side opposite to the first semiconductor region sandwiching the channel formation region therebetween and having impurity concentration higher than that of the first offset region.Type: GrantFiled: September 12, 2011Date of Patent: June 25, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Takao Ibi
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Patent number: 8456883Abstract: CMOS devices are provided in a substrate having a topmost metal layer comprising metal landing pads and metal connecting pads. A plurality of magnetic tunnel junction (MTJ) structures are provided over the CMOS devices and connected to the metal landing pads. The MTJ structures are covered with a dielectric layer that is polished until the MTJ structures are exposed. Openings are etched in the dielectric layer to the metal connecting pads. A seed layer is deposited over the dielectric layer and on inside walls and bottom of the openings. A copper layer is plated on the seed layer until the copper layer fills the openings. The copper layer is etched back and the seed layer is removed. Thereafter, an aluminum layer is deposited over the dielectric layer, contacting both the copper layer and the MTJ structures, and patterned to form a bit line.Type: GrantFiled: May 29, 2012Date of Patent: June 4, 2013Assignee: Headway Technologies, Inc.Inventor: Daniel Liu
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Patent number: 8450780Abstract: Disclosed is a solid-state image sensor including a photoelectric converter, a charge detector, and a transfer transistor. The photoelectric converter stores a signal charge that is subjected to photoelectric conversion. The charge detector detects the signal charge. The transfer transistor transfers the signal charge from the photoelectric converter to the charge detector. In the solid-state image sensor, the transfer transistor includes a gate insulating film, a gate electrode formed on the gate insulating film, a first spacer formed on a sidewall of the gate electrode on a side of the photoelectric converter, and a second spacer formed on another sidewall of the gate electrode on a side of the charge detector. The first spacer is longer than the second spacer.Type: GrantFiled: January 13, 2010Date of Patent: May 28, 2013Assignee: Sony CorporationInventor: Tetsuya Oishi
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Patent number: 8431827Abstract: Circuit modules including identification codes and a method of managing them are provided. A module substrate includes signal input output terminals and outer ground terminals provided at the peripheral portions of a surface which becomes a mounting surface when the circuit module is completed. An inner-ground-terminal formation area surrounded by the signal input output terminals and the outer ground terminals includes a plurality of inner ground terminals arranged in a matrix of rows and columns. One of the edge portions is a direction identification area. The inner ground terminal is not provided in the direction identification area, and a first identification code having information about the position of the module substrate is provided in the direction identification area.Type: GrantFiled: June 8, 2011Date of Patent: April 30, 2013Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiroshi Nishikawa, Taro Hirai
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Patent number: 8420472Abstract: Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.Type: GrantFiled: August 31, 2010Date of Patent: April 16, 2013Inventors: Kleanthes G. Koniaris, Robert Paul Masleid, James B. Burr
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Patent number: 8420474Abstract: A field effect transistor fabrication method includes defining a gate structure on a substrate, depositing a dielectric layer on the gate structure, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, annealing the first and second metal layers, and defining a carbon based device on the dielectric layer and the gate structure.Type: GrantFiled: January 11, 2012Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Martin M. Frank, Dechao Guo, Shu-Jen Hen, Kuen-Ting Shiu
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Publication number: 20130082330Abstract: A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.Type: ApplicationFiled: September 30, 2011Publication date: April 4, 2013Applicant: Broadcom CorporationInventors: Wei Xia, Xiangdong Chen
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Method for integrating SONOS non-volatile memory into a sub-90 nm standard CMOS foundry process flow
Patent number: 8409950Abstract: An embodiment of a method is disclosed to integrate silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a standard sub-90 nm complementary metal oxide semiconductor (CMOS) semiconductor foundry process flow. An embodiment of the method adds a few additional steps to a standard CMOS foundry process flow and makes minor changes to the rest of the baseline CMOS foundry process flow to form a new process module that includes both CMOS devices and an embedded SONOS NVM. An embodiment of the method utilizes new material sets (which are not utilized at larger nodes) that enhance NVM performance by improving charge tunneling behavior and reducing leakage currents. Furthermore, an embodiment of the method integrates CMOS with SONOS NVM at ever-shrinking dimensions while enhancing the NVM performance, without performing extra, costly processing steps.Type: GrantFiled: May 4, 2011Date of Patent: April 2, 2013Assignee: Northrop Grumman Systems CorporationInventors: Patrick Bruckner Shea, Dennis Adams, Michael Rennie, Joseph Terence Smith -
Patent number: 8404534Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. The plurality of gate structures are arranged in a plurality of lines, wherein an end-to-end spacing between the lines is smaller than a line-to-line spacing between the lines. The method further includes forming an etch stop layer over the gate structures, forming an interlayer dielectric over the gate structures, and forming a dielectric film over the gate structures before the interlayer dielectric is formed. The dielectric film merges in end-to-end gaps formed in the end-to-end spacing between the gate structures.Type: GrantFiled: February 11, 2011Date of Patent: March 26, 2013Inventor: Shiang-Bau Wang
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Patent number: 8383445Abstract: A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer with at least a first part and a second part on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first part of the gate oxide layer is associated with a first thickness, and the second part of the gate oxide layer is associated with a second thickness. The first thickness and the second thickness are different. The first gate region is located on the first part of the gate oxide layer associated with the first thickness, while the second gate region is located on both the first part of the gate oxide layer associated with the first thickness and the second part of the gate oxide layer associated with the second thickness. The first gate region is associated with the first well, and the second gate region is associated with the second well.Type: GrantFiled: December 27, 2010Date of Patent: February 26, 2013Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Roger Lee, Jianping Yang
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Patent number: 8383950Abstract: A first patterned etch stop layer and a first patterned conductor layer are laminated by a dielectric material to a second patterned etch stop layer and a second patterned conductor layer. As the etch stop metal of the first and second patterned etch stop layers is selectively etchable compared to a conductor metal of the first and second patterned conductor layers, the first and second patterned etch stop layers provide an etch stop for substrate formation etch processes. In this manner, etching of the first and second patterned conductor layers is avoided insuring that impedance is controlled to within tight tolerance.Type: GrantFiled: April 6, 2011Date of Patent: February 26, 2013Assignee: Amkor Technology, Inc.Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, Robert F. Darveaux
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Patent number: 8378426Abstract: A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element.Type: GrantFiled: February 11, 2008Date of Patent: February 19, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Makoto Yasuda
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Patent number: 8367494Abstract: A method is provided for fabricating an electrical fuse and a field effect transistor having a metal gate which includes removing material from first and second openings in a dielectric region overlying a substrate, wherein the first opening is aligned with an active semiconductor region of the substrate, and the second opening is aligned with an isolation region of the substrate, and the active semiconductor region including a source region and a drain region adjacent edges of the first opening. An electrical fuse can be formed which has a fuse element filling the second opening, the fuse element being a monolithic region of a single conductive material being a metal or a conductive compound of a metal. A metal gate can be formed which extends within the first opening to define a field effect transistor (“FET”) which includes the metal gate and the active semiconductor region.Type: GrantFiled: April 5, 2011Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Ying Li, Ramachandra Divakaruni
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Patent number: 8368130Abstract: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel area and a logic area, forming a light sensing element in the pixel area, and forming a first transistor in the pixel area and a second transistor in the logic area. The step of forming the first transistor in the pixel area and the second transistor in the logic area includes performing a first implant process in the pixel area and the logic area, performing a second implant process in the pixel area and the logic area, and performing a third implant process only in the logic area.Type: GrantFiled: December 14, 2010Date of Patent: February 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yao Ko, Chung-Wei Chang, Han-Chi Liu, Shou-Gwo Wuu