Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: A semiconductor device includes a first nitride semiconductor layer containing Ga, a second nitride semiconductor layer provided on the first nitride semiconductor layer containing Ga, a first electrode and a second electrode provided on or above the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a gate electrode provided between the first electrode and the second electrode, a conductive layer provided on or above the second electrode, of which a first distance to the second electrode is smaller than a second distance between the second electrode and the gate electrode, and which is electrically connected to the first electrode or the gate electrode, a first aluminum oxide layer provided between the gate electrode and the second electrode and provided between the second nitride semiconductor layer and the conductive layer, a silicon oxide layer, and a second aluminum oxide layer.

Abstract: An anisotropic conductive film, the anisotropic conductive film including an insulating layer and a conductive layer laminated on the insulating layer, the conductive layer containing conductive particles, wherein after glass substrates are positioned to face each other on the upper and lower surface of the anisotropic conductive film and are pressed against the anisotropic conductive film at 3 MPa (based on the sample area) and 160° C. (based on the detection temperature of the anisotropic conductive film) for 5 sec, a ratio of the area of the insulating layer to that of the conductive layer is from about 1.3:1 to about 3.0:1.

Abstract: Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.

Abstract: The performances of a semiconductor device are improved. A semiconductor device has a photodiode and a transfer transistor formed in a pixel region. Further, the semiconductor device has a second transistor formed in a peripheral circuit region. The transfer transistor includes a first gate electrode, and a film part formed of a thick hard mask film formed over the first gate electrode. The second transistor includes a second gate electrode, source/drain regions, silicide layers formed at the upper surface of the second gate electrode, and the upper surfaces of the source/drain regions.

Abstract: The present invention belongs to the field of display technology, and particularly relates to an array substrate, a display panel and a display device. The array substrate comprises a light-emitting unit, a driving unit for driving the light-emitting unit, and a driving signal unit for providing a driving signal to the driving unit, the driving unit being provided in a central area of the array substrate, the driving signal unit being provided on at least one side of a marginal area surrounding the central area, wherein the light-emitting unit covers the driving unit and extends into the at least one side of the marginal area on which the driving signal unit is provided. The array substrate can have not only enlarged display area but also decreased bezel width, and also have improved aperture ratio of a pixel.

Abstract: A semiconductor device includes a substrate. A planar insulating layer is disposed on an upper surface of the substrate. A channel region is disposed above the planar insulating layer. A gate electrode is disposed on the channel region. The semiconductor device includes a source region and a drain region. Each of the source region and the drain region is disposed on the substrate and is connected to the channel region. The planar insulating layer has a length equal to or greater than a length of the channel region, and the planar insulating layer includes first and second insulating layers having different permittivities.

Abstract: A wire, preferably a bonding wire for bonding in microelectronics, contains a copper core with a surface and coating layer containing aluminum superimposed over the surface of the copper core. The ratio of the thickness of the coating layer to the diameter of the copper core is from 0.05 to 0.2 ?m. The wire has a diameter in the range of from 100 ?m to 600 ?m and specified standard deviations of the diameter of the copper core and of the thickness of the coating layer. The invention further relates to a process for making a wire, to a wire obtained by the process, to an electric device containing at least two elements and the wire, to a propelled device containing the electric device, and to a process of connecting two elements through the wire by wedge bonding.

Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.

Abstract: A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.

Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.

Abstract: A package wafer processing method includes a processing step of processing a package wafer along planned dividing lines by a laser beam irradiation unit and forming processing grooves in the package wafer. The processing step includes detecting a processing groove and an exposed key pattern closest to the planned dividing line corresponding to the processing groove at a predetermined timing and measuring, as a deviation amount, the difference between the distance from the processing groove to the exposed key pattern and the distance that is registered in a registration step and is from the planned dividing line corresponding to the processing groove to the closest key pattern. An indexing feed mechanism is corrected according to the deviation amount.

Abstract: A semiconductor device includes a substrate, a laminated wiring layer unit, a nitride film disposed on the laminated wiring layer unit, a semiconductor element portion, a sealing portion surrounding the element portion. In the sealing portion, multiple wiring layers are connected with a sealing layer to configure a sealing structure which surrounds the element portion. The laminated wiring layer unit includes an uppermost layer which is made of material having higher adhesion to an uppermost wiring layer, and a protection insulating film made of material having higher adhesion to the sealing layer than the nitride film is disposed on the nitride film. In the sealing portion, a via-hole is defined in the protection insulating film, the nitride film, and the uppermost insulating film to partially expose the uppermost wiring layer. The sealing layer is embedded into the via-hole and is also disposed on a protection insulating film around the via-hole.

Abstract: The present disclosure generally relates to an improved large area substrate thin film transistor device, and method of fabrication thereof. More specifically, amorphous and LTPS transistors are formed by first forming an amorphous silicon layer, annealing the amorphous silicon layer to form polycrystalline silicon, depositing a masking layer over a first portion of the polycrystalline silicon layer, implanting a second portion of the polycrystalline silicon layer with an amorphizing species, and removing the masking layer.

Abstract: In a method, conductive lines used in a circuit are formed. Signal traces of a plurality of signal traces are grouped to a first group of first signal traces or a second group of second signal traces. A first mask is used to form a first conductive line for a first signal trace of the first group. A second mask is used to form a second conductive line for a second signal trace of the second group. The first traces each have a first width. The second traces each have a second width different from the first width. The grouping is based on at least one of following conditions: a current flowing through a signal trace of the signal traces of the plurality of signal traces, a length of the signal trace, a resistivity of the signal trace, or a resistivity-capacitive constant of the signal trace.

Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.

Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.

Abstract: An image pickup device includes on a silicon layer: a photodiode provided on each pixel basis to perform photoelectric conversion to generate a charge depending on the light receiving amount; a floating diffusion section configured to store the charge generated by the photodiode; and a transistor configured to output a pixel signal at a voltage in accordance with a level of the charge stored in the floating diffusion section, wherein the image pickup device further includes a hermetically-sealed cavity section inside the silicon layer and on at least one of the underside of the floating diffusion section and the underside of a channel body region of the transistor.

Abstract: An alignment method includes: a storage step that images a first workpiece on a chuck table and stores positions of alignment marks corresponding to scheduled division lines and positional relationships of the division lines with the alignment marks; a holding step that holds a second workpiece with the chuck table; a detection step that images positions of the alignment marks on the second workpiece, the positions corresponding to the stored alignment mark positions, and detects the alignment marks of the second workpiece; and an identification step that identifies positions of scheduled division lines of the second workpiece on the basis of the detected positions of the alignment marks of the second workpiece and the stored positional relationships. If one of the alignment marks of the second workpiece cannot be detected at one of the stored alignment mark positions, the detection step detects other adjacent alignment marks.

Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The method for manufacturing the array substrate comprises: forming a pattern of an active layer of a switching thin-film transistor (TFT) and a pattern of a corresponding pixel electrode on a base substrate, in which the active layer of the switching TFT and the pixel electrode are on the same layer.

Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.

Abstract: Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.

Abstract: An embodiment of an electronic device includes an IC die with a top surface and a bond pad exposed at the top surface. A stud bump (or stack of stud bumps) is connected to the bond pad, and the stud bump and die are encapsulated with encapsulant. A trench is formed from a top surface of the encapsulant to the stud bump, resulting in the formation of a trench-oriented surface of the stud bump, which is exposed at the bottom of the trench. An end of an interconnect is connected to the trench-oriented surface of the stud bump. The interconnect extends above the encapsulant top surface, and may be coupled to another IC die of the same electronic device, another IC die that is distinct from the device, or another conductive feature of the device or a larger electronic system in which the device is incorporated.

Abstract: The present invention improves the performance of an image sensor. In a planar view, fluorine is introduced into a part overlapping with a channel region in a gate electrode GE1 of an amplification transistor and is not introduced into the interior of a semiconductor substrate 1S. Concretely as shown in FIG. 20, a resist film FR1 is patterned in the manner of opening the part planarly overlapping with the channel region in the gate electrode GE1. Then fluorine is injected into the interior of the gate electrode GE1 exposed from an opening OP1 by an ion implantation method using the resist film FR1 in which the opening OP1 is formed as a mask.

Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.

Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate; a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer; an insulating layer formed on the second semiconductor layer; a source electrode and a drain electrode formed on the second semiconductor layer; and a gate electrode formed on the insulating layer. The insulating layer is formed of a material including an oxide and is formed by laminating a first insulating layer and a second insulating layer in a positioning order of the first insulating layer followed by the second insulating layer from a side of the second semiconductor layer, and an amount of hydroxyl groups included in per unit volume of the first insulating layer is less than an amount of hydroxyl groups included in per unit volume of the second insulating layer.

Abstract: A receiver circuit includes an input terminal through which an input signal is received. The receiver circuit also includes a first amplifier stage connected via its input to the input terminal of the receiver circuit; and an envelope detector stage that detects the incoming signal maxima to recover the signal envelope, where the detector stage is connected to the output of the first stage.

Abstract: A semiconductor device and a manufacturing method thereof is provided. The method comprises: providing a substrate for the semiconductor device with a gate structure and a first dielectric interlayer being formed thereon, said gate structure comprising a metal gate and an upper surface of said first dielectric interlayer being substantially flush with an upper surface of said gate; forming an interface layer to cover at least the upper surface of said gate such that the upper surface of said gate is protected from being oxidized; and forming a second dielectric interlayer on said interface layer.

Abstract: In a method of forming an epitaxial layer, an etching gas may be decomposed to form decomposed etching gases. A source gas may be decomposed to form decomposed source gases. The decomposed source gases may be applied to a substrate to form the epitaxial layer on the substrate. A portion of the epitaxial layer on a specific region of the substrate may be etched using the decomposed etching gases. Before the etching gas is introduced into the reaction chamber, the etching gas may be previously decomposed. The decomposed etching gases may then be introduced into the reaction chamber to etch the epitaxial layer on the substrate. As a result, the epitaxial layer on the substrate may have a uniform distribution.

Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.

Abstract: A method of fabricating a composite integrated optical device includes providing a substrate comprising a silicon layer, forming a waveguide in the silicon layer, and forming a layer comprising a metal material coupled to the silicon layer. The method also includes providing an optical detector, forming a metal-assisted bond between the metal material and a first portion of the optical detector, forming a direct semiconductor-semiconductor bond between the waveguide, and a second portion of the optical detector.

Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

Abstract: Improved electric field (steered-electron electric-field, or SEEF) sensors and methods of manufacturing the same are provided. The SEEF sensors described herein may have increased sensitivity to low-frequency electric fields while being smaller than previously known sensors, and may allow for low-power electric field detection. The invention described herein allows for sensitive, long-term electric field monitoring for applications ranging from personnel detection to underground facility monitoring, as well as extraordinarily small vector sensing (full Poynting vector) for compact direction-finding of emitters of interest. Exemplary electric field sensors may accurately sense, measure, characterize and/or transmit electric field data over a wide frequency range. Importantly, such sensing, measuring, and/or characterizing do not require any physical or resistive contact between the sensor and a source of an electric field.

Abstract: Provided is a semiconductor device for wireless communication which achieves a reduction in leakage power and allows an improvement in power efficiency. For example, to external terminals, an antenna driver section for driving an antenna and a rectifying section for rectifying input power from the antenna are coupled. The antenna driver section includes pull-up PMOS transistors and pull-down NMOS transistors. In the rectifying section, a power supply voltage generated by a full-wave rectifying circuit is boosted by a voltage boosting circuit. For example, when a supply of a power supply voltage from a battery is stopped, a power supply voltage resulting from the boosting by the voltage boosting circuit is supplied to the bulk of each of the pull-up PMOS transistors.

Abstract: In an illustrative embodiment, holes are formed in an insulating layer where the gates of NMOS and PMOS transistors are to be formed; and a hard mask spacer layer is formed on the exposed surfaces. Next, spacers are formed on the sidewalls of the holes by anisotropically etching the spacer layer to remove the portion of the spacer layer exposed at the bottom of each hole while leaving some of the spacer layer formed on the sidewalls of the holes. A high-k dielectric layer is then formed between the spacers; and a metal layer is formed on the high-k dielectric layer. Bulk metal layer is then formed on the metal layer. Chemical mechanical polishing is performed to remove the bulk gate metal down to the insulating layer, thereby isolating individual NMOS and PMOS gate structures.

Abstract: Photovoltaic (PV) cell structures having an integral light scattering interface layer configured to diffuse or scatter light prior to entering a semiconductor material and methods of making the same are described.

Abstract: A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes.

Abstract: A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration.

Abstract: A transistor using an oxide semiconductor, which has good on-state characteristics is provided. A high-performance semiconductor device including the transistor capable of high-speed response and high-speed operation is provided. In a manufacturing method of the transistor including the oxide semiconductor film including a channel formation region, an insulating film including a metal element is formed over the oxide semiconductor film, and low-resistance regions in which a dopant added through the insulating film by an implantation method is included are formed in the oxide semiconductor film. The channel formation region is positioned between the low-resistance regions in the channel length direction.

Abstract: A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.

Abstract: A method of fabricating an electronic device, such as an organic thin film transistor, is disclosed. A substrate, for example a silicate glass substrate, has a surface which supports at least one metallic electrode comprising at least one metal, for example gold, and at least a portion of the surface of the substrate is exposed. The method comprises selectively forming a self-assembled layer on the exposed portion of the substrate surface such that no self-assembled layer is formed on the at least one metallic electrode and applying a solution or other liquid which is repelled by the self-assembled layer to at least one metal electrode so as to selectively form a layer of further material, such as a charge injection promoting material, on the at least one metallic electrode.

Abstract: Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate.

Abstract: It is an object of the present invention to provide a power semiconductor device, which is capable of being operable regardless of thermal stress generation, reducing a heat generation from wire, securing the reliability of bonding portion when the device is used for dealing with a large amount current and/or under a high temperature atmosphere, a method of manufacturing the device and a bonding wire. In a power semiconductor device in which a metal electrode (die electrode 3) on a power semiconductor die 2 and another metal electrode (connection electrode 4) are connected by metal wire 5 using wedge bonding connection, the metal wire is Ag or Ag alloy wire of which diameter is greater than 50 ?m and not greater than 2 mm and the die 3 has thereon one or more metal and/or alloy layers, each of the layer(s) being 50 ? or more in thickness and a metal for the layer is selected from Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W and Al.

Abstract: A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.

Abstract: Methods and devices associated with phase change memory include diodes operating as selector switches having a large driving current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate, defining a diode array region and a peripheral region on the semiconductor substrate, forming an N+ buried layer in the diode array region by performing an ion implantation process and an annealing process. The method also includes forming a semiconductor epitaxial layer on the N+ buried layer, forming deep trench isolations through the epitaxial layer and the N+ buried layer into a portion of the substrate in the first direction, and forming shallow trench isolations in the diode array region and in the peripheral region in the second direction. The shallow trench isolation has a depth equal to or greater than a thickness of the epitaxial layer.

Abstract: A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

Abstract: A semiconductor device includes a first fin rising out of a semiconductor base. It further includes a second fin rising out of the semiconductor base. The second fin is substantially parallel to the first fin that forms a span between the first fin and the second fin. A first dielectric layer is deposited on exposed surfaces of a first gate body area of the first fin, a second gate body area of the second fin, and an adjacent surface of the semiconductor base that defines the span between the first and second gate body areas. A gate electrode layer is sandwiched between the first dielectric layer and a second dielectric layer. The semiconductor device includes a third fin interdigitated between the first fin and the second fin within the span. Exposed surfaces of the gate body area of the third fin are in contact with the second dielectric layer.

Abstract: A region for substrate potential is formed of an n-type well at a position in the direction of a channel length relative to the gate electrode and the position is between drain regions in the direction of a channel width. An n-type of a contact region with a higher concentration of n-type impurity than that of the region is provided in the region. The contact region is arranged away from the drain regions with a distance to obtain a desired breakdown voltage of PN-junction between the region and the drain region.