Abstract: A substrate 20 is placed in a process zone 115 of a process chamber 110, process gas is introduced into the process zone 115, and an energized gas is formed in the process zone 115. First process conditions are set to form etch-passivating deposits onto a surface 22 of the substrate 20. Second process conditions are set to etch the surface 22 of the substrate 20. The etch-passivating deposits formed before the etching process improve etching uniformity and reduce etch-rate microloading.

Abstract: The present invention provides a carbon based etch stop, such as a diamond like amorphous carbon, having a low dielectric constant and a method of forming a dual damascene structure. The low k etch stop is preferably deposited between two dielectric layers and patterned to define the underlying interlevel contacts/vias. The second or upper dielectric layer is formed over the etch stop and patterned to define the intralevel interconnects. The entire dual damascene structure is then etched in a single selective etch process which first etches the patterned interconnects, then etches the contact/vias past the patterned etch stop. The etch stop has a low dielectric constant relative to a conventional SiN etch stop, which minimizes the capacitive coupling between adjacent interconnect lines. The dual damascene structure is then filled with a suitable conductive material such as aluminum or copper and planarized using chemical mechanical polishing.

Abstract: A method for reducing RC delay by forming an air gap between conductive lines. A sacrificial layer is formed over a semiconductor structure, filling the gaps between conductive lines on the semiconductor structure. An air bridge layer is formed over the sacrificial layer. The semiconductor structure is exposed to an oxygen plasma, which penetrates through pores in the air bridge layer to react with the sacrificial layer, whereby the sacrificial layer is removed through the air bridge layer. The sacrificial layer and/or the air bridge layer comprise buckminsterfullerene. The air bridge layer can comprise buckminsterfullerene incorporated in an inorganic spin-on material. The buckminsterfullerene reacts with the oxygen plasma and is removed to form a porous air bridge layer. Then the oxygen species from the plasma penetrate the porous air bridge layer to react with and remove the sacrificial layer.

Abstract: A method of fabricating a gate stack having an endpoint detect layer and a multi-step etch process to prevent damage to a gate dielectric layer. The special endpoint detect layer emits an endpoint signal that allows the etch chemistry to be changed to a more selective polysilicon to oxide ratio to prevent damage to the gate oxide layer. The invention begins by forming a gate dielectric layer over a substrate. We then form an endpoint detect layer over the gate dielectric layer. A gate stack is formed over the bottom silicon layer. Then a mask is formed over the gate stack. The mask defines a gate electrode. We etch the gate stack and the endpoint detect layer using a multi-step etch comprising at least 3 steps. In a main etch step, the gate stack and the endpoint detect layer are etched using a first etch chemistry. Upon an endpoint detection signal generated by etching the gate stack, the first etch step is stopped.

Abstract: A method for determining the quality of features of a photoresist pattern, especially for vias and contacts, formed on a semiconductor wafer. A photoresist mask layer having a pattern of openings therein is deposited onto the wafer, and a test region (kerf) of the wafer is marked through the openings in the mask layer. In a preferred embodiment, the mask layer is a photoresist layer, although in alternative embodiments the mask layer could be provided as an insulator mask layer or a metal mask layer. The marking transfers an image of the bottom of the mask layer into the substrate by etching, such as by rastering a focused ion beam over the openings in the mask layer in the presence of an etchant gas. This provides an etched mark in the wafer defined by the passage of the focused ion beam through the mask opening. In alternative embodiments, the marking could be performed by staining or dyeing.

Abstract: A method for etching a doped polysilicon layer. A first doped polysilicon layer of a first conductive type and a second doped polysilicon layer of a second conductive type are formed. An etching process is performed to pattern the first doped polysilicon layer and the second doped polysilicon layer. The etching process includes a first main etching step and a second main etching step. The etching pressure of the first main etching step is lower than the etching pressure of the second main etching step.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first film over a semicondutor substrate, introducing a reaction gas including a dilution gas into a reaction atmosphere and then growing a antireflection film made of silicon nitride or silicon nitride oxide on the first film by a plasma chemical vapor deposition method in the reaction atmosphere, coating resist on the antireflection film directly or via a second film and then patterning the resist via exposure and development, patterning the first film located in an area not covered with the resist by etching, and removing the antireflection film by use of hydrofluoric acid after patterning of the first film, whereby expansion of impurity diffusion can be prevented and also retreat of sidewalls can be suppressed.

Abstract: The present invention is directed to a method of forming conductive interconnections in an integrated circuit device. In one embodiment, the method comprises forming a dielectric stack comprised of multiple layers, and determining a thickness ratio of the layers of the stack. The method further comprises determining an etching process to be performed on the dielectric stack to define an opening for a conductive interconnection based upon the determined thickness ration, and performing the determined etch process on the dielectric stack.

Abstract: A process of manufacturing a semiconductor device with a double-recessed gate field effect transistor, comprising the formation, on a substrate (1), of an active layer (3) of a semiconductor material and a first dielectric layer (D1), and further comprising the steps of: forming a second dielectric layer (R), forming an aperture (A0) in the second dielectric layer (R), then a first opening (A1) in the first dielectric layer (D1) having a same first width, while forming a second opening (A2) in the second dielectric layer having a second width larger than the first width, and then etching a preliminary recess (A4) in the subjacent semiconductor layer through said first opening (A1) having said first width, enlarging said first opening (A1) in the first dielectric layer (D1) to form a third opening (A3) having a third width larger than the second width, and then etching the semiconductor layer through said preliminary recess (A4) to form a deeper central recess (A6) having substantially said first width while

Abstract: One embodiment of the invention is a method for forming a raised structure on a semiconductor wafer. In the method, a patterned masking layer is formed over a wafer layer. The patterned masking layer typically includes a first mask covering a first region of the wafer layer and at least one side mask adjacent to the first mask, covering a side region of the wafer layer. After forming the patterned masking layer, exposed portions of the wafer layer adjacent the masks are removed using the patterned masking layer. This leaves a first raised structure (relative to an adjacent removed area) in the first substrate region and a sacrificial raised structure in the side region adjacent the first raised structure. After removing the exposed portions of the wafer layer, the sacrificial raised structure is selectively removed while leaving the first raised structure intact.

Abstract: A wet and vapor acid etching method releases a microelectromechanical systems (MEMS) structure from a substrate by dissolving a sacrificial layer disposed between the MEMS and the substrate. The sacrificial layer may be a silicon dioxide (SiO2) layer having a field portion over which the MEMS does not extend and a support portion over which the MEMS does extend. The field portion of the SiO2 layer is quickly removed using conventional wet hydrofluoric (HF) etching followed by rinsing and drying and then the support portion is removed using conventional vapor HF etching from a solution greater than 45% by weight percent. The wet HF chemical etch quickly removes the large field portion of the sacrificial layer. The HF vapor etch removes the small support portion of the sacrificial layer below the MEMS to release the MEMS from the substrate without stiction thereby preventing damage to the MEMS when released.

Abstract: A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. An oxide etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the oxide etch stop layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

Abstract: A first insulating film with a dielectric constant lower than that of a silicon oxide film is formed on a semiconductor substrate. Next, a metal film or a second insulating film, which has degrees of moisture absorption and deformation in an oxygen plasma process and exposure to a resist releasing solution equal to or less than those of a silicon oxide film, is formed on the first insulating film. Then, the metal film or the second insulating film is patterned to a prescribed pattern. An opening is formed in the first insulating film using the metal film or the second insulating film as a mask.

Abstract: A method or process for etching a trench in an IC structure is disclosed. The IC structure might be comprised of a plurality of different component materials arranged proximate to one another, all of which need to be etched down to a target level. A first etching chemistry is applied which preferentially etches a one type of component material. A second etching chemistry is applied which preferentially etches another type of component material. The method or process toggles back and forth between the etching chemistries until the target level is reached. The toggling techniques serves to maintain the profiles of the different component materials. One component material might also be embedded, as a collar or otherwise, around another component material. The toggling technique can serve to modulate the height, level, or shape of one material relative to another material. The toggling steps can be performed in situ or ex situ.

Abstract: A hard resist layer is formed on and/or within a deep-UV configured resist mask prior to patterning a semiconductor device feature. The hard resist layer reduces the amount of polymer residue generated during the patterning process, which can affect the resulting profile of the device feature. The hard resist mask is formed by subjecting the resist mask to a rapid thermal anneal (RTA) type of process. Because of the hard resist layer, the thickness of the resist mask can also be reduced, thereby increasing the resolution capabilities of the resist mask.

Abstract: An optical prove for detecting or irradiating evanescent light is manufactured by forming a film having a regulated film thickness on a substrate, then forming a recess from the rear surface of the substrate, and forming a through hole in the film from the side of the recess by etching. The obtained optical probe has a micro-aperture at the tip of the through hole and usually, a plurality of optical probes each having a micro-aperture of uniform profile are formed on a single substrate. In the recess, light-receiving or light-irradiating means may be provided.

Abstract: A semiconductor device is provided and formed using self-aligned low-resistance gates within a metal-oxide semiconductor (MOS) process. A sacrificial dielectric gate structure is formed on a semiconductor substrate instead of a conventional gate dielectric/gate conductor stack. After forming junction regions within a semiconductor substrate, the gate structure is removed to form a trench within a dielectric formed above the substrate. A low-resistance gate material can then be arranged within the trench, i.e., in the region removed of the gate conductor. The gate material can take various forms, including a single layer or multiple metal and/or dielectric layers interposed throughout the as-filled trench. The gate formation occurs after high temperature cycles often associated with activating the previously implanted junctions or growing gate dielectrics. Thus, low-temperature metals such as copper or copper alloys can be used.

Abstract: The present invention relates to semiconductor manufacturing field, more particularly, to a process of forming a charge storage electrode to which a selective hemispherical grains (HSG) silicon film is applied. The object of the present invention is to provide a method of forming a charge storage electrode having the selective HSG silicon film in semiconductor device which can secure a sufficient capacitor effective surface area by obtaining desired grain size at the time of selective HSG silicon film formation. The present invention prevents remaining of carbon component which obstructs the growth of HSG silicon film after dry etching process by limiting the carbon halide gas used in dry etching process of amorphous silicon film for defining the charge storage electrode at the time of process of forming the charge storage electrode having selective HSG silicon film.

Abstract: High density, multi-metal layer semiconductor devices are formed with accurate and uniform polysilicon gates and underlying gate oxides. Embodiments include etching the photoresist mask to reduce the horizontal layer.

Abstract: A method for fabricating a capacitor includes the formation of a self-aligned and essentially amorphous passivation edge web. The passivation edge web is formed in the course of a BST vapor phase deposition after prior etching of the lower metal electrode and of the barrier layer, the TEOS layer situated under the barrier layer being attacked by said etching. By means of targeted material redeposition on the side walls of the lower electrode and of the barrier layer, the passivation edge web is subsequently formed from this material deposition.

Abstract: After an organic bottom anti-reflective coating (12) is deposited on an underlying film (11), a resist pattern (15) is formed on the organic bottom anti-reflective coating (12). Dry etching is performed with respect to the organic bottom anti-reflective coating (12) masked with the resist pattern (15) to form an anti-reflective coating pattern. The dry-etching of the organic bottom anti-reflective coating (12) is performed by using etching gas containing gas having the S component such as SO2/O2-based etching gas or COS/O2-based etching gas.

Abstract: Plasma processing tools, dual-source plasma etchers, and etching methods are described. In one embodiment, a processing chamber is provided having an interior base and an interior sidewall joined with the base. A generally planar inductive source is mounted proximate the chamber. A dielectric liner is disposed within the chamber over the interior sidewall with the liner being received over less than an entirety of the interior sidewall. In a preferred embodiment, the interior sidewall has a groundable portion and the dielectric liner has a passageway positioned to expose the groundable interior sidewall portion. Subsequently, a plasma developed within the chamber is disposed along a grounding path which extends to the exposed interior sidewall. In another preferred embodiment, the dielectric liner is removably mounted within the processing chamber.

Abstract: A method for forming micromachined devices out of a polycrystalline silicon substrate using deep reactive ion etching to form the micromachined device. The method comprises the steps of providing a bulk material substrate of polycrystalline silicon, and etching the bulk material using deep reactive ion etching to form the micromachined device. The present invention also includes a method for forming a micromachined device comprising the steps of providing a first layer of single crystal silicon and etching a first set of elements on the first layer. The method further includes the steps of providing a second layer of single crystal silicon, etching a second set of elements on the second layer, and joining the first and second layers together such that the crystal planes of the first layer and the second layer are misaligned and such that the first set and the second set of elements are properly aligned.

Abstract: In a plasma processing chamber, a method for etching through a selected portion of an oxide layer of a wafer's layer stack to create a self-aligned contact opening is described. The wafer stack includes a substrate, a polysilicon layer disposed above the substrate, a nitride layer disposed above said polysilicon layer and the oxide layer disposed above the nitride layer. The method for etching includes etching through the oxide layer of the layer stack with a chemistry and a set of process parameters. The chemistry essentially includes C.sub.2 HF.sub.5 and CH.sub.2 F.sub.2 and the set of process parameters facilitate etching through the oxide layer without creating a spiked etch and etching the oxide layer through to the substrate without substantially damaging the nitride layer.

Abstract: In a method of manufacturing a semiconductor device, a plurality of inter layer conductive path is formed through a first resist pattern which in turn is formed by an exposure of a hole pattern mask. A plurality of conductive lines is formed, adjacent to the layer of the conductive paths, through a second resist pattern which in turn is formed by double exposure of a line pattern mask and the hole pattern mask. Each conductive line is positioned on at least one of the conductive paths. Or alternatively, each conductive path is positioned between the lines.

Abstract: A method for a salicide process where S/D silicide contacts are formed in a separate silicide step than the gate silicide contacts. Preferably, TiSi.sub.2 is formed on S/D regions and TiSi.sub.2 or CoSi.sub.2 is formed on Poly electrodes (lines or gates) by etching back a sidewall spacer on the poly electrodes. The invention has two silicide steps. The TiSi.sub.2 is formed over the S/D regions while the gate electrode is protected by a silicon nitride Cap layer. Next, an ILD layer formed over the S/D regions. The interlevel dielectric (ILD) layer, cap layer and spacers on the sidewalls of the gate electrodes are etched back. The invention has two embodiments for the composition of the spacers. In a second silicide step, Titanium silicide (TiSi.sub.x or TiSi.sub.2) or Cobalt silicide (CoSi.sub.x or CoSi.sub.2) is formed on the top and sidewalls of the electrodes. A key feature of the invention is that the gate contact silicide is formed on the top and sidewalls of the electrodes.

Abstract: The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-SI on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently.

Abstract: A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing plasma environment (20). This carbon-containing plasma environment (20) forms a carbon-containing layer (24) within the region (11). After forming this region (24), a wet etch chemistry (22) is used to remove remaining portions of the sacrificial oxide (14) without forming a layer (24) in the region (13). Furnace oxidation is then used to form regions (26a) and (26b) wherein the growth of region (26a) has been retarded by the presence of the region (24). Therefore, the regions (26a) and (26b) are differing in thickness and can be used to make different transistors having different current gains.

Abstract: A first insulating film with a dielectric constant lower than that of a silicon oxide film is formed on a semiconductor substrate. Next, a second insulating film, which has degrees of moisture absorption and deformation in an oxygen plasma process and exposure to a resist releasing solution equal to or less than those of a silicon oxide film, is formed on the first insulating film. Then, a third insulating film, which has degrees of moisture absorption and deformation in an oxygen plasma process and exposure to a resist releasing solution equal to or less than those of a silicon oxide film are formed on the second insulating film. Thereafter, the third insulating film is patterned to a prescribed pattern. An opening is formed in the first and second insulating films using the third insulating film as a mask.

Abstract: A plasma, formed from a mixture of C.sub.4 F.sub.8 and CH.sub.2 F.sub.2, is used to etch a self-aligned contact, the self-aligned contact being an opening in the oxide layer, the opening being aligned with an opening in an underlying nitride layer and extending to a substrate underlying the nitride. The mixture of C.sub.4 F.sub.8 and CH.sub.2 F.sub.2 provides a high ratio of oxide etch rate to nitride etch rate so that the etching is completed without substantially damaging the nitride layer. For thicker oxide layers a preliminary etch step using C.sub.2 F.sub.6 and C.sub.2 HF.sub.5 may be performed prior to using the mixture of C.sub.4 F.sub.8 and CH.sub.2 F.sub.2.

Abstract: In a method for selectively etching a second silicon layer of a multilayer structure which includes a first silicon layer and the second silicon layer formed on the first silicon layer and doped with impurities according to the present invention, the second silicon layer is selectively etched by using an etching gas including freon-14 gas and a gas selected from a group composed of hydrogen chloride gas and chloride gas.

Abstract: A method of fabricating a via and an interconnection. On a substrate comprising a semiconductor device and a first metal layer, a first inter-metal dielectric layer is formed on the first metal layer. A photo-resist layer is formed on the first inter-metal dielectric layer. A single step of photolithography is performed to define a via hole region, an interconnection window region, and an isolation region simultaneously. The first inter-metal dielectric layer is etched using the photo-resist layer as a mask, to form a via hole and an interconnection window simultaneously. The photo-resist layer is removed and the via hole and the interconnection window are filled with a second metal layer. The second metal layer is etched until the inter-metal dielectric layer under the isolation region is exposed. A second inter-metal dielectric layer is formed.

Abstract: A method of fabricating a compound semiconductor device includes a step of removing a semiconductor layer by an etching process to expose an upper major surface of an underlying semiconductor layer, followed by a growth of another semiconductor layer of the p-type on the surface thus exposed, wherein the exposed surface is cleaned by a flushing of a gaseous metal organic compound containing a group V element for removing impurities therefrom and further doping the exposed surface to the p-type.

Abstract: Methods for monitoring defects in a process for forming a contact hole, via or trench in a layer of a device in an integrated circuit includes the steps of forming a sacrificial topology on a substrate by duplicating at least a portion of a structure of the device while substituting a material substantially free of elemental silicon for any elemental silicon present in the device to be monitored, etching the sacrificial topology at least to the substrate, removing at least a portion of the sacrificial topology, and inspecting the substrate using a wafer surface inspection tool. The substituted material, such as a dielectric material, can be easily etched and removed from the substrate, as compared to polysilicon. The etching step preferably creates an indentation in the substrate that is readily detectable by the wafer surface inspection tool. The etching step is preferably a selective etching step, having a selectivity of at least 10:1.

Abstract: Plasma processing tools, dual-source plasma etchers, and etching methods are described. In one embodiment, a processing chamber is provided having an interior base and an interior sidewall joined with the base. A generally planar inductive source is mounted proximate the chamber. A dielectric liner is disposed within the chamber over the interior sidewall with the liner being received over less than an entirety of the interior sidewall. In a preferred embodiment, the interior sidewall has a groundable portion and the dielectric liner has a passageway positioned to expose the groundable interior sidewall portion. Subsequently, a plasma developed within the chamber is disposed along a grounding path which extends to the exposed interior sidewall. In another preferred embodiment, the dielectric liner is removably mounted within the processing chamber.

Abstract: A multi-step dry-etching method that sequentially employs plasma etching and reactive ion etching process steps to form the pairs of adjacent, doped polysilicon gate electrodes of a twin-well CMOS device. The initial dry-etching process step uses to best advantage the speed of plasma etching to rapidly form pairs of adjacent p- and n-type gate-precursor features with substantially vertical sidewalls from the upper 50-80% of a doped polysilicon layer which lies on an insulating film. The gate-precursor features and, subsequently, the gate electrodes are formed from pairs of adjacent p- and n-type regions within the doped polysilicon layer which lie over pairs of adjacent n- and p-wells (the twin wells of the CMOS device), respectively, within a substrate. The subsequent dry-etching process step uses reactive ion etching to complete the formation of the pairs of adjacent, doped polysilicon gate electrodes from the remaining 50-20% of the etched, doped polysilicon layer without over-etching the insulating film.

Abstract: The present invention provides a method of forming a dual damascene structure on a semiconductor wafer. The semiconductor wafer comprises a substrate, and a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer and a photoresist layer sequentially formed on the substrate. A dry-etching process is performed first to vertically remove a specific portion of the second silicon oxide layer down to the silicon nitride layer so as to form a hole. Then the photoresist layer is removed and the portion of the silicon nitride layer positioned under the hole is removed using a phosphoric acid solution. A lithographic process is then performed to form a photoresist layer on the second silicon oxide layer, the photoresist layer comprising a line-shaped opening positioned above the hole with a width larger than the diameter of the hole. Then an etching process is performed along the line-shaped opening to vertically remove the second silicon oxide layer and the first silicon oxide layer.

Abstract: A chemical vapor deposition (CVD) method for forming a doped silicate glass dielectric layer within a microelectronics fabrication. There is first positioned within a reactor chamber a substrate employed within a microelectronics fabrication. There is then stabilized within the reactor chamber with respect to the substrate a first flow of a silicon source material absent a flow of a dopant source material. There is then deposited upon the substrate within the reactor chamber a doped silicate glass dielectric layer through a chemical vapor deposition (CVD) method. The doped silicate glass dielectric layer is formed employing a second flow of the silicon source material, a flow of an oxidant source material and the flow of the dopant source material. There may subsequently be formed through the doped silicate glass dielectric layer an anisotropically patterned via through an anisotropic patterning method.

Abstract: A masking process for forming first and second ion-doped regions on a substrate of a semiconductor device. An oxide layer and a first nitride layer are formed on the substrate in order. The first nitride layer is etched using a photolithography process to form a first predetermined pattern which exposes portions of the oxide layer. The exposed portions of the oxide layer are then etched using the first predetermined pattern as an etching mask, until portions of the substrate corresponding to the first ion-doped regions are exposed. Next, first ions are doped into the exposed portions of the substrate using the first predetermined pattern as a doping mask. The first predetermined pattern is removed. A second nitride layer is then formed over the substrate and the patterned oxide layer. Portions of the second nitride layer are removed to reveal the top of the patterned oxide layer, forming a second predetermined pattern on the substrate.

Abstract: An interconnect layer is fabricated using a tungsten hard mask by forming a tungsten based layer over an aluminum based layer. A photoresist layer is deposited over the tungsten based layer and patterned. The tungsten based layer is patterned by applying a fluorine-based etchant using the photoresist layer as an etch mask. Then the aluminum based layer is patterned by applying a chlorine based etchant using the tungsten based layer as an etch mask.

Abstract: In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40.degree. C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40.degree. C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40.degree. C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.

Abstract: A method for selective controlled etching of a material particularly by sequentially switching between two (2) or more modes of radiofrequency waves and/or by distance from a source of the microwaves. The modes and/or distance are selected depending upon the surface of the material to be etched. The etching is rapidly conducted at 0.5 mtorr to 10 torr, preferably using microwave plasma etching.

Abstract: A method for stripping photoresist used as an etch mask in carbon based reactive ion etching includes flood exposing a patterned photoresist with a light and cyclically exposing the photoresist with an oxygen plasma in between the carbon based plasma. The step of cyclically exposing occurs after the step of flood exposing. The step of flood exposing includes the step of decomposing photosensitive compounds in the photoresist, while the step of cyclically exposing includes the step of cyclically removing layers of the photoresist.

Abstract: The present invention relates to methods for fabricating Fully Overlapped Nitride-Etch Defined (Fond) devices. These methods permit the lateral dimension and depth of the lowly-doped source and drain extensions to be independently controlled and well defined.

Abstract: A method to fabricate bottle-shaped deep trench in a semiconductor substrate which mainly involves two substitute plasma etching steps from the conventional approach. After a neck profile is formed, instead of raising the plasma gas pressure while keeping the etching composition constant, as in the conventional approach, the plasma gas pressure is first maintained the same, then decreased substantially. On the other hand, the concentrations of HBr and NF.sub.3 are increased substantially in both new steps. The first substitute plasma etching step is conducted at a pressure of 100 mtorr an RF power of about 1,000 W, a magnetic field of 65 Gauss. The plasma gas composition consists of HBr, NF.sub.3, and (He/O.sub.2) a at a ratio of about 200:20:20. The second substitute plasma etching step is conducted at plasma gas pressure of 30 mtorr, an RF power of 600 W, a magnetic field of 65 Gauss. The plasma gas composition consists of HBr, NF.sub.3, and (He/O.sub.2) a at a ratio of about 150:13:20.

Abstract: A method and apparatus for protecting a neighboring area that is adjacent to a first area that is to be etched. The method includes creating a guard cell substantially surrounding the first area, but excluding the neighboring area. The guard cell is formed of a material that is substantially selective to the etch process subsequently employed to etch within the first area. After the guard cell is formed, an etch is performed within the first area, while the guard cell prevents etching of the neighboring are outside the guard cell.

Abstract: A method for forming a patterned metal layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket metal layer. There is then formed over the blanket metal layer a patterned photoresist layer. There is then etched through use of a plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the blanket metal layer to form a patterned metal layer. The patterned metal layer so formed has a metal impregnated carbonaceous polymer residue layer formed upon a sidewall of the patterned metal layer. There is then stripped from the patterned metal layer the patterned photoresist layer through use of an oxygen containing plasma while simultaneously oxidizing the metal impregnated carbonaceous polymer residue layer to form an oxidized metal impregnated polymer residue layer upon the sidewall of the patterned metal layer.

Abstract: Generally, the present invention relates to a semiconductor device having a dual gate electrode material and a process of fabricating such a device. Consistent with one embodiment of the invention, a semiconductor device is formed by forming a first gate electrode over the substrate and forming a second gate electrode from a different material than the first gate electrode over the substrate. For example, the first gate electrode may be formed from polysilicon and a second gate electrode may be formed from a metal such as aluminum, titanium, cobalt, or copper.

Abstract: A process for etching single crystal silicon, polysilicon, silicide and polycide using iodinate or brominate gas chemistry, is disclosed. The iodinate/brominate gas chemistry etches narrow deep trenches with very high aspect ratios and good profile control and without black silicon formation or other undesirable phenomena.

Abstract: A process of opening, a stack of large diameter via holes, in a multiple levels of insulator layers, to be used for access of a laser repair procedure, applied to underlying integrated circuit shapes, while simultaneously opening small diameter via holes, in the same multiple levels of insulator layers, to be used to accommodate metal plug structures, has been developed. The process features the use of a polysilicon stop layer, used at the bottom of the stack of large diameter via holes, protecting underlying components of the underlying integrated circuit, from the dry and wet etching procedures used for the creation of the stack of large diameter via holes. The process also features the formation of metal spacers, on the sides of the large diameter via holes, created simultaneously during the formation of metal plug structures, and used again to protect the multiple levels of insulator layer, that would have been exposed, if left unprotected, during a wet etching procedure.