Abstract: Processing test results from a plurality of individual semiconductor testers by analyzing each test result at an adaptive test engine. A centralized system jointly analyzes all the test results from the plurality of individual semiconductor testers. The adaptive test engine or the centralized system identifies, based on the analysis of each test result or the joint analysis of all the test results, one or more of: a test environmental issue, a tester variability issue, a tester calibration issue, a product variability issue, and a manufacturing process variability issue. The adaptive test engine or the centralized system determines whether one or more of the plurality of individual semiconductor testers causes one or more of the identified issues or whether semiconductor products tested by the plurality of individual semiconductor testers causes one or more of the identified issues.
Type:
Grant
Filed:
August 30, 2010
Date of Patent:
October 7, 2014
Assignee:
International Business Machines Corporation
Inventors:
Mark C. Johnson, Deepak S. Turaga, Olivier Verscheure
Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.
Type:
Grant
Filed:
September 24, 2012
Date of Patent:
September 23, 2014
Assignee:
Intel Corporation
Inventors:
Christopher J. Nelson, Tak M. Mak, David J. Zimmerman, Pete D. Vogt
Abstract: In a method and to a device for identifying an erroneous algorithm (A), data output by a1) of the algorithm (A) to be tested and/or a2) a reference algorithm (B) are categorized, and the reference frequency (R(A), R(B)) at which data of at least one category (Kx) occur during operation for the case a1) of the algorithm (A) to be tested or for case a2) of the reference algorithm (B) is determined in a reference phase. The test frequency (T(A)) at which data of at least one category (Kx) occur during operation of the algorithm (A) to be tested is determined in a test phase. Finally, an error message is output if the deviation of the test frequency (T(A)) of at least one category (Kx) from the reference frequency (R(A), R(B)) of the same category (Kx) exceeds a specific threshold value (THR).
Abstract: Ultrasonic inspection equipment facilitates alignment of display positions of three-dimensional ultrasonic inspection data and three-dimensional shape data, and quickly discriminates between a defect echo and an inner-wall echo. A computer 102A has a position correction function of correcting a relative display position between three-dimensional shape data and three-dimensional ultrasonic inspection data. A display position of the three-dimensional ultrasonic inspection data or that of the three-dimensional shape data is moved by a norm of a mean vector along the mean vector that is calculated from a plurality of vectors defined by a plurality of points selected in the three-dimensional ultrasonic inspection data and by a plurality of points selected in the three-dimensional shape data. The three-dimensional shape data and the three-dimensional ultrasonic inspection data are displayed in such a manner as to be superimposed on each other on a three-dimensional display unit 103C.
Type:
Grant
Filed:
October 9, 2013
Date of Patent:
September 16, 2014
Assignee:
Mitsubishi Hitachi Power Systems, Ltd.
Inventors:
So Kitazawa, Naoyuki Kono, Atsushi Baba
Abstract: Under the present invention an audit log for the server environment is obtained and parsed to remove any extraneous information. The parsing operation will typically leave only the previous operations processed by the server environment in the audit log. Thereafter, the parsed audit log is fed back to the server environment. Specifically, each operation in the audit log is fed back to the server environment as a request. Each request will typically have its own thread to simulate concurrent thread activity in the server environment. After the requests have been fed, statistics corresponding to the resulting performance of the server environment will be generated.
Type:
Grant
Filed:
June 30, 2004
Date of Patent:
September 16, 2014
Assignee:
International Business Machines Corporation
Inventors:
Gordan G. Greenlee, Kan Y. Hsiao, Howard E. Poole, Joseph F. Riina, Joe W. Simons, Richard E. Weingarten
Abstract: A method and apparatus are provided for implementing automated memory address recording in constrained random test generation for verification of processor hardware designs. A test generation program includes a built in feature to keep track of storage addresses used and to make the addresses available to the test definition. This built in feature of a constrained random test generator allows storage addresses used in the past to be accessed by the current instruction generation eliminating the requirement of deliberately establishing target addresses first. This allows separate test events to interact with the same storage addresses without having to write a special test.
Type:
Application
Filed:
March 7, 2013
Publication date:
September 11, 2014
Applicant:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Craig T. Atherton, Avishai Fedida, Olaf K. Hendrickson, Oz Hershkovitz
Abstract: The invention relates to a system for controlling at least one actuator (6) for thrust reverser cowlings (2) on a turbojet engine, comprising a set of actuator and/or control components with at least one actuator (6) for cowlings (2) driven by at least one electric motor (7) and control means (9) for the electric motor (7). The control means (9) comprise test means (20), with an interface (22) destined for receiving test requests from a user. The test means (20) are designed on reception of a test request to carry out a test cycle on one or more components (7, 6, 15, 18) of the system comprising an isolated actuation to the component(s) (7, 6, 15, 18) with regard to the other components of the system.
Abstract: Methods, systems and apparatus are provided for ranking tests of interest. A set of failure modes of interest and a set of tests of interest are determined. A differentiation factor is then computed for each of the tests of interest, and each of the tests of interest can then be ranked based on their respective differentiation factors.
Type:
Grant
Filed:
June 15, 2011
Date of Patent:
September 9, 2014
Assignee:
Honeywell International Inc.
Inventors:
Kelly Jean Lechtenberg, Qingqiu Ginger Shao
Abstract: A display method and apparatus provides an easy to interpret presentation of multiple channel data, in the form of columns where the height of the column represents the relative measurement. A threshold line provides an indication of whether the measurement is above or below the threshold. Greater detail and numeric measurement values can be displayed for individual channels while the multiple channel display is in view.
Abstract: The present disclosure provides methods for determining the film forming potential of food products. In a general embodiment, a method for determining the film forming potential of a food product is provided and includes providing a temperature-control device having a processor and a computer readable medium storing instructions which, when executed, cause the processor to cycle an interior temperature of the temperature-control device between different temperatures in a predetermined amount of time. The methods further include placing a packaged food product in the temperature-control device, and causing the processor to execute the stored instructions.
Type:
Application
Filed:
December 31, 2013
Publication date:
August 28, 2014
Applicant:
Nestec S.A.
Inventors:
Leigh Anne HIGGINS, Vivek GNANASEKHARAN
Abstract: Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment apparatus comprises a computer system comprising a tester processor, wherein the tester processor is communicatively coupled to a plurality of FPGA components. Each of the plurality of FPGA components is coupled to a memory module and comprises: an upstream port operable to receive commands and data from the tester processor; a downstream port operable to communicate with a respective DUT from a plurality of DUTs; and a plurality of hardware accelerator circuits, wherein each of the accelerator circuits is configured to communicate with one of the plurality of DUTs.
Abstract: Example embodiments disclose a drive system including a machine including a plurality of phases and configured to generate power based on a plurality of phase currents, each respectively associated with the plurality of phases and a direct current (DC) bus, operatively connected to the machine. The DC bus includes a high-side line, a low-side line, and an inverter including a plurality of switching systems, operatively connected between the high-side line and the low-side line, the plurality of switching systems, each configured to output a respective one of the plurality of phase currents. The drive system also includes a controller, operatively connected to the DC bus and the machine, the controller configured to determine if a failure exists in the drive system based on the plurality of phase currents and a DC bus voltage, the DC bus voltage being a voltage across the high-side line and the low-side line.
Type:
Grant
Filed:
March 21, 2011
Date of Patent:
August 19, 2014
Assignee:
Deere & Company
Inventors:
Brij N. Singh, Chris J. Tremel, Alan K. Gilman
Abstract: A calibration device, capable of calibrating a gain of a radiometer, includes an actuator and a micro-electromechanical-system (MEMS) unit. The actuator receives a calibration signal outputted from a control unit. The MEMS unit is coupled to the actuator, in which the actuator enables the MEMS unit to shield an antenna of the radiometer according to the calibration signal, such that the radiometer generates an environmental signal according to an equivalent radiant temperature received from the MEMS unit, and the control unit calibrates the gain of the radiometer according to the environmental signal.
Type:
Grant
Filed:
June 19, 2012
Date of Patent:
August 19, 2014
Assignee:
Industrial Technology Research Institute
Abstract: A monitoring system includes a testing apparatus and a display control apparatus connected to the testing apparatus. The testing apparatus includes a plurality of testing locations and a collection module connected to the plurality of testing locations. Each of the plurality of testing locations receives a tested product, which is tested by the testing apparatus. The collection module collects testing states of the tested products. A display apparatus is connected to the display control apparatus. The display control apparatus controls the display apparatus to show a plurality of indicating blocks corresponding to the plurality of testing locations. The display apparatus is adapted to display the plurality of indicating blocks to match the plurality of testing locations. The display control apparatus controls each of the plurality of indicating blocks to show the testing state of the tested product in each the plurality of testing locations.
Type:
Grant
Filed:
May 23, 2012
Date of Patent:
July 29, 2014
Assignees:
Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
Abstract: A wireless electronic device may serve as a device under test in a test system. The test system may include an array of over-the-air antennas that can be used in performing over-the-air wireless tests on the device under test (DUT). A channel model may be used in modeling a multiple-input-multiple-output (MIMO) channel between a multi-antenna wireless base station and a multi-antenna DUT. The test system may be configured to perform over-the-air tests that emulate the channel model. A design and analysis tool may be used to identify an optimum over-the-air test system setup. The tool may be used in converting a geometric model to a stochastic model for performing conducted tests. The tool may be used in converting a stochastic model to a geometric model and then further convert the geometric model to an over-the-air emulated stochastic model. The over-the-air emulated stochastic model may be used in performing conducted tests.
Type:
Grant
Filed:
April 27, 2011
Date of Patent:
July 29, 2014
Assignee:
Apple Inc.
Inventors:
Matt A. Mow, Bo Niu, Robert W. Schlub, Ruben Caballero
Abstract: The present disclosure includes a method for quantifying contribution to overall variability of moisture content in wood products and associated computer software. The method comprises the steps of obtaining moisture content data for the wood products and identifying one or more sources of variability in the moisture content data. A contribution to overall variability from each of the one or more sources of variability is then quantified. One or more opportunities to impact the overall variability are then quantified, each of the one or more opportunities being associated with one or more executable steps.
Type:
Grant
Filed:
October 27, 2010
Date of Patent:
July 29, 2014
Assignee:
Weyerhaeser NR Company
Inventors:
Mark A. Stanish, John E. Jones, III, John N. Giovanini
Abstract: Example embodiments disclosed herein relate to identifying a target fan connected to a computing device. In example embodiments, the target fan may be identified based on a fan speed profile of the target fan.
Type:
Grant
Filed:
August 31, 2011
Date of Patent:
July 22, 2014
Assignee:
Hewlett-Packard Development Company, L.P.
Abstract: Various embodiments for determining dynamic care areas are provided. In one embodiment, a first inspection process is performed on a wafer after a first fabrication step has been performed on the wafer and before a second fabrication process has been performed on the wafer. One embodiment includes determining care areas for a second inspection process based on inspection results generated by the first inspection process. The second inspection process will be performed on the wafer after the second fabrication step has been performed on the wafer.
Type:
Grant
Filed:
June 30, 2011
Date of Patent:
July 15, 2014
Assignee:
KLA-Tencor Corp.
Inventors:
Ashok V. Kulkarni, Chien-Huei Adam Chen
Abstract: A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of each ground pin and ground vias along each signal path routing of each ground pin. If there are any ground vias having the same absolute coordinates, the computer determines that the ground vias are shared by more than one ground pin.
Abstract: A method for determining a parameter such as the resistance of at least one accumulator of a battery. The method includes the following steps: measuring a first voltage (U1) when the current is substantially equal to a predetermined value; conducting the plurality of voltage and current measurements (Un; In) during a current pulse; calculating a plurality of resistance values (Rn) from the first voltage and from the plurality of voltage and current measurements; determining a resistance value as the average of the calculated resistance values and an associated standard deviation; determining an absolute uncertainty on the value of the resistance as the product of the standard deviation and of a Student coefficient; if the relative uncertainty is less than or equal to a predetermined accuracy threshold, validating the resistance value (R).
Abstract: A system may include a non-destructive testing (NDT) device. The NDT device may further include a communications system configured to receive control data from an external system, wherein the NDT device is configured to use the control data to control a component included in the NDT device, to control a parameter of the NDT device, or a combination thereof.
Type:
Application
Filed:
December 31, 2012
Publication date:
July 3, 2014
Applicant:
GENERAL ELECTRIC COMPANY
Inventors:
Jason Howard Messinger, Robert Carroll Ward, Francois Xavier De Fromont, Michael Christopher Domke
Abstract: The present invention systems and methods facilitate configuration of functional components included in a remotely located integrated circuit die. In one exemplary implementation, a die functional component reconfiguration request process is engaged in wherein a system requests a reconfiguration code from a remote centralized resource. A reconfiguration code production process is executed in which a request for a reconfiguration code and a permission indicator are received, validity of permission indicator is analyzed, and a reconfiguration code is provided if the permission indicator is valid. A die functional component configuration process is performed on the die when an appropriate reconfiguration code is received by the die. The functional component configuration process includes directing alteration of a functional component configuration. Workflow is diverted from disabled functional components to enabled functional components.
Type:
Grant
Filed:
December 18, 2003
Date of Patent:
July 1, 2014
Assignee:
Nvidia Corporation
Inventors:
Michael B. Diamond, John S. Montrym, James M. Van Dyke, Michael B. Nagy, Sean J. Treichler
Abstract: A test fixture includes a first RS-232 connector and a second RS-232 connector. The data terminal ready (DTR) pin of the first RS-232 connector is connected to the DTR pin of the second RS-232 connector, and the clear to send (CTS) pin of the first RS-232 connector is connected to the CTS pin of the second RS-232 connector. The DTR pins are further connected to a power pin of each of the test computers. The test fixture sets a high level voltage for the connected DTR pins, and sets a low level voltage for the connected CTS pins according to the commands of turning on the test computers sent by the control computer, to turn on the test computers. An auto shutdown software included in each of the test computers is executed to shut down the test computers.
Type:
Grant
Filed:
August 17, 2010
Date of Patent:
July 1, 2014
Assignees:
Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
Abstract: An approach is presented for testing a change (i.e., configuration change) in a configuration of a computing environment. A user identifier (ID) of a user is received from an administrative user having an administrative user ID. First configurable attributes of the user ID are determined. A temporary simulation user ID (TSID) having second configurable attributes is generated so that the values of respective first and second configurable attributes are identical. The configuration change is received. The configuration change is associated with the TSID and with no other user ID. Based on the configuration change being associated with the TSID and with no other user ID, a simulation is performed by tracking data record modifications made by the TSID and based on the configuration change. The user ID and administrative user ID are unaffected by the configuration change. After completing the simulation, the data record modifications are undone.
Type:
Grant
Filed:
May 10, 2012
Date of Patent:
May 27, 2014
Assignee:
International Business Machines Corporation
Inventors:
Danny Yen-Fu Chen, Sarah V. White Eagle, Fabian F. Morgan, Siddhartha Upadhyaya
Abstract: A SOC (state of charge) estimation method for a rechargeable battery includes: measuring a battery parameter of the rechargeable battery; judging whether the battery parameter of the rechargeable battery is stable; if the battery parameter of the rechargeable battery is not stable yet, estimating an open circuit voltage of the rechargeable battery by a fuzzy control and expanding an established experiment data of the rechargeable battery into a 3D function by the fuzzy control; and calculating a time domain dynamic equation and converting into a SOC function, substituting the SOC function into the fuzzy control to estimate an SOC estimation value, wherein the time domain dynamic equation performing a time domain dynamic monitor.
Type:
Grant
Filed:
May 12, 2011
Date of Patent:
May 27, 2014
Assignee:
Industrial Technology Research Institute
Abstract: Methods and systems for prediction of fill factor in heterojunction solar cells through lifetime spectroscopy are provided. In accordance with some embodiments, methods for categorizing fill factor in a solar cell are provided, the methods comprising: determining lifetime values of the solar cell at different minority carrier concentrations; determining a lifetime curve shape for the solar cell based on the determined lifetime values; and categorizing the fill factor of the solar cell based on the determined lifetime curve shape using a hardware processor.
Abstract: A method of generating a test sequence diagram includes: linking a first action of the plurality of actions with a second action of the plurality of actions and generating a test sequence diagram which maintains the linking.
Abstract: Methods and systems are provided, which identify specified metrology target abnormalities using selected metrics and classify the identified target abnormalities geometrically to link them to corresponding sources of error. Identification may be carried out by deriving target signals such as kernels from specified regions of interest (ROIs) from corresponding targets on a wafer, calculating the metrics from the target signals using respective functions and analyzing the metrics to characterize the targets.
Type:
Application
Filed:
January 10, 2014
Publication date:
May 15, 2014
Applicant:
KLA-Tencor Corporation
Inventors:
Inna Tarshish-Shapir, Yoel Feler, Anat Marchelli, Berta Dinu, Vladimir Levinski, Boris Efraty, Nuriel Amir, Mark Ghinovker, Amnon Manassen, Sigalit Robinzon
Abstract: An optical fiber analysis device, comprises at least one computer processor, computer memory and wireless network interface. The device also comprises a computer program stored in the computer memory and executable by the at least one processors to: receive and utilize optical fiber field test equipment results, associate the results with newly identified or already known test results, logical connection data, and/or geographical location data, and store the results and their associations in a central object database with similar historic data for the purpose of assessing the integrity of the individual optical fiber segments, the overall level of performance of the individual optical fiber segments, and any change in performance of the individual optical fiber segments over time.
Abstract: Transceiver calibration is a critical issue for proper transceiver operation. The transceiver comprises at least one RF transmit chain and one RF receive chain. A closed loop path is formed from the digital block, the RF transmit chain, the substrate coupling, the RF receive chain back to the digital block and is used to estimate and calibrate the transceiver parameters over the operating range of frequencies. The substrate coupling eliminates the need for the additional circuitry saving area, power, and performance. In place of the additional circuitry, the digital block which performs baseband operations can be reconfigured into a software or/and hardware mode to calibrate the transceiver. The digital block comprises a processor and memory and is coupled to the front end of the RF transmit chain and the tail end of the RF receive chain.
Abstract: One embodiment of the invention is directed to a method comprising receiving instruction data relating to a sample in a sample container. The method includes generating, by at least one processor using a workflow management layer, a process plan for the sample, and providing the process plan to a process control layer. The process plan comprises a plurality of possible routes. The method also comprises selecting, by the at least one processor using the process control layer, an optimized route within the plurality of possible routes in the process plan, and providing the optimized route to a middleware control layer. The at least one processor and middleware control layer are operable to cause a transport system to proceed along the selected route.
Type:
Application
Filed:
November 7, 2013
Publication date:
May 8, 2014
Applicant:
Beckman Coulter, Inc.
Inventors:
Michael Eberhardt, Charles Martinez, Kathleen Payne, Christoph Welte, Bernd Wiedemann
Abstract: In accordance with aspects disclosed herein, impact that a user interface design has on a user's experience is measured. User response to one or more user interface designs is measured. Two or more user interface designs can be compared based on user response to each design. A single user interface design can be evaluated based on one or more measures of user response to the user interface, or two or more user interface designs can be compared using one or more user response measures corresponding to the user interface designs.
Type:
Grant
Filed:
July 7, 2010
Date of Patent:
May 6, 2014
Assignee:
Yahoo! Inc.
Inventors:
Chi-Chao Chang, Yun-Fang Juan, Amr A. Awadallah
Abstract: A method for diagnostic monitoring of a wind turbine generator system, said wind turbine generator system comprising a generator, a drive train, and a number of sensors for providing signals and a control system. The method comprising the selection of three sets of signals from said sensors. From the three sets of signals three conditioned sets of signals are obtained by high pass filtering said first set of signals, low pass filtering the second set of signals, and forming a moving average value on the third set of signals. Based on each of said first, second and third set of conditioned signals an evaluation is performed in order to determine a fault, where said evaluation comprises comparing the first, second and third set of conditioned signals with reference values. If said comparison indicates a fault an alarm is set.
Type:
Application
Filed:
January 17, 2012
Publication date:
May 1, 2014
Applicant:
VESTAS WIND SYSTEMS A/S
Inventors:
Shu Yu Cao, Bing Li, Anshuman Tripathi, Hock Heng Thia, Rasool Beevi D-O Mohamed Arif, Kheng Hong Ang
Abstract: A system and method for verifying the electrical behavior of a liquid crystal display (LCD) driver circuit connected to LCD segments of an electronic circuit includes generating test patterns for verifying the LCD driver circuit. The LCD driver circuit generates LCD stimuli in the form of electrical current based on the test patterns. The current is applied to front and back planes of each LCD segment. Root mean square (RMS) voltages of each LCD segment are determined and compared with predetermined threshold values to verify the state of each LCD segment.
Abstract: Provided is a test apparatus that tests a device under test, comprising: a test module that tests the device under test by sending signals to and receiving signals from the device under test; a test controller that controls the test module; and a network that transmits communication packets between the test module and the test controller, wherein at least one of the test module and the network transmits to the test controller a usage state packet that indicates a usage state of a communication buffer that buffers the communication packets.
Abstract: A testing method and testing system for a semiconductor element are provided. The method includes following steps. A level of a testing electrostatic discharge (ESD) voltage is determined. A plurality of sample components is provided. The testing ESD voltage is imposed on the sample components for testing ESD decay rates of the sample components. ESD withstand voltages of the sample components are detected. The relation between the ESD withstand voltages and the electrostatic discharge rates are recorded to a database. The testing ESD voltage is imposed on the semiconductor element for testing an ESD decay rate of the semiconductor element. The database is looked up according to the ESD decay rate of the semiconductor element to determine an ESD withstand voltage of the semiconductor element.
Type:
Application
Filed:
April 16, 2013
Publication date:
April 17, 2014
Applicant:
Industrial Technology Research Institute
Abstract: A system and method for implementing an integrated information system are provided. A premises server is in communication with a variety of information sources that produce monitoring data for a premises. The premises server collects, presents, and transmits the monitoring device data to a central server capable of processing data from multiple premises servers. The central server receives the data and traverses one or more logical rule sets to determine whether the inputted data violates the rules. Based on an evaluation of the rules, the central server generates outputs in the form of communication to one or more authorized users via a variety of communication mediums and devices and/or the instigation of a variety of acts corresponding to the evaluation of the rules.
Type:
Grant
Filed:
September 14, 2012
Date of Patent:
April 15, 2014
Assignee:
VIG Acquisitions Ltd., L.L.C.
Inventors:
Bruce Alexander, Paul Talley, Jeffrey Hicks
Abstract: Apparatus and method for non-invasive measuring of the sound velocity of a fluid, such as a liquid, flowing in a tubing having points of two different and known transverse length has one sensor mounted at each point connected to a circuit that provides signals to each sensor that are returned to it after passing through the tubing wall and flowing fluid and reflection from the tubing internal wall opposing each sensor and from which the round trip transit time of the signals is measured and the sound velocity calculated from the two measured round trip transit times and the differential between the known transverse lengths. Flexible tubing is placed in the slot of a measuring head which deforms it to provide the two points at one location or the slot has two sections of different transverse length along its length with a point at each section.
Abstract: An integrated circuit includes a transducer and transducer circuitry and additional elements useful in testing the transducer and transducer circuitry. A first power supply terminal and a second power supply terminal are for being directly connected to an external power supply terminal. A power bus is connected to the first power supply terminal. A logic function is for determining if the second power supply terminal is receiving power and if an automatic calibration test of the transducer and transducer circuitry has been run. An automatic calibration is for running an automatic calibration test on the transducer and transducer circuitry if the logic means determines that the second power supply terminal is receiving power and the automatic calibration test of the transducer and transducer circuitry has not been run.
Abstract: The invention provides a method of determining a parameter of a measured electronic device for purposes of programming the device or determining its functionality. A stored reference profile of a reference electronic device includes a respective frequency at each of a plurality of respective temperatures. Heat is simultaneously transferring heat to or from the reference and measured electronic devices while recording a frequency provided by the reference electronic device and a corresponding frequency provided by the measured electronic device at each of a plurality of instances in time. A temperature of the reference electronic device is determined based on the frequency detected for the reference electronic device and the corresponding temperature within the reference profile. The frequency detected from the measured electronic device is then correlated with a temperature the reference electronic device used as the temperature of the measured electronic device.
Abstract: A hand-carriable measurement module of a virtual vector network analyzer including a housing; a test port mounted to the housing; a power and communication interface mounted to the housing; and a circuit disposed within the housing and coupled to the test port and the power and communication interface. The circuit is configured to transmit and receive test signals through the test port for measurement of a device under test; and transmit digitized signals representing the test signals through the power and communication interface to a user interface separate from the housing for presentation to a user.
Type:
Application
Filed:
August 21, 2012
Publication date:
February 27, 2014
Inventors:
Sergey Aleksandrovich Zaostrovnykh, Vladimir Igorevich Ryzhov, Aleksandr Vladimirovich Bakurov, Igor Anatolyevich Ivashchenko, Alexander Isaac Goloschokin
Abstract: A system and method utilize a stand-alone controller for a multiplexed handler test cell in automated and robotic semiconductor test equipment for indexless tandem semiconductor testing. The stand-alone controller is configured such that functions relating to both the handler drivers and the data post-processor of the multiplexed handler tested cell are included within the stand-alone controller. The system and method also include provisions for using a virtual multiplexed handler test cell in a preliminary stage prior to actual implementation of the actual multiplexed handler test cell. This configuration permits the stand-alone controller to control the functions of the multiplexed handlers and to coordinate their activity with the tester.
Abstract: Method and module for judging status alterations of power supplies that are caused by changes of external power sources are provided. Through comparing first, second and third comparison voltages with a stabilized voltage of a voltage stabilization and energy storage element in a power factor correction unit, the status of the power supply can be judged, and an external power supply abnormal signal, a power supply abnormal signal or a power failure alert signal can be generated according to the status to allow a motherboard to perform loading regulation. The power failure alert signal is used to timely stop operation of the power supply, hence can resolve the problems of the conventional techniques such as delay notification, inaccurate judgment or complex composition of judgment circuit.
Abstract: A network system includes a data transfer device that transfers data and a plurality of information processing apparatuses connected to the data transfer device. The information processing apparatuses include a master information processing apparatus and a slave information processing apparatus. The master information processing apparatus includes a controlling unit and a transmitting unit. The controlling unit controls the order and timing in and at which the information processing apparatuses including the master information processing apparatus transmit data to each of the information processing apparatuses. The transmitting unit transmits the data to each of the information processing apparatuses in the order and at the timing controlled by the controlling unit. The slave information processing apparatus includes a transmitting unit that transmits the data to each of the information processing apparatuses in the order and at the timing controlled by the controlling unit.
Abstract: An exemplary method of facilitating communication includes determining a position of a portable communication device that generates a video output. A sound output control is provided to an audio device that is distinct from the portable communication device for directing a sound output from the audio device based on the determined position of the portable communication device.
Abstract: A method for diagnosing the state of health of a battery includes, determining a first state-of-charge value from the battery voltage during partial discharge at constant current, determining a second state-of-charge value from the open circuit voltage of the battery, and calculating the state of health from the difference between the first and second state-of-charge values.
Type:
Grant
Filed:
January 26, 2011
Date of Patent:
November 19, 2013
Assignee:
Commissariat a l'Energie Atomique et aux Energies Alternatives
Abstract: The present invention relates to a system and a method for creating hardware and/or software test sequences and in particular, to such a system and method in which modular building blocks are used to create, sequence and schedule a large scale testing sequence using a matrix like platform.
Abstract: A system incorporating an actuator. The actuator may have a motor unit with motor controller connected to it. A processor may be connected to the motor controller. A coupling for a shaft connection may be attached to an output of the motor unit. The processor may incorporate a diagnostics program. The processor may be connected to a polarity-insensitive two-wire communications bus. Diagnostic results of the diagnostics program may be communicated from the processor over the communications bus to a system controller. If the diagnostic results communicated from the processor over the communications bus to the system controller indicate an insufficiency of the actuator, then an alarm identifying the insufficiency may be communicated over the communications bus to the system controller.
Type:
Grant
Filed:
November 9, 2011
Date of Patent:
November 19, 2013
Assignee:
Honeywell International Inc.
Inventors:
Cory Grabinger, Torrey William McNallan, Daniel Waseen, Adrienne Thomle, Scott McMillan
Abstract: Objects such as manufactured goods or articles, works of art, media such as identity documents, legal documents, financial instruments, transaction cards, other documents, and/or biological tissue are sampled via sequential illumination in various bands of the electromagnetic spectrum, a test response to the illumination is analyzed with respect to reference responses of reference objects. The sequence may be varied. The sequence may define an activation order, a drive level and/or temperature for operating one or more sources. Illumination may be in visible, infrared, ultraviolet, or other portions of the electromagnetic spectrum. Elements of the evaluation system may be remote from one another, for example coupled by a network.
Type:
Grant
Filed:
September 11, 2012
Date of Patent:
November 12, 2013
Assignee:
Visualant, Inc.
Inventors:
Brian T. Schowengerdt, Thomas A. Furness, III, Nicholas E. Walker
Abstract: Ultrasonic inspection equipment facilitates alignment of display positions of three-dimensional ultrasonic inspection data and three-dimensional shape data, and quickly discriminates between a defect echo and an inner-wall echo. A computer 102A has a position correction function of correcting a relative display position between three-dimensional shape data and three-dimensional ultrasonic inspection data. A display position of the three-dimensional ultrasonic inspection data or that of the three-dimensional shape data is moved by a norm of a mean vector along the mean vector that is calculated from a plurality of vectors defined by a plurality of points selected in the three-dimensional ultrasonic inspection data and by a plurality of points selected in the three-dimensional shape data. The three-dimensional shape data and the three-dimensional ultrasonic inspection data are displayed in such a manner as to be superimposed on each other on a three-dimensional display unit 103C.
Type:
Grant
Filed:
May 27, 2009
Date of Patent:
November 12, 2013
Assignee:
Hitachi, Ltd.
Inventors:
So Kitazawa, Naoyuki Kono, Atsushi Baba