Abstract: Arrangement and method for managing set-top boxes used by customers of a content service provider includes at least one automated tester each arranged to couple to set-top boxes and subject each set-top box to a series of automated tests to determine whether each set-top box is functioning properly or requires subsequent repair, and a processor unit coupled to each automated tester for receiving test results therefrom and monitoring testing of set-top boxes via the automated tester(s). Each automated tester is located at a testing facility maintained by the content service provider. A database stores the test results from the automated tester(s) and enables generation of customized reports about the set-top boxes tested by the automated tester(s). A billing system is coupled to each automated tester and to the processor unit and coordinates invoicing for testing performed by the automated tester(s) and repair of set-top boxes at a repair facility.

Abstract: An electrical device includes connectors for an electrical connection to a voltage source, a sampling device for determining a voltage applied to the connectors, a controllable load for changing an electrical power consumption of the device at the connectors, and a control device, which is configured for the purpose of determining a degradation of the electrical connection if voltages, which are applied to the connectors at different electrical power consumptions, differ from one another by more than a predetermined amount.

Abstract: Methods and systems for classifying defects detected on a reticle are provided. One method includes determining an impact that a defect detected on a reticle will have on the performance of a device being fabricated on a wafer based on how at least a portion of the reticle prints or will print on the wafer. The defect is located in the portion of the reticle. The method also includes assigning a classification to the defect based on the impact.

Abstract: Methods and apparatus are provided for managing test procedures for a hardware-in-the-loop (HIL) simulation environment. The apparatus comprises an input interface for receiving input from a user, a first processor coupled to the input interface and in operable communication with the HIL simulation environment. The first processor is configured to generate a test sequence comprising a plurality of test procedure references based on input from the user, wherein each test procedure reference corresponds to a test procedure that comprises instructions for issuing commands to, and receiving data from, the HIL simulation environment, and sequentially execute each referenced test procedure within the generated test sequence in cooperation with the HIL simulation environment, in response to a command from the user.

Abstract: A test table generating device includes a unit group input part, an upstream book analyzing part, a unit characteristic acquiring part, a unit characteristic matching part, and a test table generating section. The upstream book analyzing part analyzes an upstream book about a target unit designated by the unit group input part. The unit characteristic acquiring part acquires the unit characteristics of the target unit based on a result of the analysis. The unit characteristic matching part performs matching of the unit characteristics of the target unit, and specifies a similar unit having the same unit characteristics as those of the target unit. The test table generating section acquires a test table about the similar unit, and generates a test table about the target unit based on the acquired test table.

Abstract: A circuit board testing system and a circuit board testing system for testing a circuit board of keys. The circuit board testing system includes a computer and a test frame. The circuit board is placed on the test frame. The computer includes a script database with plural pin test scripts, a script generation program and a test program. The test program is used for searching a pin test script corresponding to the circuit board from the script database, and testing the circuit board according to the pin test script. If the pin test script is not searched from the script database by the test program, the script generation program is activated to create the pin test script.

Abstract: The invention relates to a method and a system for central computer controlled execution of at least one test run in a scanning microscope, particularly a confocal microscope, wherein at least one first software module of an application software is tested. The invention achieves the aim by a network made of individual scanning microscope clients and a central server. The clients can be contacted via a network interface and are administered in a central directory in the server. The application software for the individual components of a scanning microscope is made of individual software modules, each associated with a potential test. In order to be able to perform the various tests, the scanning microscope clients have been equipped on the hardware side with additional sensors and components that allow various operating parameters to be determined.

Abstract: A test station may include a test host, a test unit, and a test chamber. Multiple devices under test (DUTs) may be placed in the test chamber during wireless testing. Radio-frequency signals may be conveyed between the test unit and the multiple DUTs using a conducted arrangement through a splitter-combiner circuit or using a radiated arrangement through a test antenna in the test chamber. The multiple DUTs may be synced to the test unit one DUT at a time (in series) or in parallel. The test host may direct the test unit to broadcast downlink signals at a given channel. The test host my direct a selected DUT to transmit uplink signals at the given channel or at a selected channel that is different from the given channel. The test unit may be used to perform desired measurement on the uplink signals transmitted from the selected DUT.

Abstract: An apparatus and associated method for non-permanently fixturing an unmounted head gimbal assembly (UHGA). A backing plate has a planar body defining a plurality of contact points, and a lip extending from the body that is operably alignable with the UHGA so that a force applied against the lip transfers through the body to urge each of the contact points against the UHGA.

Abstract: In acquiring and managing measurement data relating to operating parameters of a dissolution tester, operating parameters are measured by operating one or more sensors. The measured operating parameters are transmitted from the sensors to a user computing device. It is then determined whether the measured operating parameters are in compliance or non-compliance with one or more standards, by comparing the measured operating parameters with a plurality of corresponding predefined values. The measured operating parameters and indications of compliance or non-compliance of each measured operating parameter are stored as a data record in a memory local or remote to the user computing device. The data record may be accessible by a computing device remote from the memory. The operating parameters may include, for example, shaft parameters.

Abstract: An apparatus for testing multiple Small Form-Factor Pluggable Plus (SFP+) ports comprising: a first testing module; a second testing module; and a communications link coupled with the first and the second testing modules; wherein each of the testing modules includes: a SFP+ interface connectable to a port under test (PUT), a signal processing circuit including: a signal compensator configured to perform signal compensation on a signal received from the other testing module, and a signal modifier configured to: modify the compensated signal according to a set of predetermined modification parameters, and transmit the modified signal to the PUT.

Abstract: The present invention discloses an algorithm integrating system and an integrating method thereof. The algorithm integrating system comprises a receiving module, an analyzing module, and a processing module. The receiving module receives at least one test algorithm. The analyzing module is connected to the receiving module and analyzes the at least one test algorithm to obtain at least one basic element from the at least one test algorithm. The processing module is connected to the analyzing module and screen out the at least one non-duplicate basic element based on the at least one basic element. Then, the processing module integrates the at least one non-duplicate basic element and generates a testing module.

Abstract: Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.

Abstract: The invention concerns a method for determining a calibration value indicating the extent of loss of calibration of a group of three or more sensors in a sensor network, the method involving receiving a plurality of data values captured over a period of time by each of the sensors, determining by a processing unit (404) at least one correlation value associated with each sensor, each correlation value corresponding to the correlation between the data values captured by the associated sensor and the data values captured by at least one other sensor; extracting by a high pass filter (410) a noise component of the correlation values and outputting the calibration value determined based on the difference between the noise component and a reference noise value.

Abstract: Provided is a semiconductor test apparatus that tests a device under test, comprising a test unit that tests a device under test; and a serial transmitting section that transmits transmission data back and forth between the test unit and a control section controlling the test unit. The serial transmitting section includes a data sending section that sends a plurality of pieces of the transmission data in a predetermined order; a resending control section that resends the transmission data; and an expected acknowledgement ID storage section that stores an expected acknowledgement ID indicating identification data that is expected to be attached to an acknowledgement signal received on a transmission side. The resending control section judges whether resending is necessary based on (i) whether resend count information indicates that a piece of transmission data is resent data and (ii) the expected acknowledgment ID in the expected acknowledgement ID storage section.

Abstract: Method for identification of at least one parameter of a sampling system includes transmitting at least one input signal to at least one channel of the sampling system; measuring at least one output signal of the sampling system in response to sampling of the at least one input signal by the receiver; and determining, using a processor, the at least one parameter of the sampling system using the at least one input signal and the at least one output signal of the sampling system. A system for identification of at least one parameter relating to a sampling system in response to at least one input signal is also provided.

Abstract: A test system for testing an image processor of an electronic device by controlling the image processor to playback a test image divided into several pixel areas is provided, therein, each pixel area includes several rows of pixels, and pixel values of the rows of pixels of one pixel area are respectively the same. The test system includes a storage device, a test module, and a test device. The storage device stores a pixel value of one row of each pixel area, and position of the pixel areas of the test image (test data). When the electronic device connects to the storage device, the test module invokes the test data from the storage device, recovers the test image according to the test data, and controls the image processor to produce a corresponding image signal. The test device judges performance of the image processor according to the image signal.

Abstract: In one aspect, a network-centric processing (NCP) system includes sensors configured to monitor activities associated with testing of an asset, a first system configured to provide the testing on the asset, a second system configured to provide training of personnel using the asset, a third system configured to record problems associated with the testing and the training of the asset as input for an acquisition process and a network connected to the first system, the second system, the third system and the sensors.

Abstract: The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node.

Abstract: A test circuit provided to monitor a bandgap circuit that outputs a bandgap reference voltage The test circuit includes a reference voltage test module to output a first pass signal when an operating voltage of the bandgap circuit is greater than a first threshold voltage; an output test module to output a second pass signal when an output voltage of the bandgap circuit is greater than a second threshold voltage; and an overdrive test module to output a third pass signal when a minimum operating voltage of the test circuit is detected. Furthermore, a logic circuit is provided and coupled to outputs of each of the test modules. The logic circuit is further configured to output an operating signal, which indicates that the bandgap reference voltage is stable, after receiving the first, second, and third pass signals.

Abstract: A three-dimensional (3D) chip is fabricated from components that have been cut out of a two-dimensional (2D) chip. The components from the 2D chip are layered and coupled to create the layers of the 3D chip. By testing the 2D chip first, the layers of the 3D chip have been pre-tested, thus reducing testing and production costs.

Abstract: An apparatus and method for performing medical, biological or chemical tests in the field is disclosed. In some embodiments, the test media comprises a special purpose optical disc which is read, after application of the test specimen and subsequent processing, using commonly available CD, DVD, High Definition DVD or Blu-Ray optical disc players.

Abstract: A test system that provides an output signal for analysis without requiring the test hardware to be idle during a settling interval. The test system includes a preprocessor that identifies the near-DC drift that occurs in the output signal and then adjusts the output signal to remove the near-DC drift. A set of values representing the near-DC drift at each of multiple times during the acquisition of a signal for analysis may be computed and used to model a settling profile of the signal by fitting a curve to the set of values. The model of the settling profile may then be subtracted from samples representing the output signal to provide an adjusted signal for further analysis.

Abstract: A method for detecting a cable fault in a cabling of a flow meter is provided according to an embodiment of the invention. The method includes testing one or more first pickoff wires and one or more second pickoff wires of the cabling for pickoff open wire faults. The method further includes testing the first pickoff wires and the second pickoff wires for pickoff connection orientation faults if no pickoff open wire faults are determined in the first pickoff wires and the second pickoff wires. The method further includes testing one or more driver wires of the cabling for driver open wire faults. The method further includes testing the driver wires for a driver connection orientation fault if no driver open wire faults are determined in the driver wires.

Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Abstract: It is possible to provide a semiconductor test program debug device capable of reducing the unnecessary facilities when using a semiconductor test device or a semiconductor test program of different specification.

Abstract: Disclosed herein is a transmission/reception channel matching apparatus for a mobile communication terminal and a mobile phone test equipment. The transmission/reception channel matching apparatus includes a Printed Circuit Board (PCB), a Dual In-line Package (DIP) switch, and a fastening casing. The PCB includes mobile communication terminal-side terminals to be electrically connected to option pins provided in the serial communication connector of the mobile communication terminal, and transmission and reception terminals corresponding to the transmission and reception channels of the mobile phone test equipment for transmitting a transmission signal to the mobile communication terminal and receiving a reception signal from the mobile communication terminal. The DIP switch is provided with a plurality of switches, is combined with the PCB, and selectively connects the mobile communication terminal-side terminals to the transmission and reception terminals depending on ON/OFF information.

Abstract: Identifying systematic defects in wafer processing including performing defect inspection of a plurality of wafers, identifying defects in each of the plurality of wafers as not being associated with a trivial and/or known root cause, determining a physical location on each wafer where each of the defects occurs and correlating the physical locations where each of the defects occurs with cell instances defined for those physical locations.

Abstract: A method and apparatus for adaptively adjusting the operating voltage of an integrated circuit in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations, or reliability wearout mechanisms. The minimum operating voltage of an integrated circuit is determined either during external testing of the integrated circuit or during built-in-self-testing. The minimum operating voltage is transmitted to a variable voltage regulator where it is used to set the output of the regulator. The output of the regulator supplies the integrated circuit with its operating voltage. This technique enables tailoring of the operating voltage of integrated circuits on a part-by-part basis which results in power consumption optimization by adapting operating voltage in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms.

Abstract: In an embodiment, an apparatus comprises one or more registers and a control unit coupled to the one or more registers. The control unit is configured to monitor a power state in one or more memory modules during execution of an application, and to store data generated during the monitoring in the one or more registers. In an embodiment, a system comprises a memory controller and a plurality of memory module interface units (MMIUs) coupled to the memory controller. Each of the plurality of MMIUs: is coupled to a respective plurality of memory modules; comprises one or more registers; is configured to monitor a power state in the respective plurality of memory modules during execution of an application; and is configured to store data generated during the monitoring in the one or more registers.

Abstract: A method, a system, and a computer program product for managing one or more electronic devices. Performance of an electronic device is monitored and presented to a user through a digital agent interface. The performance of the electronic device is controlled automatically by digital agent through the digital agent interface. The invention also enables automatic testing of the electronic device through the digital agent interface by setting up test configurations, activating test signals, and interpreting any error codes that may be generated.

Abstract: Automatically determining operating parameters of a power management device is described.

Abstract: Various embodiments for determining dynamic care areas are provided.

Abstract: A method, information processing system, and computer program storage product for associating jobs with resource subsets in a job scheduler. At least one job class that defines characteristics associated with a type of job is received. A list of resource identifiers for a set of resources associated with the job class is received. A set of resources available on at least one information processing system is received. The resource identifiers are compared with each resource in the set of resources available on the information processing system. A job associated with the job class with is scheduled with a set of resources determined to be usable by the job based on the comparing.

Abstract: A method for testing an electronic device is implemented with a host computer. The host computer detects a test status of the electronic device. The host computer stores a test order table that indicates the test status and test order corresponding to the test status. The host computer transmits a test order based on the test status and the test order table to the electronic device. The electronic device executes a self-test based on the test order.

Abstract: In some embodiments, a method for testing a chassis including one or more information handling systems is provided. The method includes receiving a chassis configuration specification that defines a set of required components for a chassis configuration, generating one or more test images based at least the received chassis configuration specification, automatically determining components of the chassis, testing the determined components of the chassis using the one or more generated test images, and reporting results from the testing to a user.

Abstract: Systems and methods are disclosed for a self-testing power management unit (PMU) in an electronic device. Self-testing may enable the testing of PMU power supply outputs while reducing the need for test points to conserve circuit board real estate. In one embodiment, a PMU is placed in self-test mode, and a test controller may perform capacitance tests on each power supply output. Once the capacitance test has been performed on each power supply output, the PMU may be placed in normal operating mode, and voltage tests may be performed on each power rail. Once voltage tests have been performed on all power rails in the PMU, the self-test may be complete. In some embodiments, the test controller may communicate with a test multiplexer to select the power supply output for testing. Further, the measurements resulting from the capacitance and voltage tests may be converted to a digital signal through an analog-to-digital converter on the PMU.

Abstract: Systems and methods for managing optical inspection target components are disclosed. A method may include, but is not limited to: storing at least one external recipe component at an inspection tool node; associating at least one proxy component with the at least one external recipe component; associating the at least one external recipe component with at least one optical inspection target recipe; and storing the at least one optical inspection target recipe including the at least one proxy component in a recipe distribution server. A method may include, but is not limited to: receiving a selection of at least one recipe associated with an optical inspection target to be inspected at a first inspection tool node; and determining whether one or more external recipe components associated with the recipe are stored on at least one of the first inspection tool node and a second node.

Abstract: An electrical test system for providing a power source to each of a plurality of electrical components under electrical test includes a grouped circuitry module. The grouped circuitry module includes a plurality of individually-programmable power sources, each coupled to an output channel, a controller configured to program each of the power sources to a respective stimulus output value and to read a measured value at each corresponding output channel and random access, non-volatile, memory for storing information and for providing read/write capability for the controller. A host computer is in communication with the controller for running a self test program that sequentially programs each of the power sources to its respective stimulus output value and reads the measured value at each corresponding output channel using the controller to determine if the tested complete subsystem is operating properly.

Abstract: The disclosed device performs a control of generating a test pattern for the delay test of LSI. The input pattern control circuit counts a cycle number of an input pattern supplied to a test object circuit, and stops supply of the input pattern to the test object circuit when the cycle number of the input pattern coincides with a certain count number. The scan control circuit receives a control signal from the input pattern control circuit, and supplies a scan shift signal to the test object circuit to shift a scan chain in the test object circuit.

Abstract: Nuclear image data generated by a multimodal imaging device, such as a combined position emission tomography (PET)/magnetic resonance (MR) scanner (12, 14), is attenuation-corrected with a combined patient-specific attenuation correction (AC) map and an AC map template (70) for an MR coil (72) that is present in both the nuclear and MR scanning procedures. template library (46) contains templates for each of a plurality of MR coils and other accessories. Each template is generated on one of two manners. The coil may be imaged inside the PET scanner 14 with the transmission source 16 (e.g., Ge-68 or Cs-137). A transmission image 48 is reconstructed using the known algorithms and may be used as the AC template directly. Alternatively, the template can be generated by creating a global histogram of the transmission image and identifying segments of the coil or other accessory. An average linear attenuation coefficient (LAC) value is determined from the distribution of the histogram.

Abstract: A system is used to test whether a device works normally in a preset frequency range. The system presets a frequency range, and controls a frequency generator to send a test frequency signal to the device according to each of a predetermined number of frequencies of the frequency range, and tests whether the device and electronic parts of the device can work normally to obtain test results.

Abstract: A lightweight radio/CD player for vehicular application is virtually “fastenerless” and includes a case and frontal interface formed of polymer based material that is molded to provide details to accept audio devices such as playback mechanisms (if desired) and radio receivers, as well as the circuit boards required for electrical control and display. The case and frontal interface are of composite structure, including an insert molded electrically conductive wire mesh screen that has been pre-formed to contour with the molding operation. The wire mesh provides EMC, RFI, BCI and ESD shielding and grounding of the circuit boards via exposed wire mesh pads and adjacent ground clips. The PCB architecture is bifurcated into a first board carrying common circuit components in a surface mount configuration suitable for high volume production, and a second board carrying application specific circuit components in a wave soldered stick mount configuration.

Abstract: In a method and to a device for identifying an erroneous algorithm (A), data output by a1) of the algorithm (A) to be tested and/or a2) a reference algorithm (B) are categorized, and the reference frequency (R(A), R(B)) at which data of at least one category (Kx) occur during operation for the case a1) of the algorithm (A) to be tested or for case a2) of the reference algorithm (B) is determined in a reference phase. The test frequency (T(A)) at which data of at least one category (Kx) occur during operation of the algorithm (A) to be tested is determined in a test phase. Finally, an error message is output if the deviation of the test frequency (T(A)) of at least one category (Kx) from the reference frequency (R(A), R(B)) of the same category (Kx) exceeds a specific threshold value (THR).

Abstract: The present invention refers to a method for the precise measurement of dependency on amplitude and phase of a plurality of high frequency signals, preferably in the synchrotron accelerator of elementary particles. The essence of the solution according to the invention lies in that with a single measuring device and without any aliasing it is achieved a resolution of 0.2 micron and repeatability of measurements of 1 micron down to the lower frequency limit of a few MHz.

Abstract: A test module comprising a compression information storage section that stores compression information associating pattern sequences, pattern sequence identification information, and repetition information with each other; a basic pattern storage section that stores, as a group of basic patterns, pattern sequence data that includes a pattern sequence or pattern sequence identification information in association with a command; an instruction information storage section that stores instruction information; a basic pattern reading section that reads pattern sequence data; a pattern sequence reading section that, when the pattern sequence identification information is included in the pattern sequence data, references the compression information and reads the pattern sequence corresponding to the pattern sequence identification information; and a pattern output section that repeatedly outputs, according to the number of repetitions designated by the repetition information, the pattern sequence corresponding to th

Abstract: A near field apparatus comprises a Radio Frequency (RF) coil including at least one of a shorting bridge from a first point to a second point along an electrical path of the RF coil and/or a discontinuity in the electrical path of the RF coil.

Abstract: An internal precision oscillator (IPO) is trimmed within a microcontroller integrated circuit. The microcontroller integrated circuit receives a test program into flash memory on the microcontroller integrated circuit from a tester. The microcontroller integrated circuit also receives a reference signal from the tester. The IPO generates a clock signal having a frequency that depends upon a trim value. A general purpose timer on the microcontroller integrated circuit counts the number of cycles of the clock signal during a time period defined by the reference signal and outputs a digital value. A processor on the microcontroller integrated circuit executes the test program, reads the digital output, and adjusts the trim value such that the frequency of the clock signal is calibrated with respect to the reference signal. Test-time on the tester is reduced because the decision making during the frequency trimming process is made by the processor instead of the tester.

Abstract: A test fixture includes a first RS-232 connector and a second RS-232 connector. The data terminal ready (DTR) pin of the first RS-232 connector is connected to the DTR pin of the second RS-232 connector, and the clear to send (CTS) pin of the first RS-232 connector is connected to the CTS pin of the second RS-232 connector. The DTR pins are further connected to a power pin of each of the test computers. The test fixture sets a high level voltage for the connected DTR pins, and sets a low level voltage for the connected CTS pins according to the commands of turning on the test computers sent by the control computer, to turn on the test computers. An auto shutdown software included in each of the test computers is executed to shut down the test computers.

Abstract: The invention is an apparatus and method including hardware and software, which allows collecting and analyzing data to obtain information about mechanical properties of soft materials in a much faster way. The apparatus can be used as a stand-alone deice or an add-on to the existing AFM device. The apparatus allows collecting dynamical measurements using a set of multiple frequencies of interest at once, in one measurement instead of sequential, one frequency in a time; measurements.