Testing System Patents (Class 702/108)
  • Publication number: 20110270566
    Abstract: The present invention provides a scheduling device which can carry out scheduling of process execution periods of time, included in plural pieces of processing target data, respectively. The scheduling device sorts out plural pieces of substance data by looking up a retention time, included in each of the plural pieces of substance data. The scheduling device groups the plural pieces of substance data into a plurality of functions Fn so that pieces of substance data, included in each of the plurality of functions Fn, is successively arrayed in an order resulting from the sorting. Further, the scheduling device finds, for each of the plurality of functions Fn, a function range between a detection start time included in that function Fn and a detection end time included in that function Fn, and groups the plurality of functions Fn into a measurement group(s) In so that an interval between functions Fn included in the same measurement group is more than a condition set in advance.
    Type: Application
    Filed: November 17, 2010
    Publication date: November 3, 2011
    Applicant: RIKEN
    Inventors: Yuji SAWADA, Masami HIRAI
  • Patent number: 8050793
    Abstract: A method includes providing a design data file specifying at least one target feature on a first reticle. A reticle qualification data file specifying a plurality of feature measurements associated with features formed using the first reticle is provided. At least one of the feature measurements is linked to the target feature on the first reticle. The target feature and the linked feature measurement are stored in a data store.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: November 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrew Haskins, Chunliang Xia
  • Patent number: 8046187
    Abstract: A test system is described for testing a media drive, such as a tape drive. The test system includes a host emulator, a storage library emulator, and a control system. The host emulator communicates with a first interface of the media drive and mimics a host system to the media drive. The storage library emulator communicates with a second interface of the media drive and mimics a storage library system to the media drive. When in operation, one of the host emulator and the storage library emulator transmits a test message to the media drive responsive to an instruction from the control system. Responsive to the test message, one of the emulators receives a test response from the media drive and transmits the test response to the control system. The control system processes the test message and the test response to evaluate the performance of the media drive.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: October 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Craig A. Klein, William W. Owen, Winnie Hiu-Tung Tsang
  • Publication number: 20110254580
    Abstract: A method provides an improved checking of repeatability and reproducibility of a measuring chain, in particular for quality control by semiconductor device testing. The method includes testing steps provided for multiple and different devices to be subjected to measurement or control through a measuring system that includes at least one chain of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement or control. Advantageously, the method comprises checking repeatability and reproducibility of each type of unit that forms part of the measuring chain and, after the checking, making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement or control.
    Type: Application
    Filed: April 22, 2011
    Publication date: October 20, 2011
    Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (GRENOBLE) SAS
    Inventors: Sergio Tenucci, Alberto Pagani, Marco Spinetta, Bernard Ranchoux
  • Publication number: 20110257903
    Abstract: A device is disclosed for performing non-destructive inspection and testing (NDT/NDI) of an elongated test object, wherein the inspection system includes: a test object conveyor for conveying the test object along a longitudinal conveyance path; a probe assembly including phased-array probes, the probe assembly being configured to induce signals in the test object and sense echoes reflected from the test object; a probe assembly conveyor configured to movably support the probe assembly, to move the probe assembly on a circumferential path about the test object; and a control system coupled to the test object conveyor and to the probe assembly conveyor and configured to allow data acquisition by and from the phased-array probes while, simultaneously, the test object moves along the longitudinal path and the phased-array probes move on the circumferential path.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 20, 2011
    Applicant: OLYMPUS NDT INC.
    Inventors: Christophe IMBERT, Michael DRUMMY
  • Patent number: 8028100
    Abstract: An automated processing system that includes providing an intelligent module with a composite connection for transmitting information and configuring the intelligent module within the automated processing system for automatic recognition.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: September 27, 2011
    Assignee: Data I/O Corporation
    Inventors: Lev M. Bolotin, Bradley Morris Johnson, Carl W. Olson
  • Patent number: 8019049
    Abstract: A method for generating reliability tests for a telephone system is based upon sampling an orthogonal array which covers various combinations of test parameters. Field data is collected of actual telephone activity on a telephone system. The field data is evaluated so as to determine call-mix characteristics. Probabilistic weights for the different call-mix characteristics are obtained, and then the probabilistic weights are used to sample the test case scenarios generated in the orthogonal array which have the same call-mix characteristics. These test case scenarios are used to run tests on the telephone system. These tests are preferably performed using automated test scripts. After the test data is collected, reliability metrics are calculated from the test data.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: September 13, 2011
    Assignee: Avaya Inc.
    Inventors: James J. Allen, Jr., Janet Kenny, John Yeager, Muharrem Umit Uyar, Linda Yeager
  • Patent number: 8019564
    Abstract: A method for calibrating the loop bandwidth of a phase-locked loop (PLL) is described. At least one resistor in the PLL filter is tuned in accordance with the frequency of an input reference signal. One or more capacitors in the PLL filter are tuned in accordance with the frequency of the input reference signal. Output pulses of one or more voltage controlled oscillators (VCO) are counted. A first charge pump current associated with a target loop bandwidth is counted in accordance with the counted output pulses. A programmable charge pump current is tuned to the calculated first charge pump current.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: September 13, 2011
    Assignee: QUALCOMM Incorporated
    Inventor: Chan Hong Park
  • Patent number: 8020130
    Abstract: In a timing analysis apparatus for use in a semiconductor integrated circuit, which analyzes operation timing of a semiconductor integrated circuit having a logic gate circuit including a plurality of logic gates, a controller detects at least one of a power supply voltage and a ground voltage of a power supply, decomposes the noise waveform into frequency components, classifies the frequency components into low-frequency components lower than a predetermined threshold frequency and high-frequency components higher than the threshold frequency, calculates a static delay time of each of the logic gates due to the low-frequency components, calculates a dynamic delay time of each of the logic gates due to the high-frequency components, and determines a delay time of each of the logic gates by synthesizing the calculated respective delay times.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: September 13, 2011
    Assignee: Semiconductor Technology Academic Research Center
    Inventor: Makoto Nagata
  • Publication number: 20110218754
    Abstract: In a solder printing inspection machine, an identification code and an inspection time of an inspection target board are accumulated in a memory. The accumulated data, whose identification code is matched with that of the current inspection target board, is searched while the accumulated data is traced back one by one. When the corresponding board is found, it is recognized that the board is extracted because of the defective board and the inspection target board is the reintroduced board that was previously extracted. A graph, in which pieces of information expressing the pieces of quality of the boards are arrayed in time series, is produced based on each time of inspection result and the graph is displayed on a monitor. In the pieces of data included in the graph, the data corresponding to the board that is recognized as the reintroduction is explicitly shown by a letter “R”.
    Type: Application
    Filed: February 24, 2011
    Publication date: September 8, 2011
    Applicant: OMRON CORPORATION
    Inventor: Hiroyuki Mori
  • Patent number: 8014969
    Abstract: There is provided a test apparatus for testing a plurality of devices under test. The test apparatus includes a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals, a combining section that generates a single combination signal by using the response signals output from the devices under test, and a judging section that judges whether the devices under test operate normally with reference to the combination signal.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: September 6, 2011
    Assignee: Advantest Corporation
    Inventors: Hirokatsu Niijima, Koji Hara, Noriyoshi Kozuka, Kohei Shibata, Tetsuya Sakaniwa
  • Publication number: 20110208464
    Abstract: In a report generation system and method, one or more test parameters, a measured characteristic, and value ranges of the measured characteristic are set. Values of the one or more test parameters and the measured characteristic are retrieved from measurement data. The values are arranged to create a report of the measured characteristic versus the one or more test parameters. Each of the values of the measured characteristic is classified into one of the value ranges. The report is marked according to the value ranges of the values of the measured characteristic.
    Type: Application
    Filed: June 27, 2010
    Publication date: August 25, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHIEN-HUNG LIU, HSIEN-CHUAN LIANG, SHOU-KUO HSU
  • Publication number: 20110208465
    Abstract: Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; a control apparatus that controls the test unit; and a relay apparatus that relays between the control apparatus and the test unit. The relay apparatus includes a first communicating section that receives a command from the control apparatus to the relay apparatus and transmits the command to the test unit; a second communicating section that receives a return command that is transmitted back to the relay apparatus by the test unit that received the command; and an executing section that executes a process designated by the return command, in response to the second communicating section receiving the return command.
    Type: Application
    Filed: November 12, 2010
    Publication date: August 25, 2011
    Applicant: ADVANTEST CORPORATION
    Inventor: Kazumoto TAMURA
  • Patent number: 8006156
    Abstract: Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual operation timing of a logical circuit to be tested, ii) logical simulation block performs simulation by using delay times of signal paths corrected by adding minimum slack margin, and iii) when the simulation indicates that an end-side flip-flop cannot acquire data after an expected transition of logical value, masking block generates mask data that masks data held in the end-side flip-flop.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: August 23, 2011
    Assignee: Kawasaki Microelectronics, Inc.
    Inventor: Hiromi Kojima
  • Patent number: 8006154
    Abstract: A semiconductor integrated circuit includes a clock generator for generating a second clock signal having a frequency that varies over time by using a first clock signal having a fixed frequency, a test circuit for generating a digital signal according to a difference between a first frequency corresponding to the first clock signal and a second frequency corresponding to the second clock signal by a digital logic operation based on the first clock signal and the second clock signal, and a signal path for outputting the digital signal generated by the test circuit.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: August 23, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Shunichiro Masaki
  • Publication number: 20110202301
    Abstract: The present invention relates to middleware test component operating method and device. It is possible to improve the system capacity and the efficiency of an SDR (Software Defined Radio) system through the reconfiguration of the system according to a user's request by reconfiguring a test component for the capacity measurement of installation and test of a software component and capacity measurement of the communication port using the SDR system in a wireless communication system.
    Type: Application
    Filed: September 11, 2008
    Publication date: August 18, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jun Sik Kim, Nam Hoon Park
  • Patent number: 8001486
    Abstract: A method for automatically verifying one or more features of file-based media content (108) is disclosed. This file-based media content includes one or more media content files. The method includes customizing (204) a test plan on the basis of the one or more features. Customizing the test plan includes creating, modifying or utilizing at least one media content check of one or more media content checks. A media content check verifies at least one feature of the one or more features of the file-based media content. Further, the method includes verifying (206) the one or more features, based on the customized test plan. The method also includes documenting (208) the results obtained from the verification of the one or more features.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: August 16, 2011
    Assignee: Interra Systems, Inc
    Inventors: Shailesh Kumar, Manik Gupta, Vivek Koul
  • Patent number: 8000919
    Abstract: A method useful for the characterization of a fixture splits a partially symmetric THRU structure into portions which may then be mathematically removed from both ports of a 2-port measured structure, leaving only the desired device under test (DUT).
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: August 16, 2011
    Assignee: Tektronix, Inc.
    Inventor: Kan Tan
  • Publication number: 20110196638
    Abstract: Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; a control apparatus that controls the test unit; and a relay apparatus that relays between the control apparatus and the test unit. The relay apparatus includes a read issuing section that receives a command from the control apparatus and issues a read command for reading read data stored at an address designated by the control apparatus in a storage apparatus of the test unit; a buffer section that buffers the read data transmitted from the test unit in response to the read command; and a data transmitting section that receives the read command from the control apparatus and sends back the read data buffered in the buffer section.
    Type: Application
    Filed: November 9, 2010
    Publication date: August 11, 2011
    Applicant: ADVANTEST CORPORATION
    Inventor: Kazumoto Tamura
  • Publication number: 20110196640
    Abstract: Provided is a test apparatus that tests a device under test having a plurality of output terminals. The test apparatus comprises an executing section that executes a test command sequence for testing the device under test; a storage section that stores a plurality of pieces of setting data designating one or more output terminals among the plurality of output terminals; a detecting section that detects whether a value of an output signal from an output terminal designated by one of the pieces of setting data matches an expected value; and a selecting section that selects different pieces of setting data in the storage section when at least two detection commands, which change execution sequencing of the test command sequence according to the detection results of the detecting section, are executed, and supplies the selected pieces of setting data to the detecting section.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 11, 2011
    Applicant: ADVANTEST CORPORATION
    Inventors: Kuniyuki KANEKO, Naoyoshi WATANABE
  • Publication number: 20110196639
    Abstract: Computer-implemented methods, computer-readable media, and systems for determining one or more characteristics of a wafer are provided.
    Type: Application
    Filed: June 19, 2009
    Publication date: August 11, 2011
    Applicant: Kla-Tencor Corporation
    Inventors: Haiguang Chen, Daniel Kavaldjiev, Louis Vintro, George Kren
  • Publication number: 20110194075
    Abstract: Embodiments provide methods and systems for the modeling and analysis of visual fields. Methods for global and regional measurement of visual sensitivity and quantification of field loss are provided in accordance with various embodiments. Further embodiments provide systems and methods for the diagnosis of diseases affecting the visual field. In addition, embodiments provide methods and systems for measuring and quantifying the volume of the Hill of Vision for an individual subject.
    Type: Application
    Filed: October 28, 2009
    Publication date: August 11, 2011
    Applicant: Oregon Health & Science University
    Inventors: Richard G. Weleber, Richard E. Crandall, Scott P. Gillespie
  • Patent number: 7996173
    Abstract: Objects such as manufactured goods or articles, works of art, media such as identity documents, legal documents, financial instruments, transaction cards, other documents, and/or biological tissue are sampled via sequential illumination in various bands of the electromagnetic spectrum, a test response to the illumination is analyzed with respect to reference responses of reference objects. The sequence may be varied. The sequence may define an activation order, a drive level and/or temperature for operating one or more sources. Illumination may be in visible, infrared, ultraviolet, or other portions of the electromagnetic spectrum. Elements of the evaluation system may be remote from one another, for example coupled by a network.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: August 9, 2011
    Assignee: Visualant, Inc.
    Inventors: Brian T. Schowengerdt, Thomas A. Furness, III, Nicholas E. Walker
  • Patent number: 7987063
    Abstract: Automated test equipment (ATE) used to test semiconductor components during the manufacturing process. The ATE generates and measures signals at test points of a device under test. The ATE includes a signal formatter with an SR latch having set an reset inputs each connected through or coupled to a number of signal channels. Each signal channel may receive a long pulse from a timing generator and generate a short pulse. Each signal channel has a current steering circuit that couples the short pulses to the set or reset ports of the latch. Because the outputs of each current steering circuit have a high impedance when not sending a pulse, multiplexing circuitry and/or circuitry to logically OR the outputs of separate signal channels are unnecessary. The hardware eliminated by this design simplifies and improves the ATE. Additionally, the latch can be set and reset in quick succession with good timing resolution.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: July 26, 2011
    Assignee: Teradyne, Inc.
    Inventors: David Coyne, Igor Abrosimov
  • Patent number: 7987064
    Abstract: The present disclosure is directed to a method for determining dynamic test coverage for a product. The method may comprise: receiving a customer order, the customer order comprising at least one product configuration; receiving a rule set associated with the at least one product configuration; analyzing the rule set to determine a proxy part to add to the at least one product configuration; providing the proxy part an indicator; adding the proxy part to the at least one product configuration; iteratively comparing the product configuration to the rule set until the product configuration meets the rule set; providing a test associated with the at least one product configuration; receiving at least one signal from at least one indicator; and removing at least one proxy part from the at least one product configuration.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Steven C. Erickson, Fraser A. Syme, William Robert Taylor
  • Patent number: 7982620
    Abstract: Embodiments of the present invention include systems and methods for reducing driver boredom for the driver of a vehicle particularly for vehicle environments such as straight roads and lack of traffic that are likely to induce boredom. An example system includes an electronic circuit such as a computer, a vehicle environment monitor, a driver interface, and a driver stimulation device such as a semitransparent display.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: July 19, 2011
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Danil V. Prokhorov, Steven F. Kalik, Chenna K. R. Varri
  • Patent number: 7982155
    Abstract: A system of testing semiconductor devices includes a classification module configured to classify a plurality of lots into a plurality of groups; an apparatus assignment module configured to assign a plurality of testing apparatuses to each of the groups; and a test recipe creation module configured to create a test recipe to test defects in a second group other than a first group specified in the groups, the test recipe including a definition of testing positions in the second group defined by a rule different from the first group.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: July 19, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masafumi Asano
  • Patent number: 7979219
    Abstract: The invention provides a method for testing a transmission medium used in a full-duplex communication system comprising an endpoint that comprises a transmitting end (TX) and a receiving end (RX); the method comprises the steps of: first, transmitting a transmitted signal which comprises a test signal sequence with a high auto-correlation characteristic; then, receiving a received signal, and performing a correlation operation on the test signal and the received signal; finally, according to the result of the correlation operation, determining the impedance matching condition of the transmission medium.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: July 12, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kuang-Yu Yen, Meng-Han Hsieh, Hou-Wei Lin, Chi-Shun Weng
  • Patent number: 7979232
    Abstract: Apparatus, systems, and methods for testing SAS cables by applying a signal to one end of a SAS cable, receiving the signal from another end of the SAS cable, and generating an output of information relating to the testing. The testing apparatus may test one or more configuration characteristic of the SAS cable, including, for example a crossover status, a polarity status of transmit (“TX”) wires, and a polarity status of receive (“RX”) wires.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: July 12, 2011
    Assignee: LSI Corporation
    Inventors: Brian K. Einsweiler, Luke E. McKay, Steven F. Faulhaber
  • Patent number: 7974809
    Abstract: Systems and methods for monitoring, managing, and testing power systems are disclosed. In various embodiments, a site server collects data from one or more generators, automatic transfer switches, sensors, and cameras at a site. The site server stores captured data and triggers alarm events when preselected limits are exceeded. The site server also enables users to configure, initiate, pause, resume, monitor, and abort scripted tests of the monitored entities. In some of these and other embodiments, an enterprise-wide server collects data from multiple site servers, makes the data available via a web-based or other client interface, and provides consolidated monitoring, alarm, test management, and management resources.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: July 5, 2011
    Assignee: Blue Pillar, Inc.
    Inventors: Bradley Jay Witter, Thomas Joseph Butler
  • Publication number: 20110156742
    Abstract: A chip testing circuit is disclosed. The chip testing circuit uses a judging circuit to switch the connection of the data compressing circuit between data compressing base units which compresses 4 XIOs, so as to obtain testing data by one single interface circuit and to increase the testing throughput.
    Type: Application
    Filed: September 8, 2010
    Publication date: June 30, 2011
    Inventors: Der-Min Yuan, Yi-Hao Chang, Peng-Yu Chen
  • Publication number: 20110161039
    Abstract: A method of testing an electronic device is disclosed. The electronic device includes an embedded controller. The method includes storing a type information of the embedded controller and transmitting the type information to an application module through a data module. The application module analyzes the type information to obtain a command The application module sends the command to the embedded controller. The embedded controller returns a testing result to the application module. The application module generates a testing report after the application module compares the testing result with a predetermined result.
    Type: Application
    Filed: March 2, 2010
    Publication date: June 30, 2011
    Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Qing-Hua Liu
  • Patent number: 7970572
    Abstract: A method of detecting a free fall of a device includes measuring an acceleration of the device, calculating an integral of the acceleration, and determining whether the acceleration is periodic. If the acceleration is not periodic, the integral of the acceleration is compared with a first critical value to determine whether the device falls freely. If the acceleration is periodic, the integral of the acceleration is compared with a second critical value to determine whether the device falls freely. The first and second critical values are different. Since whether the device is periodically accelerated is considered, free fall of the device can be correctly detected, and thus malfunction of the device can be prevented. For example, an unnecessary protection operation for a hard disk drive of the device can be prevented, and thus a user can conveniently use the device.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: June 28, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-nam Cho, Jun-Seok Shim
  • Patent number: 7962305
    Abstract: A master testing control system includes at least one remote computer with one or more communications lines for communicating over a communications network and a plurality of remote sensors, a two way real-time digital video system, a two-way real-time digital audio system. A set of instructions is on each remote computer for sending and receiving data over one or more data lines and for remote display. A set of instructions is on each remote computer for displaying data. At least one local computer is located geographically distant from the remote computer and able to monitor and control the display, storage, and transmission of data acquired by to the remote computer. The remote computer collects data from the plurality of sensors and transmits this data to the local computer, under the control of the local computer, for permanent recording.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: June 14, 2011
    Inventor: Paul Tiegs
  • Patent number: 7953570
    Abstract: A method is disclosed for continuous analysis of the transmission quality in fieldbus networks in automation systems with a plurality of fieldbus participants, which communicate with one another over the fieldbus network. Directly measurable logical and physical bus parameters are recorded from the line signal transmitted over the fieldbus network, and are stored with a predefinable retrospectivity. Operational parameters are derived from the measured bus parameters, these being weighted and the weighted bus parameters being linked together to form the operational parameter. The quantitative weighting of a bus parameter is functionally determined by at least one other bus parameter.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: May 31, 2011
    Assignee: ABB AG
    Inventors: Tilo Merlin, Peter Ude
  • Patent number: 7953568
    Abstract: A method for detecting a cable fault in a cabling of a flow meter is provided according to an embodiment of the invention. The method includes testing one or more first pickoff wires and one or more second pickoff wires of the cabling for pickoff open wire faults. The method further includes testing the first pickoff wires and the second pickoff wires for pickoff connection orientation faults if no pickoff open wire faults are determined in the first pickoff wires and the second pickoff wires. The method further includes testing one or more driver wires of the cabling for driver open wire faults. The method further includes testing the driver wires for a driver connection orientation fault if no driver open wire faults are determined in the driver wires.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: May 31, 2011
    Assignee: Micro Motion, Inc.
    Inventors: Paul J. Hays, Craig B. McAnally
  • Publication number: 20110125448
    Abstract: A three-dimensional application program framework structure; a method for implementing an application program based on the same; and an automatic testing system based on a three-dimensional application software framework and a method therefor. The three-dimensional application program framework structure provides a framework comprising functions and management of the environment of the system and events to be implemented by the user (developer), and the developer can easily expand the graphic user interface (GUI) and an actual modeling function as required, and user model. In addition, by using an automatic test system based on the framework, it is possible to record the function-execution history of the user and to automatically generate a test case, and to thereby test the functioning of the application software through the use of the test case regardless of changes in the source code and the GUI.
    Type: Application
    Filed: March 3, 2009
    Publication date: May 26, 2011
    Inventor: Byung Soo Jung
  • Patent number: 7948482
    Abstract: An apparatus for testing a driving circuit for a display is disclosed. The apparatus includes a selecting circuit, a reference voltage generator and an analog-to-digital converter (ADC). The selecting circuit includes many input terminals and an output terminal. The input terminals are respectively coupled to many output pins of the driving circuit, while the selecting circuit is used for selecting one of the output pins to electrically connect the output terminal of the selecting circuit. The reference voltage generator is coupled to at least one of the output pins for generating a reference voltage. The ADC is coupled to the output terminal of the selecting circuit for outputting a digital value based on a difference between an output voltage outputted from the output terminal of the selecting circuit and the reference voltage produced by the reference voltage generator.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: May 24, 2011
    Assignees: Himax Technologies Limited
    Inventors: Chuan-Che Lee, Jiun-Lang Huang, Jui-Jer Huang
  • Publication number: 20110112788
    Abstract: A hard disk drive system comprises an interface that receives test configuration data, that transmits test result data, and that transmits and receives application data. A system on chip (SOC) includes integrated system test (IST) modules. A memory module communicates with the SOC and includes memory and an IST module. One of the IST modules communicates with the interface and is a master IST module that receives the test configuration data and that configures others of the IST modules for testing a component of the hard disk drive system.
    Type: Application
    Filed: January 14, 2011
    Publication date: May 12, 2011
    Inventors: Saeed Azimi, Son Hong Ho
  • Patent number: 7941295
    Abstract: Provided is a manufacturing apparatus for appropriately managing information about parts of the manufacturing apparatus.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: May 10, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Shimatani, Noriaki Shioyama
  • Patent number: 7937164
    Abstract: Methods and systems to detect abnormal operations in a process of a process plant include collecting on-line process data. The collected on-line process data is generated from a plurality of dependent and independent process variables of the process, such as a coker heater. A plurality of multivariate statistical models of the operation of the process are generated using corresponding sets of the process data. Each model is a measure of the operation of the process when the process is on-line at different times, and at least one model is a measure of the operation of the process when the process is on-line and operating normally. The models are executed to generate outputs corresponding to loading value metrics of a corresponding dependent process variable, and the loading value metrics are utilized to detect abnormal operations of the process.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: May 3, 2011
    Assignee: Fisher-Rosemount Systems, Inc.
    Inventors: Nikola Samardzija, Ahmad A. Hamad
  • Patent number: 7933734
    Abstract: A method is presented and described for testing of at least one electronic control system, in which the control system is connected via a data channel to a test device, at least one environmental model is calculated on the test device and the environmental model interacts with the control system by output of environment model data via the test device to the control system and by receiving control system data from the control system via the data channel. The method according to the invention executes on the test device at least one test model to influence the environment model and/or to calculate the environment model and/or the electronic control system, in which the test model or the test models is or are executed functionally independently of the environment model and, during test operation, synchronously with the environment model.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: April 26, 2011
    Assignee: dSpace digital signal processing and control engineering GmbH
    Inventors: Nicola Bruski, Ralf Grosse Boerger, Holger Krisp, Robert Leinfellner, Eduard Miller, Jobst Richert, Thomas Woelfer
  • Patent number: 7933732
    Abstract: An electronic load device provided for testing an OT (power supply to be tested) and the working bandwidth is regulated and set according to the output impedance of the OT. The electronic load device comprises a CPU, an impedance-bandwidth table, a voltage-current measurement unit, a power stage and a control module. Firstly, a current pulled out from the OT to the power stage is called by the CPU. Thereafter, an output impedance of the OT is measured by the voltage-current measurement unit and analysis by the CPU. Next, a working bandwidth of the electronic load device is regulated and set by the control module according to the output impedance and the impedance-bandwidth table.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: April 26, 2011
    Assignee: Chroma Ate Inc.
    Inventors: Hung-Hsiang Kao, Wen-Chung Chen, Kuo-Cheng Liu, Ming-Ying Tsou
  • Patent number: 7930259
    Abstract: A nondestructive inspection apparatus includes a sensor unit for detecting vibrations transmitted through a test object from a vibration generator and a signal input unit for extracting a target signal from an electric signal outputted from the sensor unit. An amount of characteristics extracting unit is also included for extracting multiple frequency components from the test signal as an amount of characteristics. Further, a decision unit has a competitive learning neural network for determining whether the amount of the characteristics belongs to a category, wherein the competitive learning neural network has been trained by using training samples belong to the category representing an internal state of the test object, wherein distributions of membership degrees of the training samples are set in the decision unit.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: April 19, 2011
    Assignee: Panasonic Electric Works Co., Ltd.
    Inventors: Yoshihito Hashimoto, Hidekazu Himezawa
  • Patent number: 7926012
    Abstract: A method is provided to improve the usability of Design-For-Testability Synthesis (DFTS) tools and to increase the design process productivity. The method comprises receiving a list of testability and design impact analysis functions, to be performed on the circuit, also referred to as a device under test (DUT). The impact analysis leads to the creation of logical transformations, which can be selected by a user with one or more available transformation methods from a list including, but not limited to, boundary scan test logic insertion, scan test logic insertion, memory BIST (built-in-self-test) logic insertion, and logic BIST logic insertion, and scan test data compression insertion logic insertion.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: April 12, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Nitin Parimi, Patrick Gallagher, Brian Foutz, Vivek Chickermane
  • Patent number: 7921381
    Abstract: In one embodiment, a plurality of test data entries are successively displayed via a graphical user interface (GUI), with each of the test data entries including at least a test result identifier and a corresponding test result. For at least one of the test data entries, a user-selectable mechanism is provided via the GUI. When the user-selectable mechanism is selected, statistical data based on multiple executions of a test identified by a particular one of the test data entries is caused to be displayed via the GUI. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: April 5, 2011
    Assignee: Verigy (Singapore) Pte. Ltd.
    Inventors: Kristin Petersen, Carli Connally
  • Publication number: 20110077892
    Abstract: The invention is a turn-key, modular platform, including software and hardware, for testing physical system components such as motors remotely over the Internet. The system allows remote customers to test multiple physical system components under the specific loading conditions of the real-world application. This will provide more detailed and accurate information than what is usually given in the data sheets for system component performance, enabling the user to make a more-reliable decision. With respect to motors, the hardware consists of a torque motor that moves autonomously in xy plane to couple to the individual test motors, through a unique coupling mechanism, and emulate various load profiles on them. Test motors are mounted onto modular fixtures that allow for one-time manual positioning in xyz space.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 31, 2011
    Inventors: Mohammad Reza Emami, Michael-Anthony Tedesco
  • Patent number: 7917327
    Abstract: Two robotic arms roam in separate, non-overlapping areas of a test station, avoiding collisions. A traveling buffer moves along x-tracks between a front position and a back position. In the front position, a first robotic arm loads IC chips from an input tray or stacker into buffer cavities in the traveling buffer. The traveling buffer then moves along the x-tracks to the back position, where a second robotic arm moves chips from the traveling buffer to test boards for testing. After testing, the second robotic arm moves chips to a second traveling buffer, which then moves along tracks to a front position for unloading by the first robotic arm. Two traveling buffers may move on the same tracks in a loop. The buffer cavities in the traveling buffer move on internal tracks to expand and contract spacing and pitch between the front and back positions to match test-board pitch.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: March 29, 2011
    Assignee: Kingston Technology Corp.
    Inventors: Ramon S. Co, Tat Leung Lai, Calvin G. Leong
  • Patent number: 7912666
    Abstract: Disclosed is a system and method for disk drive grouping in a multi-cell disk drive test system. A test platform includes a plurality of cells. Each cell is configured to receive and to provide communication with a disk drive. An automated loader/unloader is coupled to a test computer and is responsive to the test computer. The automated loader/unloader is configured to identify disk drives and to selectively load and unload disk drives into and out of the plurality of cells. Particularly, once the automated loader/unloader has identified a first disk drive, the test computer is configured to: determine a grouping criteria based upon the first disk drive; detect a subsequent disk drive having the same grouping criteria as the first disk drive; and cause the automated loader/unloader to load the subsequent disk drive into one of the plurality of cells.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: March 22, 2011
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mostafa Pakzad, Peter Cheok Him Pang, Mohammad R. Bahadori, Joseph M. Viglione, Roma Leang
  • Patent number: 7912665
    Abstract: A system and method for detecting the absence of contact between the hands of a driver of a vehicle and a steering wheel of the vehicle that have particular application in ensuring the proper functioning of various components of the driver assist steering systems and maintaining driver attentiveness. The method for detecting a no-contact condition between the hands of the driver of the vehicle and the steering wheel includes generating a model of the no-contact condition using a second-order transfer function. The method further includes obtaining a set of model-generated steering dynamics by estimating a plurality of parameters of the second-order transfer function and a set of measured steering dynamics using a plurality of sensors. The set of model-generated steering dynamics and the set of measured steering dynamics are then compared and the no-contact condition is detected based on this comparison.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: March 22, 2011
    Assignee: GM Global Technology Operations LLC
    Inventors: Weiwen Deng, Yong H. Lee, Haicen Zhang