Input/output Access Regulation Patents (Class 710/36)
  • Patent number: 8914559
    Abstract: Peripherals and data processing systems are disclosed which can be configured to interact based upon sensor data. In one embodiment, a peripheral, which is configured to be used with a data processing system, includes an interface to couple the peripheral to the data processing system, and at least one sensor, such as a proximity sensor, to sense a user of the peripheral, and a processor coupled to the interface and to the at least one sensor, wherein the processor configures the peripheral in response to data from the at least one sensor. The peripheral may communicate sensor data from its sensors to the data processing system, which may be a wireless PDA, and the data processing system analyzes the sensor data from its sensors and from the peripheral's sensors to decide how to configure the peripheral and/or the data processing system based on the sensor.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 16, 2014
    Assignee: Apple Inc.
    Inventors: Nicholas Kalayjian, Stanley Rabu, Jeffrey Terlizzi
  • Patent number: 8908378
    Abstract: A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: December 9, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Jin-Ki Kim
  • Patent number: 8902899
    Abstract: A method includes receiving a first packet at an input of a switching device and determining whether to insert first data associated with the first packet into a normal buffer of the input. The determination of whether to insert first data associated with the first packet into the normal buffer includes determining whether the first output identifier matches a second output identifier corresponding to second data in the normal buffer that is associated with a second packet. The first data is inserted into the normal buffer when the first output identifier matches the second output identifier.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Chrysos, Anil Pothireddy, Brian T. Vanderpool
  • Publication number: 20140351460
    Abstract: While software in a relay device is being rewritten by an external diagnosis device, a processing unit of the relay device prohibits transfer processing of data from each ECU connected to CAN bus and allows transfer processing of data, which is transmitted from the external diagnosis device and which indicates at least either one of transmission prohibition of periodic transmission data and storage prohibition of a failure code into each ECU by not receiving the periodic transmission data in each ECU, to the CAN buses.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 27, 2014
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Michitaka Tsuboi, Masanori Matsuura
  • Patent number: 8898347
    Abstract: A repeater device connected to source and sink devices includes: an input terminal receiving transmission data supplied from the source device; relay means for relaying the transmission data; an output terminal outputting the transmission data relayed by the relay means to the sink device; control means for setting an operating mode of a limited state where a dynamic function of causing a superficial dynamic change and allowing a user to visually confirm the superficial dynamic change is deactivated and only a static function of not causing the superficial dynamic change is activated in response to a user's predetermined operation even when the source and sink device are connected to each other in a controllable state; and switch means for switching activated and deactivated states of a connecting line to the sink device by controlling the ON and OFF states.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: November 25, 2014
    Assignee: Sony Corporation
    Inventors: Takashi Sasaki, Satoshi Higuchi, Keisuke Satou
  • Patent number: 8892792
    Abstract: An in-flight system provides a user with an entertainment environment including movies, music, games, internet, map, etc. The in-flight system provides stored media content on one or more servers located throughout an aircraft cabin and each server is associated with a plurality of seats. In a preferred embodiment, the in-flight system provides for a communication port (e.g., USB or mini-USB connector or micro-USB connector) for connection to personal electronic device providing access to the server containing the stored media, access to an internet connection, and power. In one embodiment, the in-flight system provides for a seat display unit (typically located in the seat back of the next forward seat) and associated media module hardware to process the stored media content and drive the display.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: November 18, 2014
    Assignee: Intheairnet, LLC
    Inventors: Howard Isham Royster, Michael J. Rogerson, Benjamin Alexander Medvitz
  • Patent number: 8886853
    Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: November 11, 2014
    Assignee: CommVault Systems, Inc.
    Inventors: Rajiv Kottomtharayil, Manoj Kumar Vijayan
  • Patent number: 8885472
    Abstract: The systems and methods described herein allow for the scaling of output-buffered switches by decoupling the data path from the control path. Some embodiment of the invention include a switch with a memory management unit (MMU), in which the MMU enqueues data packets to an egress queue at a rate that is less than the maximum ingress rate of the switch. Other embodiments include switches that employ pre-enqueue work queues, with an arbiter that selects a data packet for forwarding from one of the pre-enqueue work queues to an egress queue.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: November 11, 2014
    Assignee: Broadcom Corporation
    Inventors: Bruce Kwan, Brad Matthews, Puneet Agarwal
  • Publication number: 20140330993
    Abstract: The present invention includes a driverless data transfer device and method for accessing and downloading item data from an item storage unit associated with an item. The driverless data transfer device includes, inter alia, a data downloading unit configured to download the item data, an interface unit for transferring the downloaded data to an item checking unit via a communications bus, and a decoder configured to decode said stored data to conform to data processing requirements of the item checking unit.
    Type: Application
    Filed: September 23, 2012
    Publication date: November 6, 2014
    Inventor: Shimi Raz
  • Patent number: 8879985
    Abstract: Embodiments of the invention include electronic communications devices having a memory in near field communication device, a memory arbitrator and a host processor. The near field communication (NFC) devices are configured to receive data and drive power from the communication signal. The memory arbitrator is connected to the NFC device and the memory. The memory arbitrator is also configured to access the memory in response to an access request from the NFC device. Additionally, the memory is configurable to be accessed by both the host processor and the NFC device according to embodiments of the present invention.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: November 4, 2014
    Assignee: Broadcom Corporation
    Inventor: Craig Fukuo Ochikubo
  • Patent number: 8880741
    Abstract: A management method is provided, suitable for an electronic system having electronic devices connected in a daisy-chain configuration. The management method comprises the steps of: the electronic devices are sequentially connected with a host, thereby obtaining universal unique identifiers corresponding to the electronic devices; serial numbers corresponding to the electronic devices are generated according to a first order of obtainment of the universal unique identifiers of the electronic devices; and the host communicates with the electronic devices according to the serial numbers.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 4, 2014
    Assignee: Acer Incorporated
    Inventor: Kim Yeung Sip
  • Patent number: 8880702
    Abstract: A method for providing other than a 1:1 resource mapping may include receiving an indication of a selected resource reference element, receiving an indication of at least one resource to be associated with the resource reference element, and generating, via processing circuitry, a registry including a declarative policy defining an association of the selected resource reference element and the at least one resource in which the registry defines an other than 1:1 mapping between resource reference elements and resources.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Manu T. George, Murali K. Surampalli
  • Patent number: 8874805
    Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce G. Mealey, Greg R. Mewhinney, Mysore S. Srinivas, Suresh E. Warrier
  • Patent number: 8874752
    Abstract: A method for providing other than a 1:1 resource mapping may include receiving an indication of a selected resource reference element, receiving an indication of at least one resource to be associated with the resource reference element, and generating, via processing circuitry, a registry including a declarative policy defining an association of the selected resource reference element and the at least one resource in which the registry defines an other than 1:1 mapping between resource reference elements and resources.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Manu T. George, Murali K. Surampalli
  • Patent number: 8874804
    Abstract: High performance computing (HPC) and grid computing processing for seismic and reservoir simulation are performed without impacting or losing processing time in case of failures. A Data Distribution Service (DDS) standard is implemented in High Performance Computing (HPC) and grid computing platforms, to avoid the shortcomings of current Message Passing Interface (MPI) communication between computing modules, and provide quality of service (QoS) for such applications. QoS properties of the processing can be controlled.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: October 28, 2014
    Assignees: Saudi Arabian Oil Company, King Fahd University of Petroleum & Minerals
    Inventors: Raed Abdullah AlShaikh, Sadiq Sait
  • Patent number: 8874807
    Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: October 28, 2014
    Assignee: Oracle International Corporation
    Inventors: Sue K. Lee, Vivekananda C. Kolla, Akshay D. Shah, Sumanta Chatterjee, Margaret Susairaj, Juan R. Loaiza, Alexander Tsukerman, Sridhar Subramaniam
  • Patent number: 8868805
    Abstract: A storage device, which is to be connected with hosts each having host-side communication ports and a multipath driver, includes logical storage units; communication ports; a driver type judging part that stores into a storage, when a prescribed SCSI command that a non-TPGS-compliant multipath driver does not transmit is received from a host by one of the communication ports, information indicating that the TPGS-compliant multipath driver is used in the host; and a command processing part, with respect to a SCSI command received via a communication path that is set as a standby path, judges by referring to the storage whether the TPGS compliant multipath driver is used in a host that transmitted the SCSI command, and, if the TPGS compliant multipath driver is not used in the host, processes the SCSI command assuming that the communication path is not the standby path.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: October 21, 2014
    Assignee: Fujitsu Limited
    Inventors: Atsushi Takakura, Kenji Hattori
  • Patent number: 8862794
    Abstract: The invention may be embodied in a SAS expander with register bits within Phys associated with I/O devices. Setting and unsetting the register bit in the Phy associated with a particular physical or logical device allows I/O traffic to be blocked and unblocked, as desired, to the selected physical or logical devices. In a particular embodiment, when the register bit is set to a blocking state, an OPEN request that comes in on the SAS link is rejected using OPEN_REJECT (RETRY). Phy register bits may be provided for multiple different SAS protocols that can be controlled individually for each attached SAS device. The Phy register bit may also be used to reject only SAS connection requests that attempt to leave a particular SAS link.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 14, 2014
    Assignee: LSI Corporation
    Inventors: Brett J. Henning, Harold L. Johnson, William K. Petty
  • Patent number: 8862963
    Abstract: Disclosed herein is a nonvolatile memory including: a nonvolatile memory cell device including at least a nonvolatile memory cell array accessible in units of a word and further accessible at least with a fixed latency in a first access mode and with a variable latency in a second access mode; a first access path used in the first access mode; a second access path used in the second access mode; a first ECC processing part configured to be connected to the first access path and to perform error detection and correction using an ECC on the data output from the nonvolatile memory cell array in the first access mode; and a second ECC processing part configured to be connected to the second access path and to perform error detection and correction using the ECC on the data output from the nonvolatile memory cell array in the second access mode.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: October 14, 2014
    Assignee: Sony Corporation
    Inventors: Kenichi Nakanishi, Keiichi Tsutsui
  • Patent number: 8856401
    Abstract: An integrated controller is provided for controlling communications with a plurality of peripheral devices. The integrated controller includes a bus interface for processing communications with a processor; a switch for routing communications between the processor and one or more of the peripheral devices; and a plurality of controllers, where each of the controllers provide an interface to at least one peripheral device. The controllers include at least one PHY controller for a corresponding peripheral device that provides an electrical interface to a connection, such as a network connection. The controllers also include at least one MAC controller that stores and forwards packets to and from a network connection.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: October 7, 2014
    Assignee: LSI Corporation
    Inventors: Kameran Azadet, Thomas Truman
  • Patent number: 8855627
    Abstract: A system and method may comprise providing to a device user in response to one of a user request for troubleshooting assistance and a mobile telecommunications user device monitoring software conclusion that a problem exists, a diagnostic application specific to the mobile telecommunication user device of the device user; receiving from the device user an indication of a problem with the mobile telecommunication user device experienced by the device user; selecting an application update; providing to the device user the application update updating an application running on the mobile telecommunication user device; and determining whether the problem has been solved. If determining indicates that the problem has not been solved the method may further include deleting the application and further determining whether the problem has been solved, and if so forwarding problem solution data to a knowledge database.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: October 7, 2014
    Assignee: Future Dial, Inc.
    Inventors: Xinmin Ding, Chen Chen, Steven S. Chan, George C. Huang
  • Patent number: 8856400
    Abstract: Controlling I/O operations with a storage device includes establishing a quota that corresponds to a maximum amount of data to store on the storage device in a given amount of time, determining if processing an I/O operation would cause the quota to be exceeded, and performing the I/O operation if the quota is not exceeded. The quota may be provided in I/O operations per second or as I/O throughput. Controlling I/O operations with a storage device may also include accumulating credit in response to a rate of I/O operations being less than the quota and performing I/O operations when the quota is exceeded in response to the credit being greater than zero. The credit may be decreased if an I/O operation is performed when the quota is exceeded.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 7, 2014
    Assignee: EMC Corporation
    Inventors: James L. Davidson, Chris Bunting, Arieh Don, Patrick Brian Riordan, John F. Madden, Jr.
  • Patent number: 8856408
    Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the circuitry including at least one input for receiving transaction requests; at least one output for outputting transaction requests; at least one path for transmitting the transaction requests between the input and the output. Control circuitry routes received transaction requests from the input to the output in response to a barrier transaction request. An ordering of at least some transaction requests is maintained with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests. The control circuitry includes a response signal generator, the response signal generator is responsive to receipt of the barrier transaction request to issue a response signal.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: October 7, 2014
    Assignee: ARM Limited
    Inventors: Peter Andrew Riocreux, Bruce James Mathewson, Christopher William Laycock, Richard Roy Grisenthwaite
  • Patent number: 8856402
    Abstract: A method and apparatus for multiplexing a plurality of streams transmitted and received via an audio/video (AV) link by allocating to the plurality of streams a plurality of basic units included in a transmission unit, and generating and transmitting an additional plurality of transmission units.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-min Lee, Il-ju Na, Seung-hwan Kim, Seung-kwon Park, Bong-hwan Cho, Harkirat Singh
  • Publication number: 20140297903
    Abstract: Various embodiments initialize a communication link associated with data transfer to a connected state between participants in the communication link. In some cases, the communication link is paired with a first Input/Output (I/O) completion port effective to enable the data transfer. Some embodiments disassociate the communication link with the first I/O completion port and re-initialize the communication link while retaining the connected state. Alternately or additionally, the communication link is paired with at least a second I/O completion port. In some cases, the second I/O completion port utilizes an I/O model that differs from an I/O model associated with the first I/O completion port. Alternately or additionally, the communication link can be reconfigured to follow a IO model that does not utilize an IO completion port at all.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 2, 2014
    Applicant: Microsoft Corporation
    Inventors: Matthew R. Cox, Ivan D. Pashov, Jonathan A. Silvera, Paul Sliwowicz
  • Patent number: 8848532
    Abstract: A data processing method and system and relevant devices are provided to improve the processing efficiency of cores. The method includes: storing received packets in a same stream sequentially; receiving a Get_packet command sent by each core; selecting, according to a preset scheduling rule, packets for being processed by each core among the stored packets; receiving a tag switching command sent by each core, where the tag switching command indicates that the core has finished a current processing stage; and performing tag switching for the packets in First In First Out (FIFO) order, and allocating the packets to a subsequent core according to the Get_packet command sent by the subsequent core after completion of the tag switching, so that the packet processing continues until all processing stages are finished. A data processing system and relevant devices are provided. With the present invention, the processing efficiency of cores may be improved.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: September 30, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Lingyun Zhi, Linhan Li, Fei Song, Zuolin Ning
  • Patent number: 8843677
    Abstract: An embodiment of the invention pertains to a method that includes an operating system, program components running on the operating system, and a file system associated with one or more files. Responsive to a write request sent from a specified program component to the operating system, in order to write specified data content to a given file, the method determines whether the write request meets a criterion, which is derived from the identity of at least one of the specified program component, and the given file. If the criterion is met, a message is immediately sent to release the specified program component from a wait state. Data portions of the specified data content are then selectively written to a storage buffer, and subsequently written from the buffer to the given file.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Logeswaran T. Rajamanickam, Arun Ramakrishnan, Ashrith Shetty, Rohit Shetty
  • Patent number: 8843661
    Abstract: A wireless Universal Serial Bus (USB) host that optimizes the data transfer between the Wireless Host Controller Driver (WHCD) and the Wireless Host Controller (WHC). The data transfer between the WHCD and the WHC is optimized by reducing the overhead of data fragmentation. Higher performance without sacrificing memory and computation power is achieved with the optimization of the data transfer.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventor: Rakesh Avichal Ughreja
  • Patent number: 8843676
    Abstract: An embodiment of the invention pertains to a method that includes an operating system, program components running on the operating system, and a file system associated with one or more files. Responsive to a write request sent from a specified program component to the operating system, in order to write specified data content to a given file, the method determines whether the write request meets a criterion, which is derived from the identity of at least one of the specified program component, and the given file. If the criterion is met, a message is immediately sent to release the specified program component from a wait state. Data portions of the specified data content are then selectively written to a storage buffer, and subsequently written from the buffer to the given file.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Logeswaran T. Rajamanickam, Arun Ramakrishnan, Ashrith Shetty, Rohit Shetty
  • Patent number: 8843673
    Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce G. Mealey, Greg R. Mewhinney, Mysore S. Srinivas, Suresh E. Warrier
  • Patent number: 8843666
    Abstract: A SAS expander or initiator places PHYs in a wide port into a persistent reduced power state by signaling to the connected SAS device that the SAS expander or initiator intends to route data traffic through other PHYs in the wide port. The SAS expander or initiator and connected SAS device agree to disuse certain PHYs so that the PHYs enter a reduced power state according to SAS standards.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: September 23, 2014
    Assignee: LSI Corporation
    Inventors: Brad Besmer, Brian A. Day, Scott Dominguez, Kevin A. Mocklin, David J. Golden
  • Patent number: 8843671
    Abstract: Various embodiments of the invention provide resource management of available data bandwidth of a SAS system in a non-uniform way. In certain embodiments, arbitration wait time values are adaptively modified to achieve a specified performance quota for a link.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: September 23, 2014
    Assignee: PMC-Sierra US Inc.
    Inventors: Gregory Arthur Tabor, Kurt Marshall Schwemmer, John Matthew Adams
  • Patent number: 8843674
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a first buffer, a second buffer, an interface unit and a controller. Data is transferred between the interface unit and the first buffer. The controller controls the first buffer, the second buffer and the interface unit. When receiving a first command and first data at a test time, the controller transfers the first data to the first buffer via the interface unit. When receiving a second command as a dummy command, the controller reads second data from the memory cell array to the second buffer and, at the same time, outputs first data held in the first buffer via the interface unit.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hitoshi Shiga
  • Patent number: 8843672
    Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: September 23, 2014
    Assignee: Fujitsu Limited
    Inventors: Kazuichi Oe, Kazutaka Ogihara, Yasuo Noguchi, Tatsuo Kumano, Masahisa Tamura, Yoshihiro Tsuchiya, Takashi Watanabe, Toshihiro Ozawa
  • Patent number: 8838261
    Abstract: An operating system of a device receives, from an application executing on that device, data that identifies a category of hardware resources that the application needs to use in order to function. That category is mapped to a specified set of hardware resources of the device. The operating system also receives, from the application, data that identifies a mode. The mode corresponds to an intended use of a set of hardware resources and is mapped to a group of hardware resource settings that are consistent with the intended use. The operating system allocates, to the application, a particular set of hardware resources that are mapped to the category. The operating system configures one or more hardware resources in the particular set of hardware resources in conformity with a particular group of settings that are mapped to the mode.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: September 16, 2014
    Assignee: Apple Inc.
    Inventors: William G Stewart, Andrew E Rostaing, Anthony J Guetta, Eric J Johnson, Gregory R Chapman, Deepak Iyer
  • Patent number: 8838850
    Abstract: A cluster of storage control members connect different clients to different storage disks. Connection path information between the different clients and disks is discovered and distributed to the storage cluster members. The connection path information is then used to maintain coherency between tiering media contained in the different storage cluster members. Unique Small Computer System Interface (SCSI) identifiers may be associated with the different connection paths to uniquely identify particular storage disks connected to the clients.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: September 16, 2014
    Assignee: Violin Memory, Inc.
    Inventors: Sivaram Dommeti, Som Sikdar, Erik de la Iglesia
  • Patent number: 8838782
    Abstract: In a network protocol processing system in which variables of each of TCP transmission processing and TCP reception processing depend on each other, asynchronous parallel processing is realized between a transmission processing block and a reception processing block for updated protocol processing. Specifically, the system includes a high priority queue for transferring control data to be processed with high priority, a low priority queue for control data other than the above control data, and priority control means for distributing the control data to two kinds of queues. When a request for session establishment and the session disconnection of a new TCP session is issued from an application during transmission of TCP data, data related with the session establishment and the session disconnection is notified preferentially through the high priority queue, and other control data is transferred through the low priority queue.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: September 16, 2014
    Assignee: NEC Corporation
    Inventors: Masato Yasuda, Kiyohisa Ichino
  • Patent number: 8832334
    Abstract: According to an aspect of the invention, a computer comprises a memory; and a processor operable to manage a plurality of path groups, each of which includes a plurality of logical paths associated with a host computer, wherein each logical path of the plurality of logical paths connects the host computer to a logical volume of one or more logical volumes in one or more storage systems. The processor is operable to manage a priority of each path group of the plurality of path groups, and to use a logical path of a first path group instead of a logical path of a second path group for I/O (input/output) usage between the host computer and the one or more storage systems, representing a migration of I/O usage from the second path group to the first path group, based on at least the priorities of the first and second path groups.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: September 9, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Hideki Okita
  • Patent number: 8832339
    Abstract: Synchronous interfaces on a first device are configured such that a first synchronous interface is set to a slave mode while a second synchronous interface is set to a master mode. A second device with two synchronous interfaces may then be coupled to the first device with the corresponding synchronous interfaces in master mode and slave mode, respectively. A pair of unidirectional synchronous data channels is established, allowing data transfer between the devices. These channels allow for asynchronous-like transmission of data, in that transmission and corresponding receipt of data may take place at irregular intervals.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 9, 2014
    Assignee: Amazon Technologies, Inc.
    Inventor: Richard William Mincher
  • Patent number: 8832327
    Abstract: An embodiment enables an operating system to load multiple device drivers for a single device without interfering in the operations of the device. Multiple device drivers may be needed in order to communicate with the device. In one embodiment, a device, such as disk drive, is configured to present its identification information in multiple forms that are functionally analogous. The disk drive is configured to provide its serial number in different forms that convert to a same identification. For example, the disk drive may provide its serial number using different cases, such as uppercase or lowercase text. The difference in is transparent to software applications, and thus, does not affect the operations of the device. However, the different forms of the serial number are reported to the operating system as different numbers, and thus, enable the operating system to load different device drivers for the same device.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 9, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: James S. Lin
  • Patent number: 8832329
    Abstract: A USB peripheral device comprising a limited function Universal Serial Bus (USB) host controller configured to control HID compliant USB peripheral devices on a downstream facing USB port is disclosed. The port is also capable of dynamically interfacing to any USB compliant peripheral device.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: September 9, 2014
    Assignee: RGB Systems, Inc.
    Inventors: Brian E. Tauscher, Michael Izquierdo
  • Patent number: 8825925
    Abstract: An example method and system process a SuperSpeed packet transferred at a SuperSpeed transfer rate and based on processing the SuperSpeed packet, generate a Universal Serial Bus (USB) 2.0 packet to be transferred at a USB 2.0 transfer rate, the USB 2.0 transfer rate being less than the SuperSpeed transfer rate.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: September 2, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Gaurav Singh, Herve LeTourneur, Hans Van Antwerpen, Cathal G. Phelan
  • Patent number: 8825949
    Abstract: A method for regulating I/O requests in a RAID storage system may comprise: receiving a first request to access a first set of one or more logical block addresses (LBAs) of a RAID volume; receiving a second request to access at least one of the first set of one or more LBAs of the RAID volume; and queuing the second request. A system for regulating I/O requests in a RAID storage system may comprise: means for receiving a first request to access a first set of one or more logical block addresses (LBAs) of a RAID volume; means for receiving a second request to access at least one of the first set of one or more LBAs of the RAID volume; and means for queuing the second request.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: September 2, 2014
    Assignee: LSI Corporation
    Inventor: Kapil Sundrani
  • Patent number: 8819305
    Abstract: In one embodiment, the present invention provides for a layered communication protocol for a serial link, in which a link layer is to receive and forward a message to a protocol layer coupled to the link layer with a minimal amount of buffering and without maintenance of a single resource buffer for adaptive credit pools where all message classes are able to consume credits. By performing a message decode, the link layer is able to steer non-data messages and data messages to separate structures within the protocol layer. Credit accounting for each message type can be handled independently where the link layer is able to return credits immediately for non-data messages. In turn, the protocol layer includes a shared buffer to store all data messages received from the link layer and return credits to the link layer for these messages when the data is removed from the shared buffer. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: August 26, 2014
    Assignee: Intel Corporation
    Inventors: Daren J. Schmidt, Bryan R. White
  • Patent number: 8819302
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of intermediate signals in response to a plurality of input/output requests. The second circuit may be configured to generate a plurality of processed input/output requests in response to the plurality of input/output requests. The processed input/output requests may be configured to be processed by a drive controller to access a drive array in accordance with a protocol used to process the input/output requests.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: August 26, 2014
    Assignee: LSI Corporation
    Inventors: Madhukar Gunjan Chakhaiyar, Mahmoud K. Jibbe
  • Patent number: 8819364
    Abstract: An acquisition unit of an information processing apparatus acquires access information indicating the state of access to a volume of a disk device at least for data read. A determination unit detects a volume in which a sequential read was performed, on the basis of the acquired access information, and determines the volume as a backup source for a backup.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: August 26, 2014
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Watanabe, Hideaki Takahashi, Takashi Hirose, Kinya Saito, Reisuke Nakagawa
  • Patent number: 8811893
    Abstract: Embodiments of the invention include electronic communications devices having a memory in near field communication device, a memory arbitrator and a host processor. The near field communication (NFC) devices are configured to receive data and drive power from the communication signal. The memory arbitrator is connected to the NFC device and the memory. The memory arbitrator is also configured to access the memory in response to an access request from the NFC device. Additionally, the memory is configurable to be accessed by both the host processor and the NFC device according to embodiments of the present invention.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: August 19, 2014
    Assignee: Broadcom Corporation
    Inventor: Craig Fukuo Ochikubo
  • Patent number: 8812756
    Abstract: A method of dispatching and transmitting data stream, which is used for a memory storage apparatus having a non-volatile memory module and a smart card chip, is provided. The method includes configuring a plurality of logical block addresses, and a plurality of specific logical block addresses are used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory. The method also includes, when a logical block address corresponding to a read command from a host system belongs to one of the specific logical block addresses and the buffer memory stores a response data unit, transmitting the response data unit stored in the buffer memory to the host system. Accordingly, the method can make the host system to correctly receive the response data unit from the smart card chip.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: August 19, 2014
    Assignee: Phison Electronics Corp.
    Inventor: Ching-Wen Chang
  • Patent number: 8812753
    Abstract: An information processing apparatus includes a transceiver unit transmitting and receiving information to and from an external device is provided. The apparatus includes a setting information storage unit storing setting information related to an operating environment in association with user identification information, a judging unit judging whether the information that the transceiver unit transmits to or receives from the external device includes given information, an extraction unit extracting the given information from the information including the given information, a specifying unit specifying a user on the basis of the given information, and a setting unit reading the setting information stored in the setting information storage unit in association with the user identification information and setting the user operating environment on the basis of the setting information.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventors: Motoshi Sumioka, Masahiko Murakami, Ryuichi Matsukura
  • Patent number: RE45097
    Abstract: An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: August 26, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Sundar Iyer, Nick McKeown