Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.

Abstract: A device includes a task context controller, at least one transport engine connected to the task context controller, and at least one comparator connected to the transport engine. The comparator to compare a data offset from a receive frame with a current data offset and a result is used to determine frame processing order.

Abstract: A semiconductor device includes at least one endpoint communicating with a host, and an endpoint controller dividing each of the at least one endpoint into a majority of sub-endpoints and performing numbering to each of the divided sub-endpoints. The endpoint controller transmits a packet generated by the host to any one of the sub-endpoints.

Abstract: In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller. A method for block striping data to or from a plurality of read or write channels.

Abstract: Apparatus, methods, and systems provide for remote management of a set of local computers by transferring screen frames produced by the local computer for viewing at a remote computer. A redirection module captures and transmits video signals from a local computer through over a network, such as the Internet, to a remote computer where the remote computer produces a display that contains the screen frames being transferred. The module is configured for use with and installation within a keyboard, video, and mouse switch configured for receiving the module. The redirection module is further configured for use with and installation on a server-blade to allow remote management of the server-blade.

Abstract: At least one input/output (I/O) firmware partition is provided in a partitioned environment to facilitate access to I/O resources owned by the at least one I/O firmware partition. The I/O resources of an I/O firmware partition are shared by one or more other partitions of the environment, referred to as consumer partitions. The consumer partitions use the I/O firmware partition to access the I/O resources. Since the I/O firmware partitions are responsible for providing access to the I/O resources owned by those partitions, the consumer partitions are relieved of this task, reducing complexity and costs in the consumer partitions.

Abstract: A peripheral device of a host computer includes a microcontroller and two virtual devices. The first virtual device passes, to the microcontroller, commands of a first command set from any user of the host computer and preferably also commands of a second command set from only privileged users of the host computer. The second virtual device passes, to the microcontroller, commands of the second set from any user of the host computer. In one physical implementation of the invention, the two virtual devices are implemented as separate physical devices, and the second device is connected to an interface to the host computer only if the user is not privileged. In another physical implementation of the invention, the two virtual devices are implemented in a common physical device, and a sector of a memory of the peripheral device is reserved for handling commands of the second set from non-privileged users.

Abstract: A connection device restriction program for preventing use of uncalled-for connection devices. A permission list setting unit sets a connection permission list holding information defining connection devices whose connection is to be permitted, and a list memory stores the connection permission list. When a connection device is connected to one of first to third connection ports, a connection restriction unit acquires device information from the connection device, and collates the device information with the connection permission list to determine whether or not the connection device corresponds to any one of the connection-permitted devices. If the connection device corresponds to any one of the connection-permitted devices, connection of the device is permitted; if not, connection of the device is forbidden.

Abstract: A system and method for control management of shared peripheral circuits by a plurality of controllers is provided. Control of the peripherals is mediated through a shared signal controller which uses mask registers to ensure that only one controller may control a peripheral at any one time, and that the type of peripheral is matched to the type of controller.

Abstract: The present invention introduces the notions of a rendezvous component and rendezvous functionality into the communications network environment. Using the invention, an application can express information regarding when an operation requested of a device should complete and at which location, and it enables the device to perform its operations respecting this information while also improving the device's overall behavior. In an embodiment, one or more data objects are distributed across one or more collections of storage devices using a dispersal technique. When access to a data object is desired, a rendezvous component issues a set of constituent requests to the collections of storage devices. These requests typically include location and timing rendezvous parameters specifying a destination location where and a given time when a given data object is to be reconstituted.

Abstract: A computer program product and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access address referenced by an incoming I/O transaction that was initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. A single physical I/O adapter validates that one or more direct memory access addresses referenced by an incoming I/O transaction initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation.

Abstract: One embodiment provides a system which uses a temporal ordering policy for allocation of limited processor resources. The system starts by executing instructions for a program during a normal-execution mode. Upon encountering a condition which causes the processor to enter a speculative-execution mode, the processor performs a checkpoint and commences execution of instructions in the speculative-execution mode. Upon encountering an instruction which requires the allocation of an instance of a limited processor resource during the execution of instructions in the speculative-execution mode, the processor checks a speculative-use indicator associated with each instance of the limited processor resource. Upon finding the speculative-use indicators asserted for all instances of the limited processor resource which are available to be allocated for the instruction, the processor aborts the instruction.

Abstract: A method for handling input/output (I/O) commands in a storage system includes establishing first and second counters for counting unfinished I/O commands, and establishing a reference which is initially set to the first counter. The reference is periodically switched between the first counter and the second counter, and the switching interval is less than the I/O timeout value. Upon placing an I/O command into an I/O command queue, a copy of the current reference is made into an I/O specific control block and the current referenced counter is incremented. Upon finishing of an I/O command, the counter referenced by the I/O specific control block is decremented and the I/O command is removed from the I/O command queue. When switching the reference, a problem is detected in the event that the counter being switched to is above a predetermined threshold. Upon detection of a problem, a more explicit I/O check is conducted.

Abstract: A method of improving USB device virtualization to prevent bus bandwidth from being over allocated when isochronous USB devices are attached to multiple virtual machines by attaching a dummy device to each virtual machine which will mimic the bandwidth reservations made by real devices in other virtual machines, thus allowing each virtual machine to determine the true available bandwidth. The dummy devices are represented by incorporating a dummy device driver in each virtual machine and emulating the dummy device in software in the VMM.

Abstract: A method for switching KVM switch ports comprising a plurality of computer ports and a related device are provided. A behavior of a mouse coupled to the KVM switch is detected. The behavior comprises multiple click on a specific button of the mouse. In response to the behavior, the computer ports are switched accordingly.

Abstract: A communicating system suitable for a repeater and communicating method thereof are described. The communicating system comprises a receiving unit, a delay module, a transmitting unit and a control unit. The receiving unit transmits a first signal based on a KB/MS input signal. The delay module is coupled to the receiving unit and delays the first signal from the receiving unit in order to generate a second signal. The second signal has a first phase difference in comparison with the first signal. The transmitting unit is coupled to the delay module and the control unit. The transmitting unit transmits a KB/MS output signal based on the second signal while the control unit controls the transmitting unit via a control signal.

Abstract: A processing device includes a processor which executes first and second pieces of control software in a memory to perform processing, and a device 1 having a plurality of SLOTs 1 to 8 to electrically connect the processor to a plurality of device. The device 1 switches a SLOT which connects devices 2 and 3 between a SLOT 1 or 2 and a spare SLOT 8 allocated in advance through a switch. The processor executes the first and second pieces of control software to manage SLOT information including pieces of path information obtained through the SLOTs 1, 2, and 8 between the devices 1 and 2 such that the SLOT information can be registered and updated. When a failure occurs in the SLOT 1 or 2, the processor updates the path information obtained through the SLOT 1 into the path information obtained through the spare SLOT, and the SLOT which connects the devices 2 and 3 is switched from the SLOT 1 or 2 to the spare SLOT 8.

Abstract: A device for preventing a process collision based on plural of input signals includes an input block for receiving a first and a second input signals to thereby generates a first and a second process request signals, a collision controller for controlling the process collision in accordance with a predetermined priority, and a signal processing block for outputting a first process signal in response to the first process request signal and outputting a second process signal in response to the second process request signals. Herein, the process collision is caused one of cases when the second input signal is inputted at an activation sector of the first process signal of the first input signal, when the first input signal is inputted at an activation sector of the second process signal of the second input signal, and when the first and the second inputs are inputted concurrently.

Abstract: A bi-directional and full duplex facility for permitting both the IO processor and the Channel to write CCA messages on their respective queues at the same time. IOP messages to the channel are stored on the TO_CHN queue and Channel messages to the IOP on the TO_IOP queue. CCA Queues replace hardware CCAs due to increasing transmission capabilities of current IO processors and Channel processors. Even though the mechanism is similar, the present invention provides some benefits in the use of signaling. The IOP does not have to signal the Channel each time it puts something on its outbound queue. Each queue contains multiple slots. This allows the IOP and Channel to write multiple messages on the targeted queue without encountering a CCA busy signal. The actual queues are now structured in hardware system memory.

Abstract: An information processing apparatus according to an embodiment of the present invention includes: a CPU; a plurality of peripheral devices connected to the CPU through a bus; and a peripheral access protection setting unit storing access protection information representing whether an access to each of the peripheral devices is permitted or inhibited in accordance with a task to be performed by the CPU, wherein an access by the CPU to the peripheral devices is limited based on the access protection information and address information of the peripheral device.

Abstract: An apparatus and method of speculatively decoding non-memory read commands. A command register and decoder, within the apparatus, compares high-order command bits provided on a serial bus with corresponding bits of recognized non-memory read commands. An early non-memory read command is asserted when incoming command bits match a non-memory read command. Early responsive data is prepared speculatively during the time the remainder of command bits is received and decoded. A determination of command speculation correctness is made after receipt of the full command. If the full command received is not the speculated non-memory read command, the prepared data is discarded. Earlier prepared data is produced as the subsystem response if the full command matches the speculative non-memory read command. For incoming commands with operands, such as an address, the same speculative determination based on high-order operand bits is performed.

Abstract: An information processing apparatus is connected to a recording or playback apparatus having a file system. The information processing apparatus includes a receiver for receiving a command provided by an operating system in response to a file operating request from an application, and a converter for converting the command provided by the operating system into a request which is to be converted into a command based on a communication protocol capable of handling the file system in communication with said recording or playback apparatus.

Abstract: This storage apparatus includes multiple controllers, a transfer path, and multiple processors. Each of the multiple controllers is connected to the same or a different processor. A first processor connected to a controller that received a transfer command from the host system determines, based on the transfer command, a first controller to become a transfer source of data and a second controller to become a transfer destination of the data, and determines a path belonging to the transfer path between the first controller and second controller. If there are multiple paths, a path in which the number of controllers connected other than to the second controller becomes maximum as a specific path, and the multiple processors transfer data between the first controller and the second controller along with the specific path.

Abstract: A data storage system includes a data management system that transfers data between a host system and multiple storage devices through multiple channels. The data addressing is distributed amongst channels to improve system performance and durability. In one embodiment, each channel has an address translation table or address map which is utilized to gain performance improvement during data transfer or erasure, and an increase of the device's useful life span.

Abstract: A Universal Serial Bus (USB) flash drive comprising a controller including a USB interface and a nonvolatile computer readable medium interface. The USB flash drive may also comprise a nonvolatile computer readable medium in communication with the nonvolatile computer readable medium interface and storing data and a USB connector in communication with the USB interface. The USB flash drive may also comprise a transmitter for transmitting at least a portion of data from the nonvolatile computer readable medium to an external device external to the USB flash drive. The transmitter may be substantially simultaneously operable with the USB connector, may send a modulated data signal, and/or may send the at least portion data in a compressed format.

Abstract: Protecting computer systems from attacks that attempt to change USB topology and for ensuring that the system's information regarding USB topology is accurate is disclosed. A software model is defined that, together with secure USB hardware, provides an ability to define policies using which USB traffic can be properly monitored and controlled. The implemented policy provides control over USB commands through a combination of software evaluation and hardware programming. Legitimate commands are evaluated and “allowed” to be sent to a USB device by a host controller. Illegitimate commands are evaluated and blocked. Additionally, the USB topology is audited to verify that the system's topology map matches the actual USB topology.

Abstract: A memory device containing data to be protected is integrated with a microprocessor and includes a first and a second memory portion with different accessibilities. The integration of the memory device on the same integrated circuit (IC) or chip as the microprocessor permits a combination of protective hardware and software measures that are not possible with a memory device that is on a different IC than the microprocessor. The first memory portion holds an initialization program that also serves as a boot program during decryption, and the second memory portion holds a user program, for example, a program for decrypting and/or decoding received data. Such data may be, for example, audio data encoded according to the MP3 standard and encrypted with a secret or public password against unauthorized reception.

Abstract: Method, device and computer program product for determining a characteristic of an identifiable component. The method includes: receiving identification information representative of an identity of components that belong to a group of components, determining at least one characteristic of an identifiable component in response to the received identification information, and performing at least one characteristic responsive operation. The device includes an identifiable component and a component characteristic determiner. The component characteristic determiner is adapted to receive identification information representative of an identity of components that belong to a group of components and to determine at least one characteristic of the identifiable component in response to a relationship between the received identification information and reference identification information. The device is adapted to perform at least one characteristic responsive information.

Abstract: The present invention is directed to an apparatus capable of dual porting a serial advanced technology attachment (SATA) disk drive in a fault tolerant communication system, such as fiber channel. The dual porting apparatus includes two idle regenerators coupled to two serial master devices, a synchronization logic capable of synchronizing the communications between one of the idle regenerators and a third idle regenerator coupled to the SATA disk drive. Furthermore the dual porting apparatus may include an auto detector capable of enabling either of the first two idle regenerators, thus effectively switching between the two.

Abstract: A method for controlling the sequence of a plurality of functions which are executable on at least two interacting devices is provided, first of the functions being implemented on a first device and the second of the functions being implemented on a second device. A system for implementing the method is provided, including an administrative unit which controls a sequence of the functions in such a manner that it prevents a first function and a second function which interfere with one another from simultaneously running.

Abstract: Methods, systems, and computer program products for transmitting first-priority data and second-priority data. The first-priority data and second-priority data are stored in separate data buffers, and the first-priority data is transmitted preferentially over the second-priority data.

Abstract: A programmable controller includes a CPU unit, a communication unit and peripheral units connected together through an internal bus. The communication unit has a bus master function, including a cache memory for recording IO data stored in the memory of an input-output unit. When a message is received, it is judged whether the IO data stored in the memory of the input-output unit specified by this message is updated or not. If the data are not updated, a response is created based on the IO data stored in the IO data stored in the cache memory. If the data are updated, the input-output unit is accessed and updated IO data are obtained and a response is created based on the obtained IO data.

Abstract: A system for managing data in multiple data processing devices using common data paths. Embodiments of the invention comprise a first data processing system comprising a cacheable coherent memory space; and a second data processing system communicatively coupled to the first data processing system with the second data processing system comprising at least one bridge, wherein the bridge is operable to perform an uncacheable remote access to the cacheable coherent memory space of the first data processing system. In some embodiments, the access performed by the bridge comprises a data write to the memory of the first data processing system for incorporation into the cacheable coherent memory space of the first data system. In other embodiments, the access performed by the bridge comprises a data read from the cacheable coherent memory space of the first data system.

Abstract: Host computing systems with the ability to efficiently identify the Infiniband™ (IB) addressing parameters corresponding to Fiber Channel I/O devices that are accessible through IB-to-Fiber Channel adapters. An efficient apparatus and program product is described to store the IB addressing parameters pertaining to individual Fiber Channel I/O devices on a subnet administration database, and an efficient mechanism to recover from the database, the IB addressing parameters corresponding to all physical paths by which a desired Fiber Channel I/O device is accessible.

Abstract: A detection circuit indicates when a source device is coupled to a sink. An interface circuit separately interfaces with the plurality of source devices and permits display identification data associated with an interfaced source device to be sent from the memory unit to the interfaced source device. A monitoring unit monitors communications between the plurality of source devices and a memory unit and generates a signal for the plurality of source devices upon identifying that the memory unit is available for storing display identification data that is associated with a remaining source device of the plurality of source devices. The signal is communicated to the control unit to cause the control unit to update the memory unit with the display identification data that is associated with the remaining source device(s). A power detection circuit powers the sink via power from a source device(s) in a low-power mode.

Abstract: A method and a system of access control between a main processor and peripherals connected by a communication bus, including assigning, to all or part of the programs to be executed by the main processor, at least one token selectively authorizing access to one or several of said peripherals, said token being provided at least initially by an auxiliary processor exploiting a memory distinct from that of the main processor; and checking, for each request of access of one of said programs to one of said peripherals, the presence of said authorization token for the access to the concerned peripheral.

Abstract: Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.

Abstract: A memory device may comprise a nonvolatile computer readable medium, a near field communication wireless transmitter, a nonvolatile near field communication tag memory, a data input device and a controller. The nonvolatile computer readable medium is adapted to store data in a data block format. The near field communication wireless transmitter is adapted to wireless transmit data to an external near field communication receiver. The nonvolatile near field communication tag memory is adapted to store data in a tag memory format.

Abstract: An audio system sets a signal line path between the medium of an audio device and an external device and uploads a digital audio file from the external device to the audio device according to a user's manipulation of the audio. In addition, a communication system selectively uses USB and UART communications by commonly using a single USB connector and connects a connector of an external device and an audio/USB/UART common connector through a single cable, so that audio/USB or audio/UART signals are selectively outputted through a common audio signal line. Accordingly, the audio system can interface with various kinds of external devices without external modification or additional installation of a dedicated interface in the audio device with a USB connector. In addition, the USB/UART common communication system can commonly use the USB connector without regard to USB and UART connection signals and can selectively output the audio/USB or audio/UART signals through the single cable in the audio device.

Abstract: A method and apparatus is presented allowing multiple data pointers or addresses to be transferred without acknowledgment to Memory Controller (506) and Memory Controller (510) of Data Controller (500). Data is then transferred in response to the data pointers from BUFFER (512) and Buffer (514) and may be stalled during the transfer in favor of a second data transfer. Once the second data transfer finishes, the first data transfer may be completed.

Abstract: An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.

Abstract: A data transfer control device includes a PATA I/F connected to a PATA bus, an SATA I/F connected to an SATA bus, and a sequence controller that controls a transfer sequence. The PATA I/F includes a task file register (TFR). The sequence controller suspends transmission of a register FIS corresponding to an ATA packet command issued by a host to a device, and performs a dummy setting that causes the host to issue an ATAPI packet command using the TFR. The sequence controller transmits the register FIS corresponding to the ATA packet command to the device after the host has issued the ATAPI packet command.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

Abstract: The disclosure relates to a trusted interface unit and a method of making and using the same. According to one embodiment of the present invention, a method of transmitting data on a network may include receiving data from a partition within a node on the network. This node may be configured to transmit data associated with a number of sensitivity levels. According to one embodiment of the invention, these sensitivity levels may be classification levels. One method of transmission of data may include determining the identity of the partition that originated the data within the node. Furthermore, a label may be added to the data received from within the node and the data may be encrypted with a key that may be uniquely associated with the label on the data. After encryption, the data may be transmitted on the network. Additional methods including the reception of data are disclosed. Various node and network architectures are disclosed implementing the methods and apparatus of the present invention.

Abstract: An input/output control apparatus includes: a request acceptance unit configured to accept a switch request for requesting to change an operating system occupying any one of the input device and the output device; a control information generator unit configured to generate control information including any one of input destination information and output enable information in response to the switch request; and a control information output unit configured to output any one of the input destination information and the output enable information. The input destination information includes at least information for specifying an input destination operating system to which information inputted from the input device is inputted; and the output enable information includes at least information for specifying whether or not each of the plurality of operating systems can output information to the output device.

Abstract: An interposer module may be used between a unified architecture blade compute module and a mid-plane of a present technology blade compute module system. The interposer module may contain input-output controllers for desired input-output fabrics. The mid-plane couples these input-output controllers to associated input-output fabric switches. The same unified architecture blade compute module may also be used without the interposer module in a new technology blade compute module system having multi-context fabric input-output controllers. The multi-context fabric input-output controllers may be coupled to the unified architecture blade compute modules of the information handling system by a switch such as a PCI Express (PCIe) switch.

Abstract: The invention relates to a method and a device for controlling access to multiple applications which are each implemented as a client application in an operating system environment of a data processing device from a shared memory system. The problem addressed by the invention is that of providing an improved method and an improved device for controlling access to multiple applications which are each implemented as a client application in an operating system environment of a data processing device from a shared memory system, which allow an efficient exchange of data for input/output. In particular, interaction with multimedia data in such an operating environment should be optimized.

Abstract: A memory buffer for an FB-DIMM having a first input/output interface for communicating with a memory controller at a first payload data rate and a second input/output interface for communicating with memory packages at a second payload data rate, wherein a relation of the first payload data rate to the second payload data is greater than 10.

Abstract: A storage apparatus is provided that is capable of reducing data maintenance management costs with a performance that is both highly reliable and fast. The present invention is storage apparatus where an intermediary device is arranged between a controller and a plurality of disk devices of different performances arranged in a hierarchical manner. The controller unit carries out I/O accesses to and from the disk devices via the intermediary devices based on access requests sent from host apparatus. The intermediary device includes a power saving control function for the disk device and carries out operation control such as spin off and spin up of disk devices in accordance with conditions set in advance.

Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.