Abstract: Memory management in a data processing system (10) is achieved by using one or more timing bits (54) to specify a timing parameter of a memory (18, 19, 34). To implement this in some embodiments of the present invention, a memory array (32, 33, 42) is multiple-mapped in the physical memory map (70) of processor (12) and the address bits (54) associated with the multiple-mapping are used to directly control timing parameters of the memory arrays (32, 33, 42). This allows for flexible timing specifications to be derived quickly on an access by access basis without requiring any additional control storage overhead.
Abstract: A move engine and operating system transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. The operating system stores FROM and TO real addresses in unique fields in memory that are used to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space. During the process of moving the memory contents, the operating system stalls.
Type:
Grant
Filed:
October 10, 2002
Date of Patent:
July 19, 2005
Assignee:
International Business Machines Corporation
Inventors:
Ravi Kumar Arimilli, John Steven Dodson, Sanjeev Ghai, Kenneth Lee Wright
Abstract: One of the primary difficulties that result from using static variables in multi-threaded computer programs is that changes to a static variable made by one thread will be seen by all other threads operating within the same process. Multiple threads cannot use static variables separately because other threads within the process can overwrite the values stored at the variable memory location. Thus, the development of multi-threaded programs using static variables often requires explicit thread harmonization by the programmer. Another problem is that threads within the same process must use unique static variable IDs to avoid reading or writing to the location of another static variable. This also requires thread harmonization by the programmer. Accordingly, in view of the shortcomings associated with existing thread-static data implementations, there remains a need for an efficient thread-static data implementation that can be used on most modern operating systems.
Type:
Grant
Filed:
October 17, 2002
Date of Patent:
July 5, 2005
Assignee:
International Business Machines Corporation
Abstract: The invention relates to a control means for controlling burst accesses to a synchronous dynamic semiconductor memory device comprising at least two memory banks. In order to avoid relatively large time losses due to preparation cycles (precharge and activate), the invention provides an address converter unit (12) for converting a logical access address into physical access addresses by splitting the burst access into at least two partial burst accesses, wherein a first physical access address addresses a first memory area of a first memory bank for a first partial burst access and wherein a second physical access address addresses a second memory area of a second memory bank for a second partial burst access.
Abstract: A processor contains a move engine and a memory controller contains a mapping engine that, together, transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores current and new real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the current and new real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory modules. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space.
Type:
Grant
Filed:
October 10, 2002
Date of Patent:
June 14, 2005
Assignee:
International Business Machines Corporation
Inventors:
Ravi Kumar Arimilli, John Steven Dodson, Sanjeev Ghai, Kenneth Lee Wright
Abstract: A processor contains a move engine and mapping engine that transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores FROM and TO real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space.
Type:
Grant
Filed:
October 10, 2002
Date of Patent:
June 7, 2005
Assignee:
International Business Machines Corporation
Inventors:
Ravi Kumar Arimilli, John Steven Dodson, Sanjeev Ghai, Kenneth Lee Wright
Abstract: A method and an apparatus for sharing a request queue between two or more destinations. The method and apparatus utilizes a common data table and a common age queue. The age queue is used to select the oldest request. The corresponding request from the common data table is then extracted and sent to the appropriate destination.
Type:
Grant
Filed:
October 18, 2001
Date of Patent:
May 17, 2005
Assignee:
International Business Machines Corporation
Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem A for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the I/O subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.
Abstract: A method and apparatus for input/output virtual address translation and validation assigns a range of memory to a device driver for its exclusive use. The device driver invokes system functionality for receiving a logical address and outputting a physical address having a length greater than the logical address. Another feature of the invention is a computer system providing input/output virtual address translation and validation for at least one peripheral device. In one embodiment, the computer system includes a scatter-gather table, an input/output virtual address cache memory associated with at least one peripheral device, and at least one device driver. In a further embodiment, the input/output virtual address cache memory includes an address validation cache and an address translation cache.
Abstract: A single integrated circuit microcontroller 10 including embedded erasable/programmable non-volatile memory 12 having a read protection. Microcontroller 10 can operate within a special mode in which external circuits may access memory 12 by use of input/output pins 18. When microcontroller 10 activates this special mode, a read protection flag 13 within memory 12 is checked. The read protection flag 13 may be set during production of the microcontroller 10 after instructional data or firmware has been installed onto memory 12. If the read protection flag 13 has been set, the contents of memory 12 are erased or reprogrammed prior to allowing access to memory 12. In this manner, external circuits cannot access instructional data or firmware that is stored in memory 12.
Abstract: The present invention relates to disk drive having a cache control system that generates scan results that permit response to a host command using existing cached data having a logical block address (LBA) range that overlaps a host command LBA range. The cache control system forms variable length segments of memory clusters in a cache memory for caching disk data in contiguous LBA ranges. The cached LBA ranges are scanned for segments having LBA ranges overlapping with an LBA range of a host command. The cache control system is effective in exploiting any existing overlapping cache data.
Type:
Grant
Filed:
July 25, 2003
Date of Patent:
April 12, 2005
Assignee:
Western Digital Technologies, Inc.
Inventors:
Ralph H. Castro, Virgil V. Wilkins, Tsun Y. Ng
Abstract: A computer has a hardware memory arranged into portions that are separately addressable using first identifiers, which are represented using a first number of address bits. A subsystem that is able to address a second space of the hardware memory using second identifiers initiates I/O requests directed to a device that is able to address a different, first memory space using first identifiers, which are represented using a second number of address bits. The second identifiers are initially mapped into the second memory space, but for any I/O request that meets a remapping criterion, the corresponding second identifier is remapped to one of the first identifiers that identifies a portion of the memory in the first memory space. The second space is different from the first space and the second number of address bits is greater less than the first number of address bits.
Type:
Grant
Filed:
April 19, 2004
Date of Patent:
April 12, 2005
Assignee:
VMware, Inc.
Inventors:
Carl A. Waldspurger, Michael Nelson, Kinshuk Govil
Abstract: To provide a system for monitoring data transmitted between parts of an electronic machine. The system includes a mirror memory circuit that is subjected to writing and reading of data in the same manner as a memory circuit based on first data to be supplied from a memory controller to a memory circuit, and a signal sampling circuit that stores in a sampling memory circuit the first data as well as second data read out of the mirror memory circuit. The sampling memory circuit stores exact copies of the first data supplied from the memory controller to the memory circuit and exact copies of the second data supplied from the memory circuit to the memory controller. Therefore, it is possible to monitor the data transmitted between the memory controller and the memory circuit.
Abstract: A method for detecting and correcting cross-linked files while accessing data on a storage media. Each file includes control file information that defines a plurality of blocks on storage media allocated to the file. When a program identifies a volume of storage media that may include cross-linked files, the program intercepts requests to access a file on the storage device. The program then reads the control information for the file and identifies the blocks allocated to the file. The program compares the allocation to a free space map, identifying allocated and unallocated blocks on the storage media, and corrects any inconsistency between the free space map and the control information. The program also maintains a secondary map, which identifies the blocks on the storage media allocated to the files that have been previously been examined.
Abstract: An operating unit operates candidate operation data Da, Db. The candidate operation data Da, Db are contained in two source memories, respectively, or alternatively in one of the two source memories. An address-generating unit generates an address signal Aa and read enable signals RE1a, RE2a in connection with the candidate operation data Da. The address-generating unit further generates an address signal Ab and read enable signals RE1b, RE2b in connection with the candidate operation data Db. Thus, data output from the source memory is controlled with each data to be operated, not with each of the source memory. As a result, data transfer-caused loads can be suppressed. This feature provides a processor having enhanced performance, and further reduces electric power that the processor consumes.
Type:
Grant
Filed:
December 11, 2002
Date of Patent:
March 22, 2005
Assignee:
Matsushita Electric Industrial Co., Ltd.
Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem A for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.
Abstract: An apparatus for a compact disk with an independent audio functionality is disclosed. The apparatus includes a logic core, an IDE controller, and a pass-through module, which are coupled to a micro-controller core. The logic core receives and sends signals to and from a system interface in response to the micro-controller core. The logic core disables sending signals to the system interface in response to the micro-controller core. The IDE controller core receives and sends signals to and from a CD drive interface in response to the micro-controller core. The IDE controller core also disables sending signals to the CD drive interface in response to the micro-controller core. The pass-through module is coupled to the system interface and to the CD drive interface. The pass-through module passes signals between the system interface and the CD drive interface when the computer is in power on mode.
Abstract: The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.
Type:
Grant
Filed:
July 18, 2001
Date of Patent:
March 1, 2005
Assignee:
Infineon Technologies AG
Inventors:
Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lüpke, Jochen Müller, Peter Pöchmüller, Michael Schittenhelm
Abstract: The present disclosure relates to a write-once storage device. In one arrangement, the storage device comprises write-once memory adapted to store data files, re-writable memory that contains a file access table, and a device controller that is configured to control operation of the storage device. In use, the storage device can be used to receive data to be stored from a host device, store the data within write-once memory of the storage device, and update a file access table stored in re-writable memory of the storage device so as to emulate a re-writable storage card.
Type:
Grant
Filed:
June 28, 2002
Date of Patent:
February 15, 2005
Assignee:
Hewlett-Packard Development Company, L.P.
Abstract: Storage virtualization systems and methods that allow customers to manage storage as a utility rather than as islands of storage which are independent of each other. A demand mapped virtual disk image of up to an arbitrarily large size is presented to a host system. The virtualization system allocates physical storage from a storage pool dynamically in response to host I/O requests, e.g., SCSI I/O requests, allowing for the amortization of storage resources through a disk subsystem while maintaining coherency amongst I/O RAID traffic. In one embodiment, the virtualization functionality is implemented in a controller device, such as a controller card residing in a switch device or other network device, coupled to a storage system on a storage area network (SAN). The resulting virtual disk image that is observed by the host computer is larger than the amount of physical storage actually consumed.
Abstract: The present invention relates to a memory system, or more particularly to a conflict-free memory system, which can reduce access time to the memory system by supporting simultaneous access to pq units of various data elements of types of 4 directional blocks (pq) and eight directional lines of a constant interval at a location of data within M×N array in a SIMD processor having pq units of PE's (Processing Elements). Accordingly, the present invention is an improvement over the previous memory systems, from the perspective of restriction of subarrary types, constant intervals, and the size of a data array, hardware cost, speed and complexity. Further, it provides a method of address calculation and data routing using said improved conflict-free memory system.
Abstract: A communications system includes physical layer hardware and a processing unit. The physical layer hardware is adapted to communicate data over a communications channel in accordance with a plurality of control codes. The physical layer hardware is adapted to demodulate an incoming analog signal to generate a digital receive signal and modulate a digital transmit signal to generate an analog transmit signal. The processing unit is adapted to execute a privileged driver for interfacing with the physical layer hardware. The privileged driver includes program instructions for implementing a protocol layer to decode the digital receive signal, encode the digital transmit signal, and configure the physical layer hardware for receipt of the digital receive signal and transmission of the digital transmit signal based on the plurality of control codes.
Type:
Grant
Filed:
July 9, 2001
Date of Patent:
January 11, 2005
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Rodney Schmidt, Geoffrey S. Strongin, David W. Smith, Brian C. Barnes, Terry L. Cole, Michael Barclay
Abstract: The present invention provides an apparatus for storing digital data, having: a multiplicity of memory cells (21) for storing digital data (14); an internal address generation device (15), connected to an address logic device (22), for managing and generating addresses; an internal control device (16), connected to the internal address generation device (15) and a control logic device (23), for controlling the address generation device (15) and the control logic device (23); a trigger input (11), connected to the internal address generation device (15), for clocking the internal address generation device (15); a control input (12), connected to the internal control device (16), for actuating the internal control device (16); and a data input/output (13) for interchanging digital data (14) on the basis of a trigger signal (11′) and a control signal (12′). The present invention likewise provides a method for storing digital data.
Abstract: A surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers.
Abstract: A memory card having a one-time programmable memory which stores a plurality of storage allocation tables and which is compatible with a host device.
Abstract: We present a lookup table which allows sparse subtree descriptors and dense subtree descriptors to be stored in the same memory. A subtree entry in the memory stores a dense subtree descriptor for a dense subtree or a plurality of sparse subtree descriptors for sparse subtrees. The subtree entry is indexed by a leaf in the previous subtree. The sparse subtree descriptor stores at least one node descriptor. The node descriptor describes a set of leaves in the sparse subtree having a common value. The common value is encoded in the node descriptor using run length encoding.
Abstract: When a request processing unit 2a receives processing request including memory access, it executes processing in accordance with the request, and when memory access takes place, it outputs access request to address designated by the processing request. A memory access proxy unit 2b sets memory protection information 1a of object 1 at a memory management unit 3a to output memory access instruction to a processor 3. The memory management unit 3a generates exception when memory access instruction from the memory access proxy unit 2b is access except for area set as memory protection information 1a. Thus, it is possible to carry out, at high speed, with high reliability, memory access such that, in accordance with request of an object, other object executes.
Abstract: A pointer representation includes a permission field to define capabilities of the system in processing the data to which an address in the pointer of representation points. Bounds of the memory segment to which the capabilities apply are defined by a block field, which defines a block size, and a length field, which defines a number of blocks of that size within the segment of memory. To permit computation of the full range of addresses to which the capability applies, a finger field is included to denote the block of the segment of memory to which the address points. An increment-only bit may cause the system to preclude any negative offsets from the address in the pointer representation. Subsegments within a segment may be further defined by additional block, length and finger fields.
Type:
Grant
Filed:
May 15, 2001
Date of Patent:
November 30, 2004
Assignee:
Massachusetts Institute of Technology
Inventors:
Jeremy H. Brown, Thomas F. Knight, Jr., Jeffrey P. Grossman, Andrew W. Huang
Abstract: In a system that includes a plurality of objects and at least one cache, wherein each object has a key associated therewith and is capable of having different values for at least two of a plurality of different contexts, a method for caching at least some of the plurality of objects is provided. The method includes the step of maintaining a cache directory structure in which at least two different values are capable of being associated with at least one of the plurality of objects, each of the at least two different values corresponding to a different context. An object to be cached is identified from among the plurality of objects and also a context from among the plurality of different contexts. The identified object is stored in the at least one cache based upon the key associated therewith and the identified context.
Type:
Grant
Filed:
November 14, 2000
Date of Patent:
November 23, 2004
Assignee:
International Business Machines Corporation
Inventors:
Louis R. Degenaro, Arun K. Iyengar, Thomas A. Mikalsen, Isabelle M. Rouvellou
Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.
Abstract: A processor includes a CPU, a data memory, a stack memory, a memory address generator, and a stack pointer generator. The CPU is used to process data and instructions. The data memory is used to store non-stack data. The stack memory is used to store stack data. The memory address generator is used to generate addresses for accessing the data memory. The stack pointer generator is used to generate pointers for accessing the stack memory.
Type:
Application
Filed:
October 21, 2003
Publication date:
September 2, 2004
Inventors:
Li-Chun Tu, Ping-Sheng Chen, Pao-Ching Tseng, Hung-Cheng Kuo
Abstract: The template data transfer coprocessor (TDTP) offloads block data transfer operations from a mediaprocessor. A uni-block template, program-guided template, an indirect template and queue-based template are described. The TDTP includes a template interpreter that employs an event-driven control mechanism to set up a template and compute block information and block information for each template. The programming involved in defining block data transfers for video and image processing algorithms is substantially reduced by the use of these templates.
Abstract: A processing of data in cooperation with a memory (MEM), for example an MPEG decoding, has the following characteristic features. A processor (P) generates a logic request (LRQ). The logic request (LRQ) defines at least one characteristic (CAR) common to a group of data (GRP). An addressing circuit (AGA) generates a physical request (PRQ) on the basis of the logic request (LRQ). The physical request (PRQ) defines memory (MEM) addresses (A) relating to the group of data (GRP). A memory interface (INT) effects a transfer (TRNSFR) of the group of data (GRP) between the memory (MEM) and the processor (P) on the basis of the physical request (PRQ). Thus, the processor need not know how and where the data to be processed or having been processed are stored in the memory. This facilitates the design of a data processing device and, particularly, a family of such devices.
Abstract: The invention is a new field in an ARP packet which designates the canonical format of the addresses written into fields such as ar$sha (the source station hardware address) and ar$spa (the source station protocol address) ar$tha (the target station hardware address), ar$tpa (the target station protocol address) so that a receiving station can determine the canonical format used to create these fields. The station receiving the ARP request or ARP response packet can then write its ARP table entry in the correct canonical format for its computer network.
Abstract: A data processing device includes a memory system capable of a plurality of simultaneous accesses, a plurality of address generators each generating an address for accessing the memory system, an addressing register having a plurality of address registers, a data processing unit providing an operation process to the data read from the memory system, and a control unit controlling operations of the plurality of address generators and the data processing unit. The plurality of address generators can generate addresses from a common value in one address register to simultaneously read data designated by the generated addresses from the memory system.
Abstract: A built-in self test (BIST) circuit and method is provided for testing semiconductor memory. A linear feedback shift register (LFSR) is used for addressing the memory locations to be tested. Test data is derived at least partially from the address data generated from the linear feedback shift register.
Abstract: A computer network system for manipulating requests for shared data includes a plurality of groups and each group has a plurality of nodes and each node has a plurality of processors. The system further comprises a request outstanding buffer (ROB) for recording data requests, a remote access cache (RAC) for caching the results of prior memory requests which are remote to a requesting node, and a directory for recording a global state of a cache line in the system. The RAC supports only two states, Shared and Invalid, and caches only clean remote data. If the directory state is Modified/Exclusive, the line is indicated to not be in the RAC. The behavior of the RAC is described for two important cases: initial RAC does not have the line caches and initial RAC has the line cached.
Type:
Grant
Filed:
July 14, 2000
Date of Patent:
July 20, 2004
Assignee:
Fujitsu Limited
Inventors:
Patrick N. Conway, Yukihiro Nakagawa, Jung Rung Jiang
Abstract: A lock-free list for use with a computer system. The lock-free list includes a list storage structure comprising at least two sublists, each of a plurality of list elements being sequentially assignable to one of the at least two sublists in such manner that a plurality of assigned list elements is partitionable across the at least two sublists, an indicator for indicating whether each of the at least two sublists is empty or in use, an indicator for indicating whether a list element is being removed from each of the at least two sublists, an indicator for recording an order of the at least two sublists into which the plurality of assigned list elements are assigned, and an indicator for recording for each of the at least two sublists, a write address location and a read address location.
Abstract: A transfer destination address generator includes an arithmetic device that calculates a difference between a transfer destination address and a transfer source address, a difference holding register that stores the difference, and an arithmetic device that calculates the transfer destination address based on the difference stored in the difference holding register, and on the transfer source address. A transfer source address generator includes a transfer source address register that stores a present value of the transfer source address, and a transfer source reload register that stores an initial value of the transfer source address.
Abstract: A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Once the segment register update operation is detected, a code/data segment contained within the segment register is identified as one of a segmented code/data segment and a flat code/data segment. Once detected, the segment register is updated according to whether the segment is flat or segmented. Accordingly, when a segment register read is performed, one or more updated bits within the segment register are used to identify the code/data read from the segment register as either flat or segmented.
Abstract: An apparatus and method for storing and retrieving data files from a storage medium are disclosed. A storage medium stores one or more data files and address information showing the path of each data file. The address information is characterized in that numerical values derived or converted from given parts of the path names are used as the address information, whereby a data configuration which occupies less memory space than storing the path names as character strings. A numerical value can be designated from the numerical values and a character string can be generated from the numerical value to retrieve a corresponding data file.
Type:
Grant
Filed:
December 6, 2001
Date of Patent:
June 22, 2004
Assignee:
Matsushita Electric Industrial Co., Ltd.
Abstract: To maintain order in a pipelined process, a number of memory locations of a result memory are sequentially reserved for a number of processes as the processes are sequentially dispatched for execution. As an integral part of the sequential reservation, validity determination facilitators to be subsequently employed to correspondingly facilitate determining whether valid processing results of said processes have been stored into corresponding ones of said reserved memory locations are also pre-determined. Additionally, the reserved memory locations are sequentially read to sequentially accept the processing results in order. Each value read from a reserved memory location is accepted only if the corresponding validity determination facilitator exhibits a predetermined relationship with a corresponding validity determination reference value. The validity determination reference values are complementarily maintained and integrally obtained through the sequential read process.
Abstract: An apparatus for influencing process scheduling in a data processing system capable of utilizing a virtual memory processing scheme is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space that is equal to the virtual address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The storage controller, which is coupled to a physical memory cache, allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address. The physical memory cache contains a subset of information within the hard disk.
Type:
Application
Filed:
December 12, 2002
Publication date:
June 17, 2004
Applicant:
International Business Machines Corporation
Inventors:
Ravi Kumar Arimilli, John Steven Dodson, Sanjeev Ghai, Kenneth Lee Wright
Abstract: A method and apparatus for a source synchronous address receiver for a system bus is described. A flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin.
Type:
Grant
Filed:
September 20, 2000
Date of Patent:
June 8, 2004
Assignee:
Intel Corporation
Inventors:
Srinivasan T. Rajappa, Romesh B. Trivedi, Rajagopal Subramanian, Zohar Bogin, Serafin Garcia
Abstract: The present invention is directed to a memory that allows two simultaneous read requests with improved density. In an aspect of the present invention, a memory module includes at least two primary memory sub-modules and an additional memory sub-module including a sum of values located in the at least two primary memory sub-modules at corresponding addresses. The sum of the additional memory module enables at least two simultaneous read requests to be performed.
Type:
Application
Filed:
December 3, 2002
Publication date:
June 3, 2004
Inventors:
Egor A. Andreev, Anatoli A. Bolotov, Ranko Scepanovic, Alexander E. Andreev
Abstract: The present invention may provide a digital memory circuit comprising a plurality of multi-bit registers, a memory circuit interface, and a logic circuit. The memory circuit interface may be configured to access a selected one of the registers. The logic circuit may be coupled to the plurality of multi-bit registers and responsive to data received through the interface for selectively writing a predetermined logic state to at least one first bit of the selected register while leaving at least one second bit in the selected register with an unmodified state.
Abstract: A data processing system, method, and computer program product for automatically tracking insertions of integrated circuit devices into receptacle devices. An insertion of an integrated circuit device is automatically detected utilizing the data processing system. An insertion count that is associated with the integrated circuit device is automatically incremented in response to a detection of an insertion of the integrated circuit device. The insertion count is used to track insertions of the integrated circuit device.
Type:
Grant
Filed:
October 4, 2001
Date of Patent:
June 1, 2004
Assignee:
International Business Machines Corporation
Inventors:
George Henry Ahrens, Jr., Susan L. Caunt, Alongkorn Kitamorn, Leo C. Mooney
Abstract: A method of downloading application programs on the editing system platform of an electronic communication apparatus, includes the step of connecting an electronic communication apparatus to the Internet, the step of driving an editing system of a processor of the electronic communication apparatus to define a total area from a memory thereof for use by the application programs to be downloaded from the Internet, for enabling the application programs to be stored in any address within the total area, the step of driving the editing system to directly correct the operating instruction of direct address searching to the correct address when downloading an application program from the Internet and then to search the address after address correction, and the step of using a software interrupt (SWI) to alternate the operating instruction of indirect address searching so as to obtain the desired correct address for the editing system for further indirect address searching operation.
Abstract: The disclosed device, system and methods of data management facilitate the implementation of improved mirroring, back-up, volume remapping and extent relocation, among others. The disclosed intelligent I/O stream splitter may intercept and alter an I/O stream from a communications link. In the case of mirroring, the intelligent splitter may intercept write commands and associated data from a mainframe that target a specific storage location on a specific control unit. The splitter may then transmit the intercepted I/O stream to the targeted control unit and storage location over one link and transmit on another link an altered version of the intercepted I/O stream to another control unit, which is responsible for holding a mirrored version of the data. The altered version could have the same data as that on the one link, or may include new frame headers, changes to the control information, or changes to the data itself.
Type:
Grant
Filed:
June 28, 2000
Date of Patent:
May 11, 2004
Assignee:
Sepaton, Inc.
Inventors:
Seweryn Mokryn, Alexander Winokur, Marek Mokryn
Abstract: A system for recording data to a disc shaped record medium. The data is recorded according to a universal disc format employing a hierarchical file system, and data within the hierarchical structure is referenced using pointer information. The pointer information includes a file identifier descriptor and a file entry and is recorded such that the pointer information and its corresponding substantive data are stored at successive addresses.