Abstract: System and methods for addressing unique locations in an matrix are discloses. According to some embodiments, the system includes In another embodiment, a system consisting of a plurality of uniquely addressable locations is disclosed. These embodiments includes a plurality of virtual columns that include a plurality of serially connected switch elements. The plurality of switch elements may be one of a plurality of responsive types and responsive to at least one of a plurality of possible switching signal types.

Abstract: In a heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems, an I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least one disk connected to the I/O subsystem B in a magnetic tape library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: A memory module is provided with a resistor serving as an impedance adjuster which is connected directly or indirectly to an output terminal of an output transistor of a C/A register. The resistor adjusts the output impedance of the C/A register viewed from an input terminal of a C/A bus in such a manner that the output impedance becomes substantially constant within an operating voltage range of an internal signal output from the C/A register. The memory module is further provided with a capacitor serving as a rise time/fall time adjuster which adjusts rise time and fall time of the internal signal to specific values such that satisfactory waveforms are obtained.

Abstract: A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.

Abstract: A memory to support a first address protocol in response to a first control signal and a second address protocol in response to a second control signal.

Abstract: M memory cells (MC) in each of which a ferroelectric capacitor (FC) and a selector transistor (CTR) are connected in series are connected in parallel between a drive line (DL) and a bit line (BL). One end of the bit line (BL) is connected to a gate electrode of a read transistor (STR). Thus, the number of memory cells connected to the bit line (BL) can be reduced so that wiring capacitance of the bit line (BL) can be lowered, without incurring any increases in area and cost, as in the case where a sense amplifier is used. As a result, a voltage induced to the bit line (BL) can be regarded as not depending on remanent polarization of the ferroelectric capacitor (FC). Accordingly, the area of the ferroelectric capacitor (FC) can be reduced, allowing high integration to be implemented.

Abstract: An embodiment of the present invention includes a tag array, a valid vector, and a detector. The tag array stores N tag entries. Each of the N tag entries contains a one-hot tag having K bits. Each of the K bits of the one-hot tag corresponds to a translation look-aside buffer (TLB) entry in a TLB array having K TLB entries. The valid vector stores N valid entries corresponding to the N tag entries. The detector detects an error when a tag entry is read out upon a fetch read operation.

Abstract: In order to make memories more secure against interference occurring in operation, error correction devices are normally associated with them. If the memory contents of the storage location (1) are accessed by evaluating the location current, the problem arises that the location current is both value-continuous and time-continuous. If leakage currents occur in the storage location (1) that lead to an increased storage location current, then the current sensor amplifier (2) can fall below these values only with a constantly increasing access time between the values 0 and 1. When leakage currents occur the current sensor amplifier (2) for evaluating the location current may therefore switch over at arbitrary times.

Abstract: A processor has a native word width of multiples of a byte width. The processor may, nonetheless, process, store and retrieve data in word or byte widths depending on the mode of an instruction directing the processing. Instructions may assume either a word or a byte mode. In the word mode, the instruction causes the processor to read, store and operate on word width data. In the byte mode, the instruction causes the processor to read, store and operate on byte data where the byte is specified based on upper/lower byte bits in the instruction. This architecture permits a new generation of processor having word widths of more than one byte to be backward compatible with software written for byte width processors.

Abstract: A method and circuit for linear space target address generation for a relative branch is described. A selection signal is generated to be used in generating a linear space target address. The generation of the linear space target address includes generating multiple corrected target addresses and selecting the linear space target address from the multiple corrected target addresses using the selection signal. The process of generating multiple corrected target addresses includes generating first, second, and third corrected target addresses. The first corrected target address is generated using an address and a displacement. The second corrected target address is generated using the address, displacement, and a second adder correction value. The third corrected target address is generated using the address, displacement, and a third adder correction value. A multiplexer outputs the first, second, or third corrected target address using the selection signal.

Abstract: A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.

Abstract: The present invention relates to a semiconductor memory having a pre-fetch structure. In such memory, an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant cell array, firstly, the present invention comprises a redundant memory, which stores an odd redundant address and an even redundant address, together with odd and even selection data. Since redundant memory is used flexibly on the odd side and even side, it is possible to maintain a high relief probability even when redundant memory capacity is reduced.

Abstract: A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way.

Abstract: A method of calculating a formula on a collection of series of data values, the method comprising the steps of: (a) for each data value member of a first one of the collection, determining a window around a current data value member of data values required to calculate the formula; (b) utlizing the window to determine the memory location of the stored location of corresponding data values in the calculation of the forumula when applied to other series of data values in the collection.

Abstract: During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.

Abstract: A memory rewriting system for a vehicle controller is provided. The memory rewriting system transfers a first program from a rewriting device to the vehicle to rewrite a second program stored in a memory of the vehicle controller with the first program. The first program is transferred as data blocks. Each of the data blocks includes a program code field, a first address field and a second address field. The program code field contains a partial program code of the first program. The first address field contains a leading address of the memory in which the partial program code is stored. The second address field contains a leading address of the memory in which a following partial program code transferred by another block is to be stored. The data blocks are assembled in the rewriting device. Each data block is may be a fixed length or a variable length.

Abstract: In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Virtual-to-real address translation of a Target system effective address to a Host system virtual addresses is performed by identifying a working space for the effective address, determining a working space base address for that working space, and then performing a linear translation multiplying the effective address by a constant and adding it to the working space base address to generate the host system virtual address.

Abstract: In a single-chip microcomputer including a nonvolatile semiconductor memory device and write, read and erase circuits for performing a write operation, a read operation and an erase operation upon the nonvolatile semiconductor memory device, respectively, a sequencer is connected between the write, read and erase circuits and an interface. The sequencer receives first data via the interface from the exterior to write the first data into the nonvolatile semiconductor memory device, reads the first data from the nonvolatile semiconductor device, compares the first data with second data read via the interface from the exterior thus performing a verification upon the nonvolatile semiconductor memory device, and reads third data from the nonvolatile semiconductor memory device and transmits the third data via the interface to the exterior.

Abstract: The storage medium of the present invention, storing one or more data files and address information showing the path of each data file, is characterized in that numerical values derived from given parts of the path names are used as address information, a data configuration which occupies less memory space than storing the path names as character strings.

Abstract: An embodiment of the present invention includes a speculative rename table (SRT), a shadow array, and an update circuit. The SRT stores mapping of frequent and infrequent registers. The frequent registers are frequently modified by instructions dispatched from a processor core. The infrequent registers are infrequently modified by the instructions. The shadow array stores shadow registers. Each of the shadow registers contains a rename state of a corresponding frequent register after a branch instruction. The update circuit transfers contents of the shadow registers to the frequent registers based on a selection condition.

Abstract: A description is given of a memory device having memory cells for storing data. The memory device described is distinguished by the fact that a current switch-off device is provided, which prevents an existing current flow through the memory cell to be read in response to the identification of the memory cell content, and/or that a discharge device is provided, which partly discharges again a node in the memory cell which is to be precharged before the memory cell is read.

Abstract: A system and method for transparent handling of extended register states. A set of additional registers, or an extended register file, is added to the base architecture of a microprocessor. The extended register file includes two dedicated registers and a plurality of general-use registers. The extended register file is mapped to a region in main memory. One dedicated register of the extended register file stores the physical base address of the memory region. Another dedicated register of the extended register file is used to store bits to indicate the status of the extended register file. A set of extended instructions is implemented for transferring data to and from the extended register file.

Abstract: A multi-channel signal processing apparatus comprises a memory unit, a signal processing unit for single-channel implementing predetermined signal processing using a memory region of the memory unit according to a signal processing program for single-channel, an address generation unit generating a first memory address for single-channel processing, a pointer adding unit adding a pointer value indicating the head of an unused memory region of the memory unit to the first memory address generated by the address generation unit each time the signal processing in the signal processing unit is completed to generate a second memory address, and an address selecting unit selecting either the first memory address or the second memory address as a real address for the memory unit, thereby enabling multi-channel signal processing having a high processing efficiency without adding a large modification to the signal processing program for single-channel.

Abstract: A computer system allows devices to be unmasked so to be detected or to be masked invisible to the Plug-and-Play architecture or similar architectures. When operating under Plug-and-Play, which assigns systems resources to system devices in a predetermined order despite a limited number of such resources, a user uses software to set the switch in the device's memory such that an undesired device becomes “invisible” to a subsequent power-up configuration of the system. Device configuration proceeds in two phases. During a first configuration phase, the invisible device cannot be configured, i.e. cannot be assigned resources, including interrupt request lines. Hence, those lines remain available to other devices on the system that would not have received resource allocation during a prior-art configuration. During the first phase, the other devices can be assigned the necessary resources to operate properly. Thus, software can command a configuration that would otherwise be impossible.

Abstract: A memory module architecture that supports Flash and static memory devices in addition to dynamic memory devices. The module architecture of the present invention preferably redefines standard application of chip select signals on existing module architectures to provide requisite signaling to support Flash and static RAM devices. Use of serial presence detect signaling features of standard memory modules is also modified to provide desired identity and parameters of such an enhanced module. Extending the range of supported memory devices in an otherwise standard memory module reduces the need for special designs to accommodate different and evolving types of memory and is therefore particularly applicable to embedded systems where a variety of memory types are often utilized.

Abstract: A data structure and method implemented in accordance with the invention enable reading a cache to get a type information corresponding to an address of interest more reliably than with volatile read operations and faster than scanning tables or walking along linked lists. Reliably reading the cache enabled by the invention does not require locks, although, the type information and the address together require more bits than those present in one machine word.

Abstract: A method for processing partial lines of image data from a detector, each partial line of data representing a portion of an image pixel matrix, includes: (a) communicating partial lines of image data over a network from an imaging system to a remote facility; (b) receiving partial lines of image data in a first sequence; (c) assigning to each partial line of image data in a first series a position in a second sequence by reference to a plurality of base addresses; (d) altering the base addresses; and (e) assigning to each partial line of image data in a second series a position in the second sequence by reference to the altered base addresses.

Abstract: An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one of the memory cells, a first word line can be connected to a supply circuit via a controllable first switching device and a second word line can be connected to the supply circuit via a controllable second switching device. A control circuit can drive the first switching device in dependence of an activation state of the second word line and the second switching device in dependence of an activation state of the first word line. Consequently, existing word lines that are not currently being used can be used for addressing one of the memory cells. As a result, only one wiring plane is required for the word lines.

Abstract: The present invention provides a semiconductor memory device and memory system comprising a first semiconductor memory having a first peripheral circuit for transmitting and receiving memory data to/from a first memory cell array, a second semiconductor memory having a second peripheral circuit for transmitting and receiving the memory data to/from a second memory cell array, and a part of the peripheral circuit of the first semiconductor memory formed adjacent to the second memory cell array by a design rule of the second peripheral circuit.

Abstract: A data structure and method implemented in accordance with the invention enable reading a cache to get a type information corresponding to an address of interest more reliably than with volatile read operations and faster than scanning tables or walking along linked lists. Reliably reading the cache enabled by the invention does not require locks, although, the type information and the address together require more bits than those present in one machine word.

Abstract: Method for refreshing data stored in an electrically erasable and programmable non-volatile semiconductor memory including at least one two-dimensional array of memory cells containing a plurality of individually erasable and programmable memory pages. Each time a request to modify a content of a memory page is received by the memory, the method provides for modifying the content of said memory page and submitting a portion of the two-dimensional array to a refresh procedure. The refresh procedure includes detecting memory cells of that memory portion that have partially lost a respective datum stored therein and reprogramming the datum in the detected memory cells.

Abstract: A silicon-on-insulator (SOI) SRAM memory cell having a plurality of MOS transistors wherein one or more of the conductive bodies of the transistors are connected by semiconductor material which extends beneath a partial (shallow) trench.

Abstract: Improved method of replication-based garbage collection in a multiprocessing system comprising a plurality of processors, a memory divided into a current area (from-space) used by the processors during current program execution and a reserved area (to-space), and at least a garbage collector for performing, when necessary, a garbage collection consisting in flipping the roles of the current area and reserved area after all the live objects stored in current area have been copied into the reserved area and for reclaiming the current area after the flipping operation. Several program threads (mutators) are currently running in parallel and the garbage collector performs the garbage collection in parallel with the program threads, the flipping operation being performed after the program threads have been stopped and the garbage collection has been completed.

Abstract: An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad.

Abstract: A multiple changeable addressing mapping circuit is disclosed for converting an input logic address of a field array in a data array into an output physical address. The circuit has multiple address mappers for process the conversion between the input logical address and the output physical address. The circuit also has a mapper selector for selecting an address mapper to output physical address. The circuit further has a control and interface circuit for setting the registers in the address mapper, and controlling the address mapper and mapper selector.

Abstract: An information processing apparatus and method for controlling selection of data displayed on a display device. A desired area of the displayed data is selected using an input device, and a processor compares a size corresponding to the selected desired area to a maximum storage capacity of a memory device that stores the selected desired area. The processor controls the size of the selected desired area not to exceed the maximum storage capacity of the memory device.

Abstract: A flash memory device capable of compensating the decrease of a threshold voltage of an unselected cell due to the drain coupling caused by a drain voltage supplied to a bit line of a selected cell is disclosed. The flash memory device provides a ground voltage to a source line of the selected cell while supplying a preset voltage to a source line of the unselected cell. The flash memory device employs a decoding unit for supplying a program voltage to a word line selected from a cell array based on a global word line signal, a local word line signal and a predecoder signal. The decoding unit also provides a ground voltage to a source line corresponding to the selected word line in response to a sector program signal and an inverted sector program signal and inputs a preset voltage higher than the ground voltage to source lines of unselected cells.

Abstract: A multilevel data locking mechanism is described. The mechanism determines the cost of multiple granularities of locks for a query prior to initiating a transaction. Locking selection is performed by a lock manager, and is based on row, page and table granularities. An SQL server provides access to a database comprising rows of data arranged in tables. A table has multiple rows per page, and multiple pages per table. Characteristics of the database schema and query are considered in determining which granularity will result in the lowest cost. These factors include the number of rows per page, the number of rows per index scan, the isolation level per scan, an update factor which is related to how long modified rows are held, the memory load on the system, the cost of concurrency which is based on the number of rows per page and pages per table, and the number of active scans currently on the table. The proper granularity is determined at run time to ensure that the current state of the system is considered.

Abstract: Object of the present invention is to provide an address converting circuit capable of converting a virtual address that access is required into a physical address. The address converting circuit of the present invention has a CLA circuit, an adder, a CAM, a carryout selector, a physical address storing section, and a physical address selector. When adding both of the upper bit strings of the base address and the offset address that access is required, before the carryout signal from the lower bit string is calculated, addition of both of the upper bit strings in case of presuming the carryout signal as “0” and addition of both of the upper bit strings in case of presuming the carryout signal as “1” are performed. Either of the added results is selected by the carryout signal in order to perform the comparing process. Because of this, it is possible to convert into the physical address at high speed.

Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock since the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: Disclosed inventions include circuits and methods for controlling a plurality of data input buffers and a plurality data strobe buffers in a semiconductor memory device. High speed operation can be achieved by operating the plurality of data input buffers and the plurality of data strobe buffers in response to a buffer control signal generated faster than an input data, synchronized with internal rising and falling clock signals. A first internal falling clock signal generator generates a first internal falling clock signal in response to an external clock signal. A first internal rising clock signal generator generates a first internal rising clock signal in response to the external clock signal. A buffer controller generates a buffer control signal in response to the first and falling and rising clock signals. The plurality of data input buffers and the plurality of data strobe buffer are enabled or disabled in response to the buffer control signal.

Abstract: A data processing system is provided with a flash memory including a plurality of blocks and capable of erasing stored data collectively in units of block and a memory control unit for accessing the flash memory, the memory control unit having a control circuit for formatting the flash memory according to a format information for substantially coinciding each cluster serving as a logical unit of memory region of the flash memory with integer ones of the blocks and a control circuit for determining a size and position of each cluster and carrying out access control for erasing, write-in and reading of data of the flash memory according to the size and position of the determined cluster.

Abstract: In a data processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses, having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data, an arrangement for extending a range of addressable storage beyond the basic range allowed by the instruction codes. The processor is equipped to generate a long address, i.e., 30-bits, even though the instruction execution means can only generate a 23-bit address. When the processor goes into an alternate mode, the contents of a segment control register are prefixed onto the addresses generated within the processor when a certain class of instructions are executed.

Abstract: The present invention relates to a multi-port register file memory including a plurality of storage elements in columns. The storage elements are arranged in rows and columns and store data. At least one read port is coupled to each of the storage elements and a sensing device is coupled to the read port. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A pair of series transistors coupled together act as the read port while a column mux circuit is coupled to each column and the sensing device. The sensing device includes two inverters comprising input offset and gain stages. An offset device biases the local bitlines at a voltage close to the sense amplifier trip point.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention process a virtual call during execution of a multi-threaded program by ensuring that the steps of patching the virtual call to the appropriate method are performed within a single instruction cycle. This prevents other threads from executing instructions related to the virtual call in the middle of the patching procedure. Methods, systems, and articles of manufacture consistent with the present invention identify a target, such as a targeted method and a class of a receiver object, associated with the virtual call and then determine an address identifier, such as a memory address pointer to the class of the receiver object.

Abstract: A fast division technique is provided to calculate the address of a slot in a paged object, when the slot is located on a different page than the beginning of the object. The fast division technique employs arithmetical-logical operations of shifting and masking, that are faster than most hardware implementations of integer division and modulus, respectively. In one aspect, the use of these operations is facilitated by requiring the page size and the size of the page header to be a power of two.

Abstract: An integrated magnetoresistive semiconductor memory in which each memory cell contains a switching transistor or a diode in the form of an activatable isolating element, and two magnetic layers that are isolated by a thin tunnel barrier. Connecting conductors are respectively integrated for word lines, digit lines and bit lines and also for the purpose of activating the switching transistor in one or more memory cells. These connecting conductors are located in only two metallization planes and in a polysilicon connection plane.

Abstract: The present invention provides a method and an apparatus for transferring data between a computer system and a network interface card that avoids virtual-to-physical address translations. The computer system allocates blocks of memory during system initialization for storing data in transit between the computer system and the NIC, and the physical addresses of these blocks of memory are stored in a table on the NIC. Consequently, address conversion is performed only once, when the memory is allocated. When a request to transfer data to the NIC is received from the upper layers, the device driver copies the data from the upper layers into the next available memory block. The device driver then formats a command and passes it to the NIC for processing. Data transfer commands are communicated to the NIC through a packet descriptor command (PDC), which is a 32-bit value subdivided into fields that completely describe the data transfer operation.