Abstract: An improved apparatus and method for providing addresses for accessing circular memory buffers is provided. An apparatus comprised of a first feedback circuit, a second feedback circuit, a beginning address register, an ending address register, and a comparator circuit. A control circuit is also provided. The beginning and ending address registers preferably include the beginning and ending addresses respectively of a circular memory buffer. The first feedback circuit is comprised of a first register, a first phase delay register, a first adder, a first displacement register, and a first multiplexer. The second feedback circuit is preferably comprised of a second register, a second phase delay register, a second adder, and a second displacement register.

Abstract: A data storage device comprises a controller and a semiconductor chip which includes a nonvolatile semiconductor memory having plural storage areas into each of which data is stored, a store instruction signal input terminal to which a store instruction signal is inputted, a storage controller for storing data into the semiconductor memory when receiving a store instruction signal through the store instruction signal input terminal, a read instruction signal input terminal to which a read instruction signal is inputted, and a read controller for sequentially specifying one of the storage areas in the semiconductor memory each time it receives a read instruction signal through the read instruction signal input terminal and then reading the data stored in the specified storage area.

Abstract: Disclosed is a bus bridge for mutually connecting a memory bus having memories connected thereto and an I/O bus having plural I/O devices connected thereto, which comprises a conversion table in which pairs of entry and physical address are included and which is divided into a fixed part and a refillable part; an address conversion means for converting a logical address supplied from the I/O device to a physical address supplied to the memory, while selectively using the fixed part or the refillable part in accordance with whether the logical address is in address remapping space or in I/O-TBL space; and refilling means for refilling the contents of the refillable part from a mother address conversion table on a memory in case that the logical address is in the I/O-TBL space and the entry corresponding to the logical address does not exist in the refillable part.

Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

Abstract: A digital system is disclosed for use with a host, the digital system including a controller and a nonvolatile memory unit having memory locations organized in blocks with each block having a plurality of sectors for storing information provided by the host in the form of non-user data files and user data files, the controller for controlling reading, writing and erasing operations performed on the nonvolatile memory, the host providing to the controller an address, identifying the starting location of the user file to the controller, and a user file identified by a starting sector address for storage within the nonvolatile memory unit. The controller finds a free block within the nonvolatile memory unit that is available for storage of information, and aligns the user file starting address with the beginning of the free block, and stores the user file within the free block starting with the beginning of the free block.

Abstract: In this invention, data track of a magneto-optical disc is divided into a volume management area and an extent area to record data of file into the extent area, and to record directory management information and file management information into the volume management area. The volume management area is caused to consist of 32 clusters. Data allocation unit of the volume management area is caused to be 2 k bytes and data allocation unit in the extent area is caused to be 8 k bytes. Relative recording location within the volume management area of sub directory is recorded, as directory information, into the volume management area. Thus, this invention can quickly carry out access.

Abstract: A network switch configured for switching data packets across multiple ports uses an address table to generate frame forwarding information. The address table includes address entries storing address information and data forwarding information. The data contained in the table may be modified by a management agent in one of two modes. In the first mode, data can be written to individual fields in an address entry. In the second mode, data can be written to the address table as complete address entries.

Abstract: A data transfer system includes a memory having first and second memory areas for storing information and being identified by different addresses, first and second address memories for storing the address of the first and second memory areas, and a central processing unit for reading information from the first memory area on the basis of the address stored in the first address memory. The central processing unit also writes new information in the first memory area on the basis of the address stored in the first address memory, and also stores the information read from the first memory area in the second memory area on the basis of the address stored in the second address memory. In addition, the second memory area can have a portion called a common area, in common with the first memory area. The central processing unit can read information from the first memory area including this common area on the basis of the address in the first address memory.

Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset.

Abstract: An apparatus having a stack-top updating unit for processing an exchange instruction and a load instruction in parallel in a pipe-lined processor having a stack register file. Based on an information signal representing a modification of the stack-top after the current instruction is executed in a first pipe-line, a control signal indicating that a load instruction is executed by one of the first and second pipe-lines, and a second pipe-line enable signal, the stack-top updating unit generates a new stack-top signal and a current stack-top signal. The first pipe-line, in response to the current stack-top signal and operands, executes the operands, and the second pipe-line, in response to the new stack-top signal and the control signal, performs the load instruction or an exchange instruction. As a result, the load instruction or the Fload instruction can be simultaneously executed with another instruction or operand in the pipe-lined processor in an effective manner.

Abstract: A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed and physically tagged. The branch target index (if predicted-taken, or the sequential index if predicted not-taken) is provided as the index to the instruction cache. The selected physical tag is provided to a reverse translation lookaside buffer (TLB) which translates the physical tag to a virtual page number. Concatenating the virtual page number to the virtual index from the instruction cache (and the offset portion, generated from the branch prediction) results in the branch target address being generated. In one embodiment, the process of reading an index from the branch prediction storage, accessing the instruction cache, selecting the physical tag, and reverse translating the physical tag to achieve a virtual page number may require more than a clock cycle to complete.

Abstract: A modulo address generation circuit for generating multiple-word memory accesses for use in a computer system. The circuit includes an address pointer latch for retaining a current address pointer, an adder for receiving the current address pointer as a first input and a displacement as a second input. The adder for adding the inputs to provide an output. A comparator compares the current address pointer to an ending address of a circular buffer ignoring least significant bits thereof when the displacement is greater than one. The comparator provides an output that is a first state when the inputs are the same and an output that is a second state when the outputs are different. A control circuit is adapted to receive an indicator of the beginning address of the circular buffer, an indicator of the current address pointer, and an indicator of the ending address of the circular buffer.

Abstract: A backup system enables unmodified data to be copied to a read-only backup container that is smaller than the read-write container. The system creates and maintains structures that map the unmodified copies of data in the backing store container to locations in the read-write container. The mapping structures contain addresses of locations in the backing store container where collections of blocks of data are stored based on the original data block address of the data in the read-write container. In order to obtain the address of the location in the backing store container where a block of data is stored, the system converts the physical block number of the read-write block of data into a physical block address in the backing store container which actually contains the data.

Abstract: A first register stores a value that can be used as a pointer to indirectly address a second register. The first register is referred to as a pointer register and the pointer as a register pointer. The second register may be a conventional register that stores a conventional register value (i.e., a data value or a pointer to a data value stored in external memory) or another pointer register. In certain embodiments, a pointer register can also be used to store conventional register values. Pointer registers of the present invention can be used to implement efficiently certain types of digital processing, such as circular buffers, vector processing, convolutional processing, and partitioned processing, using data in registers rather than memory.

Abstract: A memory system includes a data memory and a distinct cache status memory for storing status information regarding the data memory. A memory controller generates timing and control signals for accessing the data memory in a page mode while concurrently accessing the cache status memory in a word mode. In the preferred embodiment, the data memory is accessed in a four word per page mode while a read-modify-write operation is performed on an associated cache status memory. In order to conserve pins on the memory controller, the cache status memory shares a substantial portion of the address lines which are received by the data memory. Supplemental cache status address lines are generated by programmable control logic, which may be incorporated into the memory controller. Programmable control logic generates supplemental address lines based on the maximum number of data memory modules, the size of an addressed data memory module and the number of cache status columns.

Abstract: A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a first sample page base address corresponding to a first part of a first address received from a digital signal processor (DSP). The present invention also generates a second sample page base address corresponding to a first part of a second address received from the DSP. The first and second generated sample page base addresses are then stored in respective first and second locations within a multiple entry sample page base address cache which can be accessed by the DSP without accessing a PCI bus. The first part of the first address is compared to a first part of a third address.

Abstract: In order to generate internal addresses from an external address in a burst operation in a synchronous dynamic random access memory (SDRAM), an external address is latched in response to an external clock signal. First and second control signals are generated in synchronous with the external clock signal. An internal address for a first clock cycle of a burst operation is generated from the latched external address in a sequential mode in response to the first control signal using a first transfer path. An internal address for each of a second clock cycle and subsequent clock cycles of the burst operation in the sequential mode is generated in response to a second control signal using a second transfer path such that the internal address for each of the second clock cycle and subsequent clock cycles has substantially the same delay time as that of the internal address for the first clock cycle with respect to the external clock signal.

Abstract: In executing indivisible operations to be executed without being interrupted, pseudo-store instructions PST which do not perform data writing are used to perform a check for the presence or absence in a memory of pages necessary for execution of the indivisible operations. In the event of absence of the necessary pages, the necessary pages are pre-stored in the memory. This prevents the generation of page fault interruptions during the execution of an indivisible operation, thereby enabling the indivisible operation to be implemented on a software basis. A disable interrupt instruction is executed prior to the execution of the indivisible operation as required, and data indicating an address of the disable interrupt instruction is preserved in order to return to the disable interrupt instruction.

Abstract: A convolutional interleaver for interleaving a data stream composed of N number of data with predetermined interleaving level B to randomize the data stream for an error correction, comprising: an input buffer; a memory; an address generating unit; an output buffer; and a controller, and a method for generating an address of the memory are disclosed. In the method for generating an address of the memory, a basic memory of which the number of vertical end is B-1 and horizontal length is (B-1).times.M cell is transformed to an intermediate memory of which the number of vertical end is B-1 and horizontal length is (B/2).times.M cell, and a physical address for accessing the intermediate memory is generated.

Abstract: A method and apparatus for dynamically updating virtual to physical address mappings in order to reduce cache thrashing is disclosed in an example computer system having a memory apportioned into a number of pages. A cache is included in the computer system to store a subset of the pages of memory. Each of the pages of memory is addressed by a physical address that includes a cache page address portion. The pages of cache memory are accessed using a cache page address, which corresponds to the cache page address portion of the physical address of a corresponding page of memory. The disclosed system monitors the activity of virtual addresses and uses the activity of virtual addresses to increment cache page address activity counters. The cache page address activity counters are monitored to identify those cache page addresses that are frequently being accessed within a process to identify potential performance problems, such as thrashing.

Abstract: A microcontroller is presented including additional hardware which generates multiple auxiliary address signals needed to expand the memory address space of the microcontroller. The auxiliary address signals allow access to memory locations within external memory devices which would not otherwise be accessible while advantageously maintaining software compatibility with previous microcontroller products. The auxiliary address signals form the most significant bits of augmented addresses, thereby dividing memory locations within the external memory devices into multiple memory banks of equal size. When memory banking is enabled, software instructions select the desired memory bank by writing appropriate values to address bit positions within a memory banking control (MBC) register. The auxiliary address signals are normally produced having values stored within corresponding bit positions of the MBC register.

Abstract: An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and a minimum array size boundary value. The array boundary checking apparatus of the invention includes an associative memory element that stores and retrieves a plurality of array bound values. Each one of the plurality of array bound values is associated with one of the plurality of array access instructions. An input section simultaneously compares the array access instruction identifier with at least a portion of each of the stored array reference entries, wherein the array access instruction identifier identifies an array access instruction. An output section is configured to provide as an array bounds output values one of the plurality of array bound values stored in one of the plurality of memory locations of the associated memory element.

Abstract: The memory device comprises a cache memory indexed by the cache index and group information of the virtual address. The physical address translated from the virtual address contains primary and secondary group information. If the tag of the cache entry addressed according to the above standard by indexing of the cache memory corresponds to the physical address, indexing is carried out again using the second group information associated with the physical address (and using the cache index of the virtual address). If the tag of the cache entry thus addressed still does not correspond to the physical address, a cache miss is signaled.

Abstract: A deinterleaver includes a first storage unit for storing data an order of which is rearranged from a correct order to a random order, a data latching unit for temporarily holding output data of the first storage unit, a second storage unit for storing output data of the data latching unit, and an addressing unit for generating a read addressing signal which is outputted to the first storage unit, and a write addressing signal which id outputted to the second storage unit. The addressing unit includes a counting unit for counting a clock to generate the read addressing signal, and an arithmetic unit for generating the write addressing signal for rearranging to the correct order using the read addressing signal outputted from the counting unit.

Abstract: A logical address and a pointer entry for a file in an indirect address file system are translated into a physical address. A decision module tests a pointer flag in a present pointer entry. The pointer entry has a pointer and a pointer flag to identify whether the pointer points to a data storage area or a metadata storage area. The decision module indicates whether the pointer is a data pointer or a metadata pointer. In response to the decision module indicating the pointer is a data pointer, a set module combines the data pointer with the logical address to generate a physical address. A split module, in response to the decision module indicating the pointer is a metadata pointer, divides the logical address into a first portion as an index value and a remaining portion as an offset value. An update module then sets the logical address to the offset value. A retrieve module combines the metadata pointer with the index value to get the next pointer entry.

Abstract: A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a sample page base address corresponding to a first part of a first address received from a digital signal processor (DSP). The generated sample page base address is then stored in a sample page base address cache which can be accessed by the DSP without accessing a PCI bus. The first part of the first address is compared to a first part of a second address. Provided that the first part of the first address and the first part of the second address are the same, the present invention combines a second portion of the second address sent from the DSP with the generated sample page base address stored in the sample page base address cache. In so doing, the present invention generates a complete address of a sample to be fetched without accessing the PCI bus.

Abstract: In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative of one greater than an ending address, a second input that is a beginning address, and a select input that is the sign of a displacement for stepping through addresses in a circular buffer. The first selector is adapted to select one of its inputs as an output. A first adder combines an address pointer and displacement to produce a first potential next address pointer. A second adder combines the address pointer, the displacement, and a length modified by the sign of the displacement to produce a second potential next address pointer.

Abstract: In a computer system including a disk subsystem having channel interface compatible to a count-key-data format and a SCSI interface compatible to a fixed length data format, the disk subsystem is connected to a CPU controlled by an open system operating system through the SCSI interface, and connected to an other CPU controlled by a main frame operating system through the channel interface. The CPU is provided with a CKD record access library and a VSAM access library which accesses in a FBA format the VSAM record stored by the other CPU in a CKD format in the disk subsystem and allows the access by an application program of the CPU as a VSAM record based on VSAM control information.

Abstract: Method, apparatus and program are provided for replicating an image of a source hard disk (22) onto a larger destination hard disk (22') in a manner that renders available the non-image-utilized sectors of the destination hard disk. Destination disk address dimensions are obtained from a drive (24') which handles the destination hard disk. Both source disk address dimensions and an image of sectors stored on the source disk are obtained from a temporary storage media (84). The image of the source disk is recorded on the destination disk (22'), but address values stored in the sectors of the image are adjusted to be based on the destination disk address dimensions rather than the source disk address dimensions.

Abstract: An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM (SDRAM) is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a SDRAM during a test process in real time and generates column addresses for the SDRAM by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, a Z address signal, and an operation mode control signal, a conversion memory that outputs data based on a conversion table, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with a burst length control signal.

Abstract: Integer permutation is performed while a data sequence is transferred between buffers 1 and 2 alternately. Each data piece is divided into four elements and integer permutation is executed with the elements as keys from low-order to high-order elements. In the integer permutation, the data pieces are stored in the storage areas in the buffers in pack relation. To enable this, for each value of each element, a dividing analysis section 10 preliminarily surveys the number of data pieces having the element of such a value, and initializes pointers for specifying areas into which data pieces having the elements of each value are to be written. A digit place setting section 21, a digit place sort section 22, a switch circuit 30, and switches SW1 and SW2 determine the value of the corresponding element of data read from the buffer and guide the pointer required for data write to an address terminal of the buffer from the dividing analysis section 10.

Abstract: Architectures and circuits are described for various implementations of a memory-centric computing system for DSP and other compute-intensive applications. A shared, reconfigurable memory system is accessible to both a host processor or controller and to one or more execution units such as a DSP execution unit. By swapping memory space between the processor and the execution unit so as to support continuous execution and I/O, improved performance is achieved while cost is reduced. The shared memory system includes multiple reconfigurable memory segments to allow allocation of various amounts of memory to respective execution units or I/O or DMA channels as needed to optimize performance. A "virtual two-port" solution also is described for using single-port memory in the shared configuration with multiple address sources.

Abstract: Some virtual memory systems allow more that one memory page size. To quickly translate virtual page addresses into physical page addresses, a multi-page size translation look-aside buffer is needed. The multi-page size translation look-aside buffer has a virtual address array and a physical address array. The virtual address array has a set of virtual address entries that are compared to a received virtual address. The virtual address array entries have virtual address tag field, a valid bit, and a page size bit. The page size bit defines the size of the memory page and thus defines the number of bits in the virtual address that must be matched with virtual address tag bits in the virtual address array. The valid bit indicates if the entry is valid or not. When a hit is detected in the virtual address array, a corresponding entry in the physical address array is activated. The physical address array comprises a physical page address and a set of page attributes.

Abstract: A multiple bus master computer system employs an interface to a central processor allowing external bus masters to query the central processor with addresses and to receive back translated addresses. A first preferred embodiment employs two signals namely: translation request and translation address strobe to request/acknowledge the request for translation. The translation request is maintained asserted by one of the alternative bus masters until the central processor acknowledges it--at which time the alternative bus master drives an address (for example a virtual address) onto the address bus for translation. The central processor then translates the virtual address to its corresponding physical address (doing any page table walking or page faulting) and drives this physical address out on the address lines and asserts another translation address strobe.

Abstract: A processor and method of processing a multiple-register instruction are described. The processor includes execution circuitry and a set of registers, which are each capable of storing a data word. A multiple-register instruction specifying a plurality of data words that are to be written to a corresponding plurality of registers within the set of registers is dispatched to the execution circuitry. In response to receipt of the multiple-register instruction, the execution circuitry executes the multiple-register instruction, such that at least two data words among the plurality of data words are written to at least two corresponding registers among the plurality of registers during a single cycle of the processor.

Abstract: A buffer memory controller allows to sequentially store sampled data having variable bit length. That is, rather than assigning each sampled data to a single word of the memory, the sampled data is sequentially stored head to tail so that memory space is not wasted.

Abstract: An apparatus and method of efficiently and dynamically generating the addresses associated with a set of instructions in a microprocessor pipeline is disclosed. Program counter age bits associated with the offsets of an address of a predetermined instruction within a set of instructions are used to indicate the chronological age of each instruction within the set of instructions. The age bits are generated by a logic circuit which also dispatches instructions to various execution units. The age bits are used to maintain and track the addresses of an instruction stream within a processing system so that there is no need to store the addresses of each and every instruction.

Abstract: A bridge logic takes non-burst write cycles that appear one at a time as an address followed by an associated data word on a first bus, detects consecutive addresses, and uses this information to create burst cycles on a second bus that has protocols that allow burst cycles such as a Peripheral Component Interconnect (PCI) bus.

Abstract: A memory control device having a memory for reading out and holding managing data from a recording medium is equipped with a memory controller for outputting write-in/read-out addresses through an address generating circuit and receiving write-in/read-out data, and a system controller for controlling the memory controller to execute the data write-in/read-out operation on the memory. When link data in the managing information is supplied from the system controller or obtained from the data read in from the memory, an address to be next accessed on the basis of the link data is calculated and the calculated address is output to the memory.

Abstract: A method and device for generating address aliases corresponding to memory locations, for avoiding false load/store collisions during memory disambiguation. The alias generator takes advantage of the fact that the entire address range will most likely not be active in the registers at any one time. The subset of the address range that is active can be represented with a smaller number of bits and, hence, the computation of true dependencies is greatly reduced. The address alias generator includes an array for receiving the memory addresses, comparators having inputs connected to each array entry and having outputs connected to an alias encoder, and a control logic unit for writing the given memory address in one of the entries. The output of a given gate is turned on if a memory address is the same as the contents of one of the entry corresponding to that output, and the control means is activated if the output of all of the gates are turned off.

Abstract: A computer system having a bridge and I.sup.2 C EEPROMs is provided with a host I.sup.2 C controller implemented in the bridge for accelerating the reading of the I.sup.2 C EEPROMs. The host I.sup.2 C controller accelerates the reading of I.sup.2 C EEPROMs by executing current address reads of the I.sup.2 C EEPROM when a requested slave address matches a current slave address stored in a current slave address register, and the requested EEPROM address matches a current EEPROM address stored in a current EEPROM address counter. The host I.sup.2 C controller thus eliminates the use of software to track the read accesses of a plurality of masters to an I.sup.2 C EEPROM and also eliminates the use of bus command protocols to support both random reads and current address reads to an I.sup.2 C EEPROM.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: A high speed bus system in which at least one master device, such as a processor and at least one DRAM slave device are coupled to the bus. An innovative packet format and device interface which utilizes a plurality of time and space saving features in order to decrease the die size of the device receiver and decrease the overall latency on the bus is provided. In the preferred embodiment the request packet is transmitted on ten multiplexed transmission lines, identified as BusCtl and BusData. The packet is transmitted over six sequential bus cycles, wherein during each bus cycle, a different portion of the packet is transmitted. The lower order address bits are moved ahead of the higher order address bits of the memory request. This enables the receiving device to process the memory request faster as the locality of the memory reference with respect to previous references can be immediately determined and page mode accesses on the DRAM can be initiated as quickly as possible.

Abstract: A microprocessor system integrated on a chip having one or more address generation devices, at least one memory location, and at least one peripheral unit. The address path is divided into two portions having a first logic unit conditioning the address from the one or more address generation devices on the first portion of the address path for gating onto the second portion of the address path. The first logic unit converts a single 16 bit address location into two 8 bit address locations. The first logic unit maintains a first address on the second address path when the CPU is in a next address pipeline mode. A second logic unit selects a memory architecture so that the system can address DRAM units having a various number of rows and/or columns.

Abstract: A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched.

Abstract: The present invention provides a method and apparatus for storing additional information, such as HOLE information, within a buffer while minimizing the overhead.A method according to the present invention for efficiently storing additional information in a memory, the memory including at least one address, the memory for storing at least a portion of a packet to be transferred by a network system, the method comprising the steps of determining whether the at least a portion of a packet ends at a boundary of the at least one address; encoding a portion of the packet to indicate that the packet ends at the address boundary if the packet ends at the address boundary; and encoding a portion of the at least one address to indicate that the packet does not end at the address boundary, if the packet does not end at the address boundary.

Abstract: A method and system for storing file system state information within sectors of the file system. File system information includes pointers to top-level file system structures, such as free space bitmaps, a bad block list, a directory block band, and a root directory. The system classifies the file system state information into two groups: frequently-updated information and infrequently-updated information. The two groups are stored on separate sectors. Thus, the frequently updated information can be updated without rewriting the infrequently updated information. Because the infrequently updated information is not rewritten, the risk of this information being corrupted is significantly reduced.

Abstract: A tag memory circuit includes an address index input, an address offset input and an integrated adder and pre-decode circuit. The integrated adder and pre-decode circuit has a first addend input coupled to the address index input, a second addend input coupled to the address offset input, and a pre-decoded sum output. A final row decode and word line driver circuit is coupled to the pre-decoded sum output and generates a word line output which is coupled to the address inputs of a tag memory array. The data outputs of the tag memory array are coupled to a sense amplifier.

Abstract: A DMA controlling device is provided.

Abstract: An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a semiconductor device under test during a test process in real time and generates column addresses for the device under test by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, Z address signal, and an operation mode control signal is arranged, a conversion memory that outputs certain conversion table contents is arranged, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with the burst length control signal.