Abstract: An address operation circuit generates a row address which indicates an address in memory under test to be accessed. The row address memory stores the row addresses generated by the address operation circuit in increments of banks. A memory control signal that includes a bank address to be applied to the memory under test, and which is generated according to a pattern program, is used as a save address to be used to write the row address to the row address memory, and as a load address to be used to read out the row address from the row address memory.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

Abstract: A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit.

Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

Abstract: A system for testing electronic circuits is configured to receive a test signal and an ideal response signal and output a test result signal. The system for testing electronic circuits includes a circuit portion to be tested, a comparator and a comparison result recorder. The circuit portion to be tested receives a test signal from a test instrument, and outputs a system response signal. The comparator receives the system response signal from the circuit portion to be tested and receives an ideal response signal from the test instrument. Then, the comparator outputs a comparison result according to the system response signal and the ideal response signal. The comparison result recorder receives and records the comparison result. The comparison result recorder may record comparison results within a period of test time. The test instrument can obtain a record of the comparison results from the comparison result recorder.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

Abstract: Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test pattern 100a given in advance for a logic circuit into an intermediate test pattern 100b of a bit constitution of different logic values, where the constitution elements of the initial test pattern 100a are at least two test vectors applied in succession. The conversion device includes a decision means for deciding a combination of logic values in the initial test pattern 100a which meet a detection condition of faults of the logic circuit which can be detected by applying the constitution elements.

Abstract: A semiconductor inspecting apparatus includes: a buffer memory whose width is matched to the greater of parallel bus width and the width of the number of serial lanes; a preceding stage bus switching unit that fills the buffer memory with input data without making a free space; equivalent transmission capacity conversion including a following stage bus switching unit that fills read data to the width of an arbitrary number of serial lanes without making a free space; a preceding stage bus switching unit that fills a buffer memory with input data without making a free space; and equivalent transmission capacity inverse conversion including a following stage bus switching unit that fills a parallel bus of arbitrary width with data read from a buffer memory without making a free space.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.

Abstract: A data transformation method for a testing system includes using a reception end for receiving a test signal comprising a test data and a timing information corresponding to the test data, and using a transformation unit for transforming the test data according to the timing information, so as to generate a test pattern utilized for testing a communication device.

Abstract: A semiconductor memory device including a plurality of banks, each including a plurality of memory cells, a pattern signal generator configured to generate pattern signals having combinations in response to an input signal applied through an arbitrary pad in a compression test mode. Input paths are configured to transfer the plurality of pattern signals to the corresponding banks.

Abstract: Facilitating assessment of a test suite of a software product. In an embodiment, an inventory is maintained containing the features of the software product and one or more execution flows operative when a feature is provided by the software product. Information related to execution flows for which test scripts are present (in the test suite) is also indicated in the inventory. Various test metrics and views are provided to a user facilitating the user to assess the test suite of the software product.

Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

Abstract: Functional coverage techniques during design verification using cross-product coverage models and hole analysis are enhanced by the use of coverage queries. After running a test suite, a core set of non-covered events is specified. A coverage query is then automatically constructed and executed on the test results to identify a hole in the functional coverage that satisfies conditions of the coverage query and includes the core set. The results of the query are presented as a simplified view of the coverage of the events in the cross-product space. Use of coverage queries allows a verification team to focus on specific areas of interest in the coverage space and to deal practically with highly complex coverage models. It also avoids the burden of producing and evaluating complete hole analysis reports.

Abstract: A method for generating reliability tests for a telephone system is based upon sampling an orthogonal array which covers various combinations of test parameters. Field data is collected of actual telephone activity on a telephone system. The field data is evaluated so as to determine call-mix characteristics. Probabilistic weights for the different call-mix characteristics are obtained, and then the probabilistic weights are used to sample the test case scenarios generated in the orthogonal array which have the same call-mix characteristics. These test case scenarios are used to run tests on the telephone system. These tests are preferably performed using automated test scripts. After the test data is collected, reliability metrics are calculated from the test data.

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

Abstract: A testing module including a designation information storing section that stores designation information designating an order of decoding fundamental patterns, a fundamental pattern storing section that stores the fundamental patterns, a plurality of pattern generating sections that each generate a test pattern to be supplied to a device under test, a plurality of position information storing sections that each store, in association with a corresponding pattern generating section, position information designating a read position from which the designation information is read from the designation information storing section, and an information transmission path shared by the pattern generating sections that transmits a part of the designation information from the designation information storing section to the designation information temporary storing section in each pattern generating section.

Abstract: A method for injecting timing irregularities into test patterns self-generated by a device under test (DUT) includes obtaining timing irregularities, receiving the test patterns generated by the device under test driven from output drivers of the DUT, injecting the timing irregularities into the test patterns to generate test patterns with timing irregularities injected therein, and applying the test patterns with timing irregularities injected therein to input receivers of the DUT. A tester is configured to test loopback functionality of a device under test (DUT) utilizing a timing irregularities injection apparatus which receives timing irregularity data readable by the tester and test data generated by the DUT, and injects the timing irregularity data into the test data for application to the DUT.

Abstract: Provided are a generation device and the like for generating a new vector whose volume can be reduced rapidly when an output pattern derived from a decompressor of a logic circuit under test includes an unspecified bit in relation to the logic circuit under test. The output pattern includes unspecified bits. In step SS1, classification unit classifies the unspecified bits and determines if an unspecified bit is an implied bit or not. The implied bit is an unspecified bit if its value is a logic value determined as logic value 0 or 1 relating to logic bits in the initial vector and according to a predetermined condition (such as compressibility) among bits in the initial vector derived from the upstream logic circuit 1. In step SS1, the unspecified bits which are not implied bits are classified as free bits. The classification unit classifies free bit sets in step SS2, and further classifies free bits to identify compatible free bit sets.

Abstract: A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is provided for: storing test patterns, a description of integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.

Abstract: An apparatus for generating a digital signal pattern may comprises a memory, a program sequencer, first and second circuits, and an event execution unit. The memory may have stored therein a plurality of instructions that, when executed, cause a digital signal pattern to be generated on a plurality of nodes. The program sequencer may be configured to control a sequence in which the plurality of instructions are retrieved from the memory and executed. The first circuit may sequentially step through a plurality of different output states in response to a clock signal. The second circuit may identify an output event when an output state of the first circuit corresponds to an output state identified by retrieved instructions of a particular type. The event execution unit may control states of signals on the plurality of nodes in a manner specified by the retrieved instructions of the particular type in response to the second circuit identifying an output event.

Abstract: A receive test accelerator retrieves an adjusted jitter amount and an adjusted test time in which to test a device. The adjusted jitter amount and the adjusted test time correspond to an adjusted bit error rate that is extrapolated from a baseline bit error rate, which corresponds to a baseline jitter amount. In turn, the receive test accelerator tests the device, at the adjusted test time, using a data stream that is modulated by the adjusted jitter amount.

Abstract: A method comprises generating a test pattern for a device under test (DUT), wherein the DUT comprises a plurality of scan chains coupled to a plurality of multiple input shift registers (MISRs). The plurality of faults detected by a first MISR and by a second MISR are identified. In the event the plurality of faults detected by the first MISR does not include any of the plurality of faults detected by the second MISR and the plurality of faults detected by the second MISR does not include any of the plurality of faults detected by the first MISR, the first MISR and the second MISR are coupled as an independent MISR pair. The test pattern is applied to the DUT to generate a scan chain output. The independent MISR pair captures the scan chain output to generate a test signature. The test signature is compared with a known good signature.

Abstract: The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal. Additionally, in other embodiments, the timing signal associated with various DUTs is used as a timing reference for other devices.

Abstract: A test pattern generation method for determining if a combinational portion 17 is defective, by applying test patterns to a semiconductor integrated circuit 10 and comparing responses to the test patterns with expected responses, the method including: a first step of generating test patterns having logic bits for detecting defects and unspecified bits; a second step of selecting critical paths 19, 19a, 19b generated by the application of the test patterns; a third step of identifying critical gates on the critical paths 19, 19a, 19b; and a fourth step of determining unspecified bits so that a critical capture transition metric, which indicates the number of the critical gates whose states are changed, is reduced; wherein by reducing the critical capture transition metric, output delays from the critical paths 19, 19a, 19b are prevented, and thereby false testing can be avoided.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment. In order to do so, the testing interface includes components configured for generating addresses, commands, and test data to be conveyed to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent. The systems are optionally configured to include a test plan memory component configured to store one or more test plans. A test plan may include a sequence of test patterns and/or conditional branches whereby the tests to be performed next are dependent on the results of the preceding tests. The test plan memory is, optionally, be detachable from the test module.

Abstract: A method for generating a multi-frame image rendering of a challenge-response test on a display is presented. The method begins by identifying a pattern with graphical elements, and a display region for rendering an entry object of the multi-frame image of the challenge-response test. Then a foreground sampling window having a non-patterned area defined by the entry object is defined. The foreground sampling window captures graphical elements of the pattern along a first path. In addition, a background sampling window that captures graphical elements of the pattern along a second path is defined. The foreground sampling window is overlaid on the background sampling window at the display region of the display, such that the entry object of the challenge-response test is discernable from the pattern during a period of time when multiple frames are rendered.

Abstract: A semiconductor memory device includes: a pattern selector configured to receive a first test control signal and a second test control signal to output a plurality of pattern selection signals and a selection end signal in response to an entry signal; a shifting controller configured to receive the first test control signal and the second test control signal to output a shifting control signal in response to the selection end signal; and a pattern test signal generator configured to select a stress pattern corresponding to the pattern selection signals to generate a plurality of test mode signals for controlling a sequential entry into a plurality of test modes for executing the stress pattern in response to the shifting control signal.

Abstract: Provided is a test apparatus that tests a device under test, including a vector expanding section that sequentially generates a plurality of test vectors; a vector selecting section that selects test vectors that cause a prescribed characteristic of the device under test, which is to be measured when test signals that are each based on one of the test vectors are supplied to the device under test, to fulfill a preset condition; and a judging section that judges pass/fail of the device under test based on measured values of the prescribed characteristic of the device under test supplied with the test signal based on the test vectors selected by the vector selecting section.

Abstract: Logic circuitry has a test point to detect a signal about a delay fault propagating on a logic path between an input terminal and an output terminal, the test point being coupled to the logic path, wherein the test point includes a delay component to delay timing to detect the signal about a delay fault propagating on the logic path by predetermined time.

Abstract: Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

Abstract: Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation device 100 generates a test vector for a logic circuit by assigning logic values to each of a plurality of unspecified bits (X-bits) included in a test cube.

Abstract: A test system for performing a test of a device is provided that comprises a source file of a test plan that describes a program for performing a test, and one or more of elements that are formed in a unit that divides the source file into one or more blocks. The test system further comprises an annotatable object that, when debugging of objects of the source file is performed, manages modification details of the debugging with reference to an element corresponding to a portion where the debugging is performed, and a controller that, after the debugging, rewrites the source file with details after the debugging is performed on an element basis based on the element and the annotatable object.

Abstract: A system comprises a decompressor that receives an input test vector and generates an output vector in response to the input test vector. A decoder couples to the decompressor and comprises a reset pattern detector (RPD), a lookup table, and control logic. RPD scans the output vector to identify a predetermined reset pattern. The control logic couples to the RPD and the lookup table and directs operation of the lookup table in a first or second mode based on whether the output vector comprises the predetermined reset pattern, as identified by the RPD. The lookup table receives the output vector, to operate in the first mode, storing one of a plurality of codeword sets, each codeword set comprising a plurality of pairs of codewords and associated data; and to operate in the second mode, generating test data blocks in response to identified codewords in the output vector.

Abstract: Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device converts a test vector set corresponding to the full scan sequential circuit. The conversion device comprises a setting unit for setting a candidate bit which can be a don't care bit and a fixed bit which cannot be the don't care bit according to predetermined constraint conditions based on an input-output relationship in the logic circuit in order to identify the don't care bit identifiable as don't care from each test vector of the test vector set, and a logic value deciding unit for deciding a logic value for the don't care bit in view of a relationship in a plurality of bit pairs in relation to a test cube including the don't care bit identified by the setting unit.

Abstract: A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatus 200 generating an initial test vector set 216 for a logic circuit includes a target vector identification unit 204 identifying a test vector satisfying a predetermined criterion and to be selected for the number of bits (the number of bit transitions) whose logic values differ before and after scan capture with respect to outputs from scan cells included in the sequential circuit, from among test vectors in the initial test vector set 216, and a test vector set conversion unit 206 converting the test vector identified by the test vector identification unit 204 and to be selected so as to reduce the number of bit transitions with respect to outputs from the scan cells included in the sequential circuit.

Abstract: A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled.

Abstract: To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.

Abstract: A single-pass, concurrent validation method for generating test pattern sequences for sequential circuits maps fault objects arriving at circuit next-state lines into good next-state fault objects, and passes these mapped results to a next time-frame by placing the good next-state fault objects on present-state lines corresponding to the next-state lines at which to fault objects arrived. Path-enabling functions created during an initial time-frame are reused for all subsequent time-frames, permitting a fault-propagation size and a path-enabling function size to be bounded by a function size established during the initial time-frame. A valid test pattern sequence is found when a primary output line has a good output level that is a complement of a faulty output level for the line. In one embodiment, the determination and comparison of output levels is carried out concurrently.

Abstract: Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group. A second group of applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and may be utilized in a variety of integrated circuits, such as an SLDRAM.

Abstract: A shift amount measuring apparatus for measuring a phase shift amount of a signal under measurement which is input thereto includes a PLL circuit that generates a strobe signal which is synchronized with a reference signal, a CDR circuit that inputs, into the PLL circuit, a control signal which has a level determined in accordance with a difference in phase between the signal under measurement and the strobe signal, so as to achieve a predetermined difference in phase between the signal under measurement and the strobe signal, and a measuring circuit that, before and after the signal under measurement is phase-shifted, measures a value of the control signal when the predetermined difference in phase is achieved between the signal under measurement and the strobe signal, and calculates the phase shift amount of the signal under measurement based on a difference between the measured levels of the control signal.

Abstract: Test entry circuit and method for generating test entry signal including a first source signal generator configured to receive a test signal through a pad to generate a first mode source signal for a first test mode, a second source signal generator configured to count activation transitions of the test signal to generate a second mode source signal for a second test mode and an entry signal generator configured to receive the first and second mode source signals to generate a first test mode entry signal for entering the first test mode and a second test mode entry signal for entering the second test mode.

Abstract: An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set of transactors sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.

Abstract: A system that provides large instruction sets for testing memory yet reduces area overhead is disclosed. The system for testing a memory of an integrated circuit comprises a set of registers providing element based programmability for a plurality of tests, wherein each test includes a plurality of test elements; a finite state machine for receiving a plurality of test instructions from the set of registers, wherein the finite state machine dispatches signals instructing a test pattern generator to generate a test pattern; a memory control module for applying the generated test pattern to the memory; and a comparator module for comparing a response received from the memory to a stored, known response.

Abstract: A method and system for testing an electronic device is disclosed. The method includes loading a first test into a test pattern generator of a first device and generating a first test pattern at the test pattern generator. A second test seed is loaded into the test pattern generator while the first test pattern is being generated. In one embodiment, the state of the test pattern generator is modified based upon the second test seed, and the first test seed.

Abstract: Provided is a test apparatus for testing a specimen by using a test pattern and an expected value pattern. The test apparatus includes: a control unit for outputting a test pattern to the specimen; a pattern converting unit for converting the expected value pattern based on an output pattern output from the specimen upon an input of the test pattern; and a determination unit for determining the specimen as a non-defective product or a defective product by using the converted expected value pattern.

Abstract: An input and/or output pad is dedicated to an integrated circuit comprising a core with input and/or output pins. This pad comprises a pad cell comprising a pad block connected to an input buffer and/or an output buffer and arranged to be connected to one of the core input and/or output pins. The pad also comprises a pad logic module comprising a first and/or a second boundary scan cell, connected to the pad block through the input buffer and/or output buffer and arranged to feed input signals to and/or deliver output signals from the pad block, and control means connected to the first and/or second boundary scan cell(s) and adapted to receive control signals for controlling access to the first and/or second boundary scan cell(s) and feeding the first boundary scan cell with the input signals and/or outputting the output signals delivered by the first boundary scan cell.

Abstract: A semiconductor device tester includes programmable hardware configured to test a semiconductor device under test. The programmable hardware is programmed with two or more pattern generators to control a flow of data to and from the semiconductor device under test.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.