Abstract: A controller comprises an error correction circuit configured to check an error bit number of error bits in the read data and correct the error bits; a read retry range setting circuit configured to reset a preset read retry range with respect to the read data, and set a new read retry range based on the error bit number and an error correction capability of the error correction circuit; a read voltage setting circuit configured to reset the set read voltage and set, as a new read voltage, a voltage among a plurality of voltages of the reset read retry range, corresponding to the new read retry range; and a flash control circuit configured to control the memory device to perform a read retry operation on the stored data, using the new read voltage.

Abstract: Some instances of a memory device include a memory die having an array of memory cells including a plurality of banks. In some cases, the memory die further includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. In some examples, the memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.

Abstract: A method for error correction and a system. The method may include opening a selected row of a memory bank out of multiple memory banks of a dynamic memory module; and while the selected row is open: (i) receiving selected data sub-blocks that are targeted to be written to the selected row, (ii) calculating selected error correction code sub-blocks that are related to the selected data sub-blocks, (iii) caching the selected error correction code sub-blocks in a cache memory that differs from the dynamic memory module and (iv) writing, to the selected row, the selected error correction code sub-blocks.

Abstract: The data storage system is a RAID-based data storage system in which resources are globally shared. This storage system includes the first number of disks, and the RAID mechanism is used to store data on each disk. The blocks on different disks form stripes, and at least one of the blocks on the stripe stores the parity information, wherein the width of the stripe is less than the first number. The data layout of the data storage system satisfies the following characteristics: any two physical blocks in the stripe are distributed on different disks; the data blocks distributed on each disk are the same, and the distributed parity blocks are also the same; other data in the stripe associated with any piece of disk data is evenly distributed across all the remaining disks. Normal data layout and degraded data layout can be implemented by orthogonal Latin squares.

Abstract: Calibrating read reference voltages is disclosed. In an aspect, a control die calibrates read reference voltages for reading the non-volatile memory cells. The control die is bonded to a memory die that contains memory cells. In one aspect, a tiered approach to calibrating read reference voltages is taken. For example, first the control die may attempt to determine new values for read reference voltages. If the new read reference voltages are satisfactory, then the control die may use the new read reference voltages. The control die could use one or more different techniques to determine new read reference voltages. If the new read reference voltages determined by the control die are unsatisfactory, then a memory controller in communication with the control die may calibrate the read reference voltages. By the control die determining the new read reference voltages, the memory controller is substantially less burdened with such tasks.

Abstract: Fault-tolerant error correction (EC) is desirable for performing large quantum computations. In this disclosure, example fault-tolerant EC protocols are disclosed that use flag circuits, which signal when errors resulting from ? faults have weight greater than ?. Also disclosed are general constructions for these circuits (also referred to as flag qubits) for measuring arbitrary weight stabilizers. The example flag EC protocol is applicable to stabilizer codes of arbitrary distance that satisfy a set of conditions and uses fewer qubits than other schemes, such as Shor, Steane and Knill error correction. Also disclosed are examples of infinite code families that satisfy these conditions and analyze the behaviour of distance-three and -five examples numerically. Using fewer resources than Shor EC, the example flag EC protocols can be used in low-overhead fault-tolerant EC protocols using large low density parity check quantum codes.

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). A circuit measures programming and reading temperatures for a set of memory cells in the NVM. Error rates are determined for each of the reading operations carried out upon the data stored in the memory cells. A code rate for the NVM is adjusted to maintain a selected error rate for the memory cells. The code rate is adjusted in relation to a cross-temperature differential (CTD) value exceeding a selected threshold. The code rate can include an inner code rate as a ratio of user data bits to the total number of user data bits and error correction code (ECC) bits in each code word written to the NVM, and/or an outer code rate as a strength or size of a parity value used to protect multiple code words.

Abstract: An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a page buffer/reading circuit 170 and a controller 150. The page buffer/reading circuit 170 includes a first latch circuit L1 and a second latch circuit L2. The first latch circuit L1 keeps data read from the memory cell array. The second latch circuit L2 keeps data transferred from the first latch circuit L1. Just after power is turned on or reset, the controller 150 controls data of block 0/page 0 of the memory cell array to be kept in the second latch circuit L2 and controls the SFDP data to be kept in the first latch circuit L1. The SFDP data or the data of block 0/page 0 is serially output according to an input command.

Abstract: A volatile memory device includes memory cells arranged on rows and columns; first counters each storing a count value representing a number of cells in which first data is stored among cells of a corresponding column, wherein the count value is updated or maintained whenever a write operation on each of the rows is performed; a calculator calculating a number of cells in which the first data is stored for each of the columns upon a determination that an EDC check on any one row among the rows fails, and determining a column in which a bit flip occurs by comparing the calculated number and the count value for each of the columns; and a control circuit determining that a cell of the row on which the EDC check fails among cells of the column in which the bit flip occurs is the bit-flipped cell.

Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach.

Abstract: Techniques are described in which network devices, such as one or more data center access nodes, are configured to support durable block storage with inline erasure coding, i.e., erasure coding in real time as data is updated. A Durable Block Device (DBD) supports a block level API for one or more storage volumes that may be mapped to one or more applications executed by servers in communication with the data center access nodes. The disclosure describes the operation of the data plane of the DBD that is hosted on one or more access nodes, and its interactions with the management and control planes of the DBD that are hosted on one or more of the servers. The disclosure describes generation of a log structured volume in the DBD configured to gather multiple data blocks into larger chunks of data for inline erasure coding for storage across multiple storage devices.

Abstract: A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a G matrix; transforming the G matrix into a systematic form, the transformed G matrix composed of a P matrix and a H matrix; sorting rows of the P matrix according to row weights; determining the number of rows in the P matrix to be truncated in view of a correcting strength and the number of data bits; generating a truncated P matrix by truncating the sorted rows of the P matrix that have a first row weights and keeping the sorted rows of the P matrix that have a second row weights; and forming the error correction circuit according to the truncated P matrix to correct the error of the codeword; wherein the first row weights are greater than the second row weights.

Abstract: Each of a plurality of distributed computing devices receives a respective data partition of a plurality of data partitions for a computing task. A first distributed computing device generates a first partial result of a plurality of partial results generated by the plurality of distributed computing devices. The first computing device iteratively executes a distributed average consensus (DAC) process. At each iteration, the first computing device transmits the first partial result to a second computing device, receives a second partial result generated by the second computing device, and updates the first partial result by computing an average of the first and second partial results. In response to determining that respective partial results of the plurality of distributed computing devices have reached a consensus value, the first computing device stops executing the DAC process, and generates a final result of the computing task based on the consensus value.

Abstract: A method begins by receiving a request for a move data function regarding a data object, where the data object is stored at a source DSN location in a first bucket of memory of the DSN. The move data function includes a target DSN location within a second bucket of the memory of the DSN. The method continues by determining dispersed storage error encoding parameters of the first and second buckets. When dispersed storage error encoding parameters of the first and second buckets substantially match, the method continues by creating new metadata, regarding the data object being stored at the target DSN location, that includes a logical address to logical address mapping such that the target DSN location points to the source DSN location and the data object is not physically present at a physical address space that corresponds to the target DSN location.

Abstract: A memory system includes a storage unit configured to include a plurality of memory blocks, a controller configured to read data from the memory block and to determine disturbance risk for the memory block, and a buffer memory unit configured to store the data read from the memory block and to provide the data to a host, wherein the controller is configured to control the buffer memory unit, in which the data read from the memory block is stored, based on the disturbance risk for the memory block.

Abstract: Systems, methods, and non-transitory computer-readable media can receive a plurality of web templates associated with a web page. A buffer having a fixed, pre-determined length is allocated. A first set of data associated with a first web template of the plurality of web templates is copied to the buffer. A second set of data associated with a second web template of the plurality of web templates is copied to the buffer.

Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.

Abstract: A memory system that includes an error check and correct (ECC) circuit is provided. The memory system includes a memory, a circuit, and a processor. The memory system has a function of receiving write data from the outside. The memory includes a user data region, a first management region, and a second management region. The user data region stores the write data. The circuit has a function of performing ECC processings on the write data read from the user data region. The first management region stores data that indicates whether the user data region has stored the write data or not. The second management region stores data that indicates whether the circuit has performed the ECC processings on the write data read from the user data region or not.

Abstract: A computing device for use in a dispersed storage network (DSN) to recover corrupt encoded data slices. The computing device requests, from storage units of the DSN, encoded data slices corresponding to a data segment. In response, the computing device receives at least a decode threshold number of encoded data slices and at least one integrity error message that provides an indication of a corrupt encoded data slice, such that less than a decoded threshold number of valid slices is received. Utilizing at least one correction approach, which may involve stored integrity data, the computing device corrects the corrupt slice(s) to produce a decode threshold number of encoded data slices in order to decode the corresponding data segment. A variety of correction approaches may be employed, including a multi-stage approach that utilizes data from both valid and invalid slices.

Abstract: Provided are an apparatus, memory device, and method to determine error location polynomial coefficients to provide to bit correction logic instances to decode bits of a codeword. A memory controller for a memory includes coefficient generating logic to receive as input a plurality of syndrome values to generate a plurality of coefficients for an error locator polynomial. A plurality of instances of bit correction logic, one instance for each bit of bits to correct in a codeword for a block in the memory array to decode. Each instance of bit correction logic is to receive as input the coefficients for the error locator polynomial and elements for the bit to correct from a decoder alphabet to determine whether to correct the bit and output as a decoded bit the bit or a corrected bit to include in a decoded codeword.

Abstract: Techniques are disclosed relating to detecting potential malware. A computer system may access process information identifying a set of software modules stored in a memory space allocated for a computer process. The computer system may determine address ranges that are respectively associated with a software module and define a segment in the memory space where program instructions are stored corresponding to that software module. The computer system may access thread information specifying, for each of a set of threads, a start address that identifies a location from which an initial program instruction is to be retrieved to begin execution of that thread. The computer system may make a determination that a thread is associated with a start address identifying a location outside of all address ranges, but within the memory space. Based on the determination, the computer system may classify the thread as being associated with malicious activity.

Abstract: Storage space may be allocated from a non-reserved zone of a file system when the file system is not undergoing an online file system check. When the file system is undergoing an online file system check, storage space is allocated from a soft-reserved zone.

Abstract: Apparatus and method including a probabilistic compute element for analyzing measured quantum values and responsively adjusting error correction parameters. For example, one embodiment of an apparatus comprises: a quantum controller to generate physical pulses directed to qubits on a quantum processor in response to operations specified in a quantum runtime; quantum measurement circuitry to measure quantum values associated with the qubits following completion of at least a first cycle of quantum runtime operations; and a probabilistic compute engine to analyze the one or more quantum values using inferencing and to responsively adjust a quantum error correction depth value for minimizing a number of errors to be detected on subsequent cycles of the quantum runtime.

Abstract: Techniques provide for data rebuilding in a storage system. The techniques involve: in response to failure of a first disk in the storage system, determining a second disk having a high risk of failure in the storage system; determining whether the second disk contains a second data block that is associated with a first data block to be rebuilt in the first disk, the first and second data blocks being from a same data stripe in the storage system; and in response to determining that the second disk contains the second data block and the second data block has not yet been replicated into a third disk for backup in the storage system, reading the second data block from the second disk to rebuild the first data block, and replicating the read second data block into the third disk.

Abstract: A memory system including a nonvolatile memory (NVM) device and a controller is provided. The NVM device includes a main region and a spare region. The controller writes write data to a selected row of the main region, determines whether the written row is bad, and writes the write data to a spare address in the spare region and writes the spare address to the bad row, when the written row is determined to be bad.

Abstract: A memory system in an embodiment includes a nonvolatile memory and a memory controller. The memory stores a multi-dimensional error correction code including at least one symbol that is capable of being protected by at least a first and a second component code. The controller reads the error correction code from the memory, executes hard decision decoding of the first component code with respect to the read error correction code and outputs a first decoding result and index information for calculating likelihood of the first decoding result, executes, when the hard decision decoding fails, soft decision decoding of the second component code by using the first decoding result and the index information and outputs a decoding result as a hard bit, and, executes, when the soft decision decoding fails, the hard decision decoding with respect to the result of the soft decision decoding output.

Abstract: Soft read suspend schemes for a memory system reduce overall command latency and improve QoS of the memory system, which includes a memory device and a memory controller. The memory controller controls the memory device to perform, in response to a command, a hard read to generate hard information for hard decoding, and predict whether soft decoding of the data is to be performed, and if so, how many soft reads are to be performed. When hard decoding fails and soft decoding and at least one soft read is to be performed, the memory device is controlled to perform an initial soft read to generate soft information for soft decoding, predict whether, and if so, how many, subsequent soft reads are to be performed, and determine whether to perform a first subsequent soft read on the data based on the prediction.

Abstract: A method includes dispersed storage error encoding, by a computing device of a dispersed storage network (DSN), a plurality of data segments to produce a plurality of sets of encoded data slices. The method further includes obfuscating a first set of encoded data slices of the plurality of sets of encoded data slices using a first obfuscating method to produce a first set of obfuscated encoded data slices. The method further includes obfuscating a second set of encoded data slices of the plurality of sets of encoded data slices using a second obfuscating method to produce a second set of obfuscated encoded data slices. The method further includes outputting the first and second sets of obfuscated encoded data slices for storage.

Abstract: Technology is generally described for automating the project management and execution of data migration from a source email system to a destination email system. In some examples, the technology can include receiving a domain name of a second computing system; obtaining domain name system (DNS) records for the received domain name; determining an email hosting provider for the second computing system; determining, by the processor, based on the obtained DNS records, an email system service type of the source email system on the second computing system; discovering mailboxes and message delivery rules of the source email system; displaying customization options for migrating discovered source email system mailboxes; migrating data items from the source email system to the destination email system; and managing migration of data from source email system client computing devices to the destination email system.

Abstract: A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.

Abstract: The present invention provides a method and system for enabling machine type communication in a long term evolution (LTE) network environment. In one embodiment, a Physical (PHY) layer of a LTE protocol stack maps data bits in resource elements of a logical channel to resource elements of a physical channel. The PHY layer identifies the data bits intended for legacy devices but mapped to a first set of resource elements of machine type communication (MTC) devices and the data bits intended for the MTC device but mapped to the second set of resource elements of the legacy devices. Accordingly, the PHY layer remaps the data bits intended for the legacy devices to the second set of resource elements and the data bits intended for the MTC devices to the first set of resource elements prior to transmission.

Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, comprising: continuously monitoring data frames and/or control frames from a second side; and triggering a TX (transmission) data rate adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects errors from received data.

Abstract: A method includes receiving, by a computing entity of a dispersed storage network (DSN), a request from a requesting device of the DSN to perform an encoded data slice operation. The request includes an indication that the encoded data slice operation is a stage in a predefined DSN workflow. The method further includes sending, by the computing entity, a response to the requesting device that includes a DSN workflow tag, wherein the DSN workflow tag includes an identifier of the stage in the predefined DSN workflow. The method further includes enabling a performance optimization mode. The performance optimization mode includes one or more performance optimization procedures for one or more of: the stage and one or more future stages of the predefined DSN workflow. The method further includes executing the encoded data slice operation in accordance with the performance optimization mode.

Abstract: The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom portion, a datum being copied from the bottom portion to the top portion for processing by the application. The computer is adapted to interrupt the execution of the main application. Upon an interruption in the execution of said application, a reference to a datum stored in a top portion of the memory is stored, wherein said datum must be used in order to enable the execution of the application. After programming a resumption of the execution of the application and before the resumption thereof, said datum is accessed in a bottom portion of the memory in accordance with the reference to be stored in a top portion of the memory.

Abstract: A set of quantum assembly language referencing a quantum algorithm is received from a user. A quantum device is selected to execute the set of quantum assembly language. Responsive to the selected quantum device, an implementation of the quantum algorithm from a remote repository is selected, the remote repository comprising a set of implementations of a set of quantum algorithms. An implementation in the set of implementations in the remote repository is compiled to form a compiled quantum circuit. The compiled quantum circuit is transformed into a quantum circuit model. Using the selected quantum device, the quantum circuit model is executed.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing blockchain data. One of the methods includes receiving a request from a blockchain node of the blockchain network to execute one or more software instructions in a trusted execution environment (TEE). One or more blocks infrequently accessed for executing the one or more software instructions are determined. Error correction coding of the one or more blocks in the TEE is performed to generate one or more encoded blocks. Each of the one or more encoded blocks are divided into a plurality of datasets based on the one or more software instructions. The plurality of datasets and a data storage arrangement are sent to blockchain network nodes, where the data storage arrangement indicates at least one of the plurality of datasets to be stored by each of the blockchain nodes.

Abstract: An example multi-master system in a system-on-chip (SoC) includes a plurality of master circuits, an error-correcting code (ECC) proxy bridge comprising hardened circuitry in the SoC, a local interconnect configured to couple the plurality of master circuits to the ECC proxy bridge, a memory not having ECC support, and a system interconnect configured to couple the ECC proxy bridge to the memory. The ECC proxy bridge is configured to establish an ECC proxy region in the memory and, for each write transaction from the plurality of master circuits that targets the ECC proxy region, calculate and insert ECC bytes into the respective write transaction.

Abstract: The present invention discloses a unidirectional bit error correction method for a OTP ROM, comprising: applying error correction encoding to bit information and writing the bit information to the OTP ROM; during power-up initialization, converting hard bit information read out from the OTP ROM to soft bit information; during the power-up initialization, performing error correction decoding through a soft bit decoder. The advantages of the present invention include: utilizing otherwise temporarily idle decoding modules in the chip, without requiring additional hardware resource, while providing stronger error correction capability to the OTP ROM, improving the stability of chip applications, prolonging chip service life, and significantly reducing rejection rate in chip production.

Abstract: A memory cell can have a state in a valley between adjacent data states. A determination can be made whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.

Abstract: In one embodiment, an apparatus comprises a controller comprising circuitry, the controller to generate an error correction code for a memory line, the memory line comprising a plurality of first data blocks, wherein the error correction code comprises parity bits generated based on first portions of a plurality of second data blocks, wherein the plurality of second data blocks are the first data blocks or diffused data blocks generated from the plurality of first data blocks; generate a metadata block corresponding to the memory line, wherein the metadata block comprises the error correction code for the memory line and at least one metadata bit; encode the first data blocks and the metadata block; and provide the encoded data blocks and the encoded metadata block for storage on a memory module.

Abstract: Power consumption of a semiconductor device is reduced. A semiconductor device according to an embodiment includes a plurality of circuits, a bus circuit including a plurality of buffers that temporarily store communication data between the circuits and a plurality of arbitration circuits that arbitrate an access between the circuits and the buffers, a storage unit that stores information based on a use state of the buffers during communication between the circuits and configuration information including designation of unused circuits that are not used for the communication from among the circuits, and a control circuit that controls the bus circuit so as to stop use of unused buffers that are not used for the communication from among the buffers and at least a partial configuration in arbitration circuits corresponding to the unused circuits from among the arbitration circuits based on the configuration information.

Abstract: A method for analyzing a potential data breach is disclosed. In one embodiment, such a method includes identifying a time frame and data store in which a data breach potentially occurred. The method reconstructs the data store to a point in time near an end of the time frame. The method then repeatedly performs the following until the data store reaches a point in time near a beginning of the time frame: revert to a previous version of the data store by removing an incremental update to the data store; record changes to the data store caused by removing the incremental update; and record timestamps associated with the changes. Once the data store reaches the point in time near the beginning of the time frame, the method creates a report that documents the changes and the timestamps and provides the report to a user. A corresponding system and computer program product are also disclosed.

Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.

Abstract: A method of decoding data stored in non-volatile memory in which each memory cell stores data by adopting one of a plurality of storage states.

Abstract: A load control device is able to receive radio-frequency (RF) signals from a Wi-Fi-enabled device, such as a smart phone, via a wireless local area network. The load control device comprises a controllably conductive device adapted to be coupled in series between an AC power source and an electrical load, a controller for rendering the controllably conductive device conductive and non-conductive, and a Wi-Fi module operable to receive the RF signals from the wireless network. The controller controls the controllably conductive device to adjust the power delivered to the load in response to the wireless signals received from the wireless network. The load control device may further comprise an optical module operable to receive an optical signal, such that the controller may obtain an IP address from the received optical signal and control the power delivered to the load in response to a wireless signal that includes the IP address.

Abstract: Several embodiments of systems incorporating memory sub-systems are disclosed herein. In one embodiment, a memory sub-system can include a memory component and a processing device configured to perform a background scan on a memory region of the memory component. In some embodiments, the background scan includes generating a bit error count (BEC) of a codeword saved on the memory region and saving statistical information corresponding to the BEC of the codeword to a histogram statistics log. In some embodiments, when the BEC of the codeword is greater than a BEC threshold, a refresh operation is scheduled for the memory region and/or logged. In these and other embodiments, when one or more error recovery error correction code (ECC) operations do not correct bit errors in the codeword, a refresh and/or retirement operation is schedule for the memory region and/or is logged.

Abstract: A memory system may include performing a first read operation on first data stored in first memory cells coupled to a first word line, performing an error correction operation on the first data, performing an interference program operation on second memory cells coupled to a second word line when the error correction operation fails, and performing a second read operation on the first data stored in the first memory cells after performing the interference program operation.

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

Abstract: An error correction method and a chip kill detection method of a memory including a plurality of chips may be provided. The method may include a first data error detection step of detecting whether an error exists in data outputted from the plurality of chips. The method may include a random error correction step of correcting an error occurred in data when it is detected in the first data error detection step that an error exists. The method may include a chip kill detection step of determining, when an error occurs even after the random error correction step, that a chip kill error has occurred, and detecting a chip where the chip kill error has occurred, by correcting the error through assuming one chip among the plurality of chips as a chip where the chip kill error has occurred.

Abstract: Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.