Abstract: A memory system includes a semiconductor memory device, a memory controller for controlling the semiconductor memory device, and a memory buffer connected between the semiconductor memory device and the memory controller. The memory buffer is configured to perform error correction coding (ECC) on first data that is received from the memory controller to be stored in the semiconductor memory device and to perform ECC on second data read from the semiconductor memory device.

Abstract: A memory system includes an error checking and correction (ECC) engine configured to perform error checking and correction of data temporarily stored in a first memory array and data read out from the first memory array according to a first method, and perform error checking and correction of data stored in a second memory array after read out from the first memory array and data read out from the second memory array according to a second method, wherein the first method and the second method are selected in response to a control signal having at least a first logic level, and the second method checks and corrects data errors occurring at a higher rate compared the first method.

Abstract: According to one embodiment, a data storage control apparatus includes an interface module and a controller. The interface module receives first data, in specific units, from a host and stores the data in a buffer memory. The controller generates second data from the first data stored in the buffer memory, and performs a control to write the second data to a nonvolatile storage medium. The controller generates the second data of a second format having the same size as the first format of the data stored in an ordinary recording area provided at the nonvolatile storage medium, and including a plurality of units of the first data and invalid data. The controller further performs a control to write the second data in a save area provided on the nonvolatile storage medium.

Abstract: There is provided a method of writing data to a data sector of a storage device. The data sector has at least one parity sector associated therewith, each sector being configured to include a data field and a data integrity field. The data integrity field including a guard field, an application field and a reference field. The method includes providing data to be written to an intended sector; generating, for the intended sector, version information for the sector; generating a version vector based on the version information for the data sector; and writing the data to the data field of the data sector; writing the version information to the application field of the data sector; and writing the version vector to the application field of the parity sector.

Abstract: According to example embodiments, a method of controlling a memory controller includes executing an error correction code (ECC) on first page data that has been read from a non-volatile memory device using a first read voltage level, estimating a second read voltage level for reading the first page data using metadata of second page data when an uncorrectable error is detected in the first page data according to a result of executing the ECC.

Abstract: Channel marking is provided in a memory system that includes a memory channel with a plurality of memory devices. The memory devices are arranged into a first group of memory devices and a second group of memory devices. The memory system is configured to perform a method that includes determining that more than a threshold number of memory devices in the first group are failing. An error correction code (ECC) is configured to compensate for errors associated with memory devices in the first group on the memory channel and to perform error correction on errors associated with memory devices in the second group on the memory channel.

Abstract: Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.

Abstract: Methods for error checking and correcting (ECC) in a memory module including at least one memory unit are provided. The method includes the steps of: receiving input data from the memory unit; performing, by a first ECC module, a first ECC operation to the input data and generating a decoding result which indicates whether decoding was successful; and determining whether to activate a second ECC module to perform a second ECC operation to the input data according to the decoding result, wherein the first and second ECC modules respectively utilize a first method and a second method, wherein the first method applies a ECC with a first fault tolerant quantity for error correction and the second method applies a ECC with a second fault tolerant quantity for error correction, and the second fault tolerant quantity is larger than the first fault tolerant quantity.

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Abstract: In one embodiment a variable barrel shifter includes a shifter operable to apply a cyclic shift to each of a number of portions of a data word, a pivot circuit operable to swap sections of the data word around at least one pivot point in the data word, a first multiplexer operable to select between an input of the variable barrel shifter or an output of the pivot circuit as an input to the shifter, a second multiplexer operable to select between the input of the variable barrel shifter or an output of the shifter as an input to the pivot circuit, and a third multiplexer operable to select between the output of the shifter or the output of the pivot circuit as an output to the variable barrel shifter.

Abstract: Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.

Abstract: A data handling system includes a compressive sensing unit that receives a source date file. A sparseness module compressive sensing unit generates a sparse source data file by inducing sparseness into the source data file. A measurement module within the compressive sensing unit generates a compressed sensed source data file from the sparse source data file and based on a sensing matrix. The compressed sensed source data file is to be transmitted to a remote data storage facility for storage. A recovery unit generates the source data file from the compressed sensed source data file retrieved from the remote data storage facility and based upon the sensing matrix.

Abstract: A storage controller includes an error correcting code managing portion, an address managing portion and an error correcting portion. The error correcting code managing portion manages a correspondence relationship between predetermined plural pieces of unit data, and a second error code corresponding to the plural pieces of unit data every entry when plural pieces of unit data and a second error correcting code are stored in a storage portion. The address managing portion manages a correspondence relationship between logical addresses and the entries in the error correcting code managing portion. The error correcting portion acquires the entry in the error correction managing portion corresponding to the logical address as an object of read from the address managing portion, and carries out error correction based on the plural pieces of unit data managed in the entry concerned, and the second error correcting code.

Abstract: An apparatus and associated method provided for a plurality of storage elements arranged and concurrently accessible in an array. A controller executes programming instructions stored in memory to append an error correction code (ECC) block to a first data block and to store the first data block with appended ECC block in a first storage element of the plurality, the appended ECC block associated with a second data block other than the first data block.

Abstract: Allocation process that allows erasure coded data to be stored on any of a plurality of disk drives, in a pool of drives, so that the allocation is not tied to a fixed group of drives. Still further, the encoded data can be generated by any of multiple different erasure coding algorithms, where again storage of the encoded data is not restricted to a single group of drives based on the erasure algorithm being utilized to encode the data. In another embodiment, the encoded data can be “stacked” (aligned) on select drives to reduce the number of head seeks required to access the data. As a result of these improvements, the system can dynamically determine which one of multiple erasure coding algorithms to utilize for a given incoming data block, without being tied to one particular algorithm and one particular group of storage devices as in the prior art.

Abstract: The present disclosure relates to a BCH encoding, decoding, and multi-stage decoding circuits and method, and an error correction circuit of a flash memory device using the same. The concatenated BCH multi-stage decoding circuit includes: a first stage encoding unit that receives a part or all of data input to a flash memory device, performs BCH encoding, and outputs a first output BCH code or a parity bit thereof; an interleaving unit that receives a part or all of data input to the flash memory device, interleaves, and outputs the data, and a second stage encoding unit that performs BCH encoding of the BCH code or data that is the output of the interleaving unit, and outputs a second output BCH code or a parity bit thereof.

Abstract: A memory controller provides low-latency error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to receive a memory access command that includes an address and a length associated with data that is to be transferred to or from the memory device, and transfer one or more bytes of data and one or more bytes of ECC information to or from locations of the memory device associated with the address and the length.

Abstract: A memory controller is disclosed, having a memory access circuit and an LDPC decoding circuit. The memory access circuit reads the hard information of a first code word and a second code word from a memory device. The LDPC decoding circuit decodes the first code word according to the hard information of the first code word. When the LDPC decoding circuit does not decode the first code word successfully, the LDPC decoding circuit configures the memory access circuit to read the soft information of the first code word and the second code word, and decodes the first code word and the second code word according to the soft information of the first code word and the second code word.

Abstract: A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault value to the stuck-at fault value. The control circuit is operable to generate encoded data bits by inverting each of the data bits having a different value than the stuck-at fault value of the corresponding one of the memory cells and by maintaining a digital value of each of the data bits having the stuck-at fault value of the corresponding one of the memory cells. The control circuit is operable to prevent any of the data bits from being stored in the memory cells determined to have unstable values. The control circuit is operable to generate redundant bits that indicate at least one operation to perform on the encoded data bits to regenerate the data bits.

Abstract: A nonvolatile memory device comprises a memory controller having a memory cell status estimator that generates status estimation information indicating the status of a memory cell based on status register data, a coupling group index selector configured to generate a select signal for selecting a page and coupling group index from the status estimation information, and a memory cell status value generator configured to map the status estimation information to the data reliability decision bits and the coupling group index and generate a status value of the memory cell for error correction code decoding.

Abstract: A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault to a value of the stuck-at fault, and to invert each of the data bits having a different value than the value of the stuck-at fault of the corresponding one of the memory cells to generate encoded data bits. The control circuit is operable to generate redundant bits that indicate the encoded data bits to invert to regenerate the data bits.

Abstract: Embodiments of the technology disclosed herein are intended to flexibly set the rules of attaching error correction codes to a group of data sequences stored in a memory. A storage control apparatus has an error correction code attachment rule hold block and an error correction portion. The error correction code attachment rule hold block holds the rules of attaching error correction codes to a group of data sequences stored in a memory by relating the rules with the data for each address of the group of data sequences. If an access occurs to the memory, the error correction portion executes error correction processing on a group of data sequences stored in the memory in accordance with the attachment rules related to the address at which the access occurred.

Abstract: A memory system comprises a nonvolatile memory device comprising a memory cell array comprising first and second memory blocks, and a memory controller configured to control the nonvolatile memory device to read data from the first memory block, selectively determine an error correction operation to be performed on the data after it is read from the first memory block based on a state of at least one of the first and second memory blocks, and then store the data in the second memory block.

Abstract: A method of enhancing an error correction performance in a data storage system, and a storage device using the method, determines a deterioration status of a physical area of a memory device to which data is to be stored and compresses data and stores the compressed data and an error correction code (ECC) with respect to the compressed data in an area of which the deterioration status is equal to or greater than a threshold value that is initially set and stores uncompressed data and an ECC with respect to the uncompressed data in an area of which the deterioration status is less than the threshold value.

Abstract: A method begins by a dispersed storage (DS) processing module generating a data object identifier for data to be stored in a dispersed storage network (DSN) and partitioning the data into a plurality of data partitions based on a set of retrieval preferences and data boundary information. For a data partition, the method continues with the DS processing module dispersed storage error encoding the data partition to produce a plurality of sets of encoded data slices and generating a plurality of sets of DSN addresses for the plurality of sets of encoded data slices, wherein a DSN address of the plurality of sets of DSN addresses includes a representation of the data object identifier, a representation of one or more retrieval preferences of the set of retrieval preferences, a representation of a corresponding portion of the data boundary information, and dispersed storage addressing information.

Abstract: A storage control apparatus including a first error detection block and a second error detection block is provided. The first error detection block is configured to execute error detection in accordance with a first data unit read from a memory and a first error detection code corresponding to the first data unit. The second error detection block is configured, if a second error detection code corresponding to a second data unit smaller than the first data unit is held in an error detection code hold block different from the memory, to execute error detection in accordance with the second data unit read from the memory and the second error detection code held in the error detection code hold block.

Abstract: According to one embodiment, a memory controller that controls a non-volatile semiconductor memory including a memory cell of 3 bits/cell includes a controller that extracts bits which becomes an error caused by the movement to the adjacent threshold voltage distribution from a first bit and a second bit of data to be written in each of the memory cells to generate a virtual page and an encoding unit that generate an error correcting code for the virtual page and writes the data for three pages and the error correcting code in the non-volatile semiconductor memory.

Abstract: A method begins by a dispersed storage (DS) processing module determining whether to send an encoded data slice of set of encoded data slices in accordance with a zero information gain (ZIG) format. When the encoded data slice is to be sent in accordance with the ZIG format, the method continues with the DS processing module selecting a partial encoding threshold number of encoded data slices of the set of encoded data slices, wherein the partial encoding threshold number of encoded data slices does not include the encoded data slice and generating a set of ZIG encoded data slices based on a ZIG function and the partial encoding threshold number of encoded data slices, wherein the set of ZIG encoded data slices represents recovery information of the encoded data slice. The method continues with the DS processing module outputting the set of ZIG encoded data slices.

Abstract: A method begins by a dispersed storage (DS) processing module receiving a zero information gain (ZIG) encoded data slice and a subset of encoded data slices of a set of encoded data slices. The method continues with the DS processing module generating a set of ZIG encoded data slices using a ZIG function and corresponding ones of the subset of encoded data slices, wherein the set of ZIG encoded data slices represents additional components of recovery information of a first encoded data slice. The method continues with the DS processing module recreating the first encoded data slice from the ZIG encoded data slice and the set of ZIG encoded data slices. The method continues with the DS processing module decoding the subset of encoded data slices and the first encoded data slice using a dispersed storage error coding function to reproduce data.

Abstract: A method begins by a dispersed storage (DS) processing module encoding data using a dispersed storage error coding function to produce a set of encoded data slices. The method continues with the DS processing module encoding a first encoded data slice of the set of encoded data slices using a zero information gain (ZIG) function based on a second encoded data slice of the set of encoded data slices to produce a ZIG encoded data slice. The method continues with the DS processing module outputting the ZIG encoded data slice and a subset of encoded data slices of the set of encoded data slices, wherein the subset of encoded data slices includes less than a decode threshold number of encoded data slices and does not include the first or the second encoded data slice.

Abstract: A method begins by a dispersed storage (DS) processing module obtaining a plurality of data objects for storage in a dispersed storage network (DSN) and determining one or more common data object aspects of a data object of the plurality of data objects. The method continues with the DS processing module disperse storage error encoding at least a portion of the data object to produce a set of encoded data slices and generating a set of DSN addresses for the set of encoded data slices, wherein each of the set of DSN addresses includes a field referencing the one or more common data object aspects. The method continues with the DS processing module outputting the set of encoded data slices for storage in the DSN based on the set of DSN addresses.

Abstract: A memory system that supports error detection and correction (EDC) coverage. The memory system includes a memory module with at least two groups of memory devices that store data and another memory device that stores error checking information (e.g., Error Correcting Code) for both groups of memory devices. The memory module also includes a memory buffer that determines an address for accessing the error checking information based on whether data is transferred with the first group of memory devices or the second group of memory devices. Alternatively, the memory controller may determine the address for accessing the error checking information to reduce or eliminate the need for a memory buffer.

Abstract: A flash memory controller includes an encoding block, a decoding block and a control unit. The encoding block is utilized for encoding raw bits with a target forward error-correction (FEC) coding scheme selected from a plurality of candidate FEC coding schemes. The decoding block is utilized for decoding encoded bits with a target FEC decoding scheme selected from a plurality of candidate FEC decoding schemes, wherein the target FEC decoding scheme corresponds to the target FEC coding scheme. The control unit is coupled to the encoding block and the decoding block, and utilized for controlling a selection of the target FEC coding scheme utilized by the encoding block and a selection of the target FEC decoding scheme utilized by the decoding block according to a number of program/erase cycles of a flash memory.

Abstract: A method includes, after data is stored at a data area of a memory device and error correction code (ECC) data corresponding to the data is stored at an ECC area corresponding to the data area, detecting a triggering condition. In response to detecting the triggering condition, the method also includes storing second ECC data in the ECC area, where the second ECC data includes redundant information for a first portion of the data area and storing third ECC data at the memory device. The third ECC data includes redundant information for a second portion of the data area.

Abstract: A method for providing data protection for data stored within a Random Access Memory element. The method comprises receiving data to be written to memory, dividing the received data into a plurality of data sections, applying error correction codes to the data sections to form codeword sections, interleaving the codeword sections to form an interleaved data codeword, and writing within a single clock cycle the interleaved data codeword to memory.

Abstract: A data storage device includes a memory including a plurality of storage elements. The memory is configured to read a group of the storage elements using a first read voltage to obtain a first plurality of bit values. A controller is coupled to the memory. The controller is configured to initiate a first error correction code (ECC) procedure on the first plurality of bit values. In response to the first ECC procedure determining that the first plurality of bit values is not correctable, the controller is further configured to instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values, and to change one or more values of the first plurality of bit values to corresponding values of the second plurality of bit values to generate a first plurality of corrected bit values.

Abstract: An apparatus, system, and method are disclosed for a front-end, distributed redundant array of independent drives (“RAID”). A storage request receiver module receives a storage request to store object or file data in a set of autonomous storage devices forming a RAID group. The storage devices independently receive storage requests from a client over a network, and one or more of the storage devices are designated as parity-mirror storage devices for a stripe. The striping association module calculates a stripe pattern for the data. Each stripe includes N data segments, each associated with N storage devices. The parity-mirror association module associates a set of the N data segments with one or more parity-mirror storage devices. The storage request transmitter module transmits storage requests to each storage device. Each storage request is sufficient to store onto the storage device the associated data segments. The storage requests are substantially free of data.

Abstract: A mechanism is provided for optimizing and enhancing performance for parity based storage, particularly redundant array of independent disk (RAID) storage. The mechanism optimizes a repetitive pattern write command for performance for storage configurations that require parity calculations. The mechanism eliminates the need for laborious parity calculations that are resource intensive and add to IO latency. For repetitive write commands that span across the full stripe of a RAID5 or similar volume, the mechanism calculates parity by looking at the pattern and the number of columns in the volume. The mechanism may avoid the XOR operation altogether for repetitive pattern write commands. The mechanism may enhance secure delete operations that use repetitive pattern write commands by eliminating data reliability operations like parity generation and writing altogether.

Abstract: According to the presently disclosed subject matter there is provided inter alia, a method and system which enable to uncover errors which are correctable by a data integrity mechanism in a computer system. The same data is read with the help of two different types of read commands. The first command is a read command which does not implement an inherent ECC and therefore does not correct corrupted data. The second command is a read command which includes an ECC and is adapted to correct errors which are detected in the data which is being read. The data obtained by each of the two read commands is compared, and in cases where a difference is identified between the two data, it is determined that an error has been detected and corrected by the ECC.

Abstract: A low-density parity check (LDPC) decoder includes a memory configured to store multiple variable node LLR values in a LLR memory and multiple check nodes messages in a CN memory. The LDPC decoder also includes a saturation indicator configured to determine whether each check node of the H-matrix becomes saturated, and a multiplexer. The multiplexer is configured store an extrinsic check node value in the CN memory and updated LLR value in the LLR memory when the variable node is not saturated; and store a freeze input value in the CN memory and a freeze value in the LLR memory when the variable node is saturated.

Abstract: An error-correcting code processing method includes: calculating descending symbols or ascending symbols or both, and calculating, as a parity, exclusive OR of all elements of an information symbol sequence; one or both of calculating exclusive OR for each element of the descending symbols, to generate low-order n bits of the descending symbols and calculating exclusive OR for each element of the ascending symbols, to generate low-order n bits of the ascending symbols; one or both of calculating exclusive OR of elements obtained by selecting, in descending order, elements from an element sequence resulting from arranging parities, to generate a high-order m bit of the descending symbols and calculating exclusive OR of elements obtained by selecting, in ascending order, elements from the element sequence, to generate a high-order m bit of the ascending symbols; and outputting the descending symbols or the ascending symbols or both as check symbols or a syndrome.

Abstract: Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.

Abstract: A method for providing end-to-end data protection while supporting multiple cyclic-redundancy-check (CRC) algorithms is disclosed. In one embodiment, such a method includes receiving, from a first host device, a data block protected by a first CRC. The first CRC is generated using a first CRC algorithm. The method checks the integrity of the data block using the first CRC and the first CRC algorithm. The method then computes a second CRC for the data block using a second CRC algorithm different from the first CRC algorithm. The method then stores the data block, the first CRC, and the second CRC on a storage medium, such as magnetic tape.

Abstract: An apparatus and method for veiling protected data in a memory is provided. The method includes encoding protected data using an Error Correcting Code (ECC); inserting a progression to the encoded protected data according to a preset rule; combining an error with the progression-inserted protected data; and storing the error-combined protected data in an arbitrary position in the memory.

Abstract: A flash memory device connected to a host includes: a flash memory; and a control circuit comprising a first error correcting code unit and a second error correcting code unit. The data length of a redundancy generated by the second error correcting code unit is longer than the data length of a redundancy generated by the first error correcting code unit. The first error correcting code unit is adopted to process with a data transmitted to the flash memory from the host when a damage risk of the flash memory is lower than a specific value; and the first and second error correcting code units are adopted to process with the data transmitted to the flash memory from the host when the damage risk of the flash memory is higher than the specific value.

Abstract: A decoding system includes a decoder, a first module and a second module. The decoder is configured to receive data read from an optical storage medium and perform a first decoding iteration and a second decoding iteration to decode the data. The first decoding iteration includes generating a resultant matrix. The first module is configured to, based on first decoding statuses of multiple bytes in the resultant matrix, determine second decoding statuses of bytes proximate to failed bytes of a feedback matrix. The feedback matrix is generated based on the resultant matrix. The first module is configured to mark selected ones of the failed bytes as erasures based on the second decoding statuses. The second module is configured to correct one or more of the bytes marked as erasures during the second decoding iteration.

Abstract: Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a plurality of erroneous data bits that belong to only one specific group of a plurality of groups of data bits and if none of the other groups of the plurality of groups have errors.

Abstract: The invention is directed to a method for reading information from an optical data storage medium, operating by: obtaining at least one coding/decoding unit of the optical data storage medium wherein the coding/decoding unit comprises a plurality of codewords; checking if the coding/decoding unit is reliable; and when the coding/decoding unit is not reliable; selecting at least one spec-defined codeword from the plurality of codewords. The spec-defined codeword includes a plurality of spec-defined fields defined by the specification of the coding/decoding unit; checking whether the spec-defined codeword is reliable; and when the spec-defined codeword is reliable, retrieving information from the spec-defined codeword.

Abstract: A method for computing and storing parity information in a RAID system includes dividing each segment in a stripe into a data block and a parity block, and storing in each parity block, parity information for a limited number of other data blocks in the stripe. A method for rebuilding data in a RAID system includes rebuilding the data from parity information and storing the rebuilt data on reserve portions of the remaining disks in the system.

Abstract: According to the embodiments, a memory device includes a memory to which data is written using memory cells as a write unit and a controller which controls the memory. In response to a request to write data with a logical address to the memory from a host device, the controller requests the host device to transmit a segment of the write data with a size specified by the controller. The controller writes the write data with additional data to the memory. The write-data segment has a size determined to allow the combined size of the write-data segment and corresponding additional data to be the largest while smaller than the size of the write unit or has a multiple integral of the size.