Cover ring for use in a semiconductor processing chamber
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Description
The broken lines in the drawings illustrate portions of the cover ring for use in a semiconductor processing chamber that form no part of the claimed design.
Claims
The ornamental design for a cover ring for use in a semiconductor processing chamber, as shown and described.
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Patent History
Patent number: D1145726
Type: Grant
Filed: Jun 28, 2024
Date of Patent: Sep 1, 2026
Assignee: Applied Materials Inc. (Santa Clara, CA)
Inventors: Abhishek Chowdhury (Bangalore), Harisha Sathyanarayana (Bangalore), Edwin C. Suarez (Pleasanton, CA), Siqing Lu (Santa Clara, CA), Nataraj Bhaskar Rao (Bangalore)
Primary Examiner: Richard Edgar
Assistant Examiner: Caleb M Baker
Application Number: 29/949,945
Type: Grant
Filed: Jun 28, 2024
Date of Patent: Sep 1, 2026
Assignee: Applied Materials Inc. (Santa Clara, CA)
Inventors: Abhishek Chowdhury (Bangalore), Harisha Sathyanarayana (Bangalore), Edwin C. Suarez (Pleasanton, CA), Siqing Lu (Santa Clara, CA), Nataraj Bhaskar Rao (Bangalore)
Primary Examiner: Richard Edgar
Assistant Examiner: Caleb M Baker
Application Number: 29/949,945
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)