Using Plasma Patents (Class 216/67)
  • Patent number: 8821741
    Abstract: A preprocess step for supplying an inert gas into an enclosed space in which a substrate is disposed, while exhausting gas by sucking out of the enclosed space. And then, an etching step for supplying a process vapor into the enclosed space while exhausting gas out of the enclosed space at an rate lower than a rate in the preprocess step. And then a post-process step for supplying an inert gas into the enclosed space while exhausting gas by sucking out of the enclosed space at a rate higher than the rate in the etching step.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: September 2, 2014
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Takashi Ota, Akio Hashizume, Takahiro Yamaguchi, Yuya Akanishi
  • Patent number: 8821739
    Abstract: A method for processing a substrate is provided; wherein the method comprises applying a film of a copolymer composition, comprising a poly(styrene)-b-poly(siloxane) block copolymer component; and, an antioxidant to a surface of the substrate; optionally, baking the film; subjecting the film to a high temperature annealing process under a gaseous atmosphere for a specified period of time; followed by a treatment of the annealed film to remove the poly(styrene) from the annealed film and to convert the poly(siloxane) in the annealed film to SiOx.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: September 2, 2014
    Assignees: Rohm and Haas Electronic Materials LLC, Dow Global Technologies LLC
    Inventors: Xinyu Gu, Shih-Wei Chang, Phillip D. Hustad, Jeffrey D. Weinhold, Peter Trefonas
  • Patent number: 8821746
    Abstract: A method of fabricating a semiconductor device includes dressing a surface of a polishing pad with a conditioning disk held by an arm while rotating a platen that holds the polishing pad in a chemical mechanical polishing apparatus, wherein the dressing is performed by pressing the conditioning disk to the polishing pad, and rotating the arm around a rotational axis of the arm thereby to move the conditioning disk substantially along a radius direction of the platen between a center part and a circumferential part of the platen, and wherein torque N applied to the arm is measured at plural positions of the conditioning disk along the substantial radius direction during the dressing, and it is determined whether maintenance to the arm is necessary in accordance with an average value <N> of the measured torques N and a fluctuation range Y of the measured torques N.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: September 2, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Ryota Kojima
  • Patent number: 8822341
    Abstract: A first gas for plasma etch and a second gas for plasma deposition are introduced onto a semiconductor substrate, the semiconductor substrate including a mask pattern. A flow rate of the first and second gases is periodically changed within a range of flow rates during a process cycle, such that a plasma etch process and a plasma deposition process are performed together to form an opening in the semiconductor substrate.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: September 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Ho Jeon, Dong-Hyun Kim, Je-Woo Han, Kyoung-Sub Shin
  • Patent number: 8821752
    Abstract: The present invention provides an etching composition, comprising a silyl phosphate compound, phosphoric acid and deionized water, and a method for fabricating a semiconductor, which includes an etching process employing the etching composition. The etching composition of the invention shows a high etching selectivity for a nitride film with respect to an oxide film. Thus, when the etching composition of the present invention is used to remove a nitride film, the effective field oxide height (EEH) may be easily controlled by controlling the etch rate of the oxide film. In addition, the deterioration in electrical characteristics caused by damage to an oxide film or etching of the oxide film may be prevented, and particle generation may be prevented, thereby ensuring the stability and reliability of the etching process.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: September 2, 2014
    Assignees: SK Hynix Inc., Soulbrain Co., Ltd.
    Inventors: Sung-Hyuk Cho, Kwon Hong, Hyung-Soon Park, Gyu-Hyun Kim, Ji-Hye Han, Jung-Hun Lim, Jin-Uk Lee, Jae-Wan Park, Chan-Keun Jung
  • Patent number: 8821738
    Abstract: A method for processing a substrate is provided; wherein the method comprises applying a film of a copolymer composition, comprising a poly(styrene)-b-poly(siloxane) block copolymer component; and, an antioxidant to a surface of the substrate; optionally, baking the film; annealing the film in a gaseous atmosphere containing ?20 wt % oxygen; followed by a treatment of the annealed film to remove the poly(styrene) from the annealed film and to convert the poly(siloxane) in the annealed film to SiOx.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: September 2, 2014
    Assignees: Rohm and Haas Electronic Materials LLC, Dow Global Technologies LLC
    Inventors: Phillip D. Hustad, Xinyu Gu, Shih-Wei Chang, Jeffrey D. Weinhold, Peter Trefonas
  • Patent number: 8822345
    Abstract: A plasma processing apparatus includes a gas distribution member which supplies a process gas and radio frequency (RF) power to a showerhead electrode. The gas distribution member can include multiple gas passages which supply the same process gas or different process gases at the same or different flow rates to one or more plenums at the backside of the showerhead electrode. The gas distribution member provides a desired process gas distribution to be achieved across a semiconductor substrate processed in a gap between the showerhead electrode and a bottom electrode on which the substrate is supported.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: September 2, 2014
    Assignee: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Eric Lenz
  • Patent number: 8821742
    Abstract: A plasma etching method by using a plasma etching apparatus having a depressurizable processing chamber; a lower electrode for mounting thereon a substrate to be processed in the processing chamber; an upper electrode facing the lower electrode in the processing chamber with a plasma generation region formed therebetween; a radio frequency power supply unit for applying a radio frequency power between the upper electrode and the lower electrode to thereby form a radio frequency electric field in the plasma generation region, the method comprising: supplying a first gas including etchant gas to an upper gas inlet to introduce the first gas through the upper electrode into the plasma generation region; and feeding a second gas including dilution gas to a side gas inlet to introduce the second gas through a sidewall of the processing chamber into the plasma generation region.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: September 2, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Ryoichi Yoshida, Tetsuo Yoshida, Michishige Saito, Toshikatsu Wakaki, Hayato Aoyama, Akira Obi, Hiroshi Suzuki
  • Patent number: 8821736
    Abstract: A method for making a perpendicular magnetic recording disk includes forming a template layer below a Ru or Ru alloy underlayer, with a granular Co alloy recording layer formed on the underlayer. The template layer is formed by depositing a solution of a polymer with a functional end group and nanoparticles, allowing the solution to dry, annealing the polymer layer to thereby form a polymer layer with embedded spaced-apart nanoparticles, and then etching the polymer layer to a depth sufficient to partially expose the nanoparticles so they protrude above the surface of the polymer layer. The protruding nanoparticles serve as controlled nucleation sites for the Ru or Ru alloy atoms. The nanoparticle-to-nanoparticle distances can be controlled during the formation of the template layer. This enables control of the Co alloy grain diameter distribution as well as grain-to-grain distance distribution.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 2, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Bruce Alvin Gurney, Dan Saylor Kercher, Alan C Lam, Ricardo Ruiz, Manfred Ernst Schabes, Kentaro Takano, Shi-Ling Chang Wang, Qing Zhu
  • Publication number: 20140238954
    Abstract: A method of producing a structure containing a phase-separated structure, including forming, on a substrate, a layer containing a block copolymer having a block of a polyhedral oligomeric silsesquioxane structure-containing structural unit; forming a top coat film by applying, to the layer containing the block copolymer, a top coat material which undergoes a change in polarity upon heating, and controls a surface energy of the layer containing the block copolymer; and subjecting the layer containing the block copolymer on which the top coat film is formed to phase separation by thermal annealing.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicants: Tokyo Institute of Technology, Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Tasuku Matsumiya, Takehiro Seshimo, Katsumi Ohmori, Ken Miyagi, Daiju Shiono, Kenichiro Miyashita, Tsuyoshi Kurosawa, Teruaki Hayakawa
  • Publication number: 20140238955
    Abstract: Plasma processing systems and methods for using pre-dissociated and/or pre-ionized tuning gases are disclosed herein. In one embodiment, a plasma processing system includes a reaction chamber, a support element in the reaction chamber, and one or more cathode discharge assemblies in the reaction chamber. The reaction chamber is configured to produce a plasma in an interior volume of the chamber. The support element positions a microelectronic workpiece in the reaction chamber, and the cathode discharge assembly supplies an at least partially dissociated and/or ionized tuning gas to the workpiece in the chamber.
    Type: Application
    Filed: May 8, 2014
    Publication date: August 28, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Mark Kiehlbauch
  • Patent number: 8815746
    Abstract: An apparatus and the use of such an apparatus and method for producing microcomponents with component structures are presented which are generated in a process chamber on a substrate according to the LIGA method for example and are stripped from the enclosing photoresist with the help of a cooled remote plasma source.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: August 26, 2014
    Assignee: R3T GmbH Rapid Reactive Radicals Technology
    Inventor: Josef Mathuni
  • Patent number: 8815745
    Abstract: A method of forming features in a porous low-k dielectric layer disposed below a patterned organic mask is provided. Features are etched into the porous low-k dielectric layer through the patterned organic mask, and then the patterned organic mask is stripped. The stripping of the patterned organic mask includes providing a stripping gas comprising COS, forming a plasma from the stripping gas, and stopping the stripping gas. A cap layer may be provided between the porous low-k dielectric layer and the patterned organic mask. The stripping of the patterned organic mask leaves the cap layer on the porous low-k dielectric layer.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: August 26, 2014
    Assignee: Lam Research Corporation
    Inventors: Sean S. Kang, Sang Jun Cho, Thomas S. Choi
  • Publication number: 20140231389
    Abstract: At a first timing after mounting a semiconductor wafer W on an electrostatic chuck 38, a susceptor 12 is switched from an electrically grounded state into a floated state. From a second timing after the first timing, a second high frequency power HF for plasma generation is applied to the susceptor 12, and a processing gas is excited into plasma in a chamber 10. From a third timing after the second timing, a first high frequency power LF for ion attraction is applied to the susceptor 12, and a self-bias (?Vdc) is generated. From a fourth timing close to the third timing, a negative second DC voltage ?BDC corresponding to the self-bias (?Vdc) is applied to the susceptor 12. From the fifth timing after the fourth timing, a positive first DC voltage ADC is applied to an inner electrode 42 of the electrostatic chuck 38.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 21, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kohichi Nagami, Norikazu Yamada, Tadashi Gondai, Kouichi Yoshida
  • Patent number: 8808562
    Abstract: A method of etching an aluminum-containing layer on a substrate is described. The method includes forming plasma from a process composition containing a halogen element, and exposing the substrate to the plasma to etch the aluminum-containing layer. The method may additionally include exposing the substrate to an oxygen-containing environment to oxidize a surface of the aluminum-containing layer and control an etch rate of the aluminum-containing layer. The method may further include forming first plasma from a process composition containing HBr and an additive gas having the chemical formula CxHyRz (wherein R is a halogen element, x and y are equal to unity or greater, and z is equal to zero or greater), forming second plasma from a process composition containing HBr, and exposing the substrate to the first plasma and the second plasma to etch the aluminum-containing layer.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: August 19, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Yusuke Ohsawa, Hiroto Ohtake, Eiji Suzuki, Kaushik Arun Kumar, Andrew W. Metz
  • Patent number: 8808561
    Abstract: A method for processing substrate in a processing chamber, which has at least one plasma generating source and a gas source for providing process gas into the chamber, is provided. The method includes exciting the plasma generating source with an RF signal having RF frequency. The method further includes pulsing the gas source, using at least a first gas pulsing frequency, such that a first process gas is flowed into the chamber during a first portion of a gas pulsing period and a second process gas is flowed into the chamber during a second portion of the gas pulsing period, which is associated with the first gas pulsing frequency. The second process gas has a lower reactant-gas-to-inert-gas ratio relative to a reactant-gas-to-inert-gas ratio of the first process gas. The second process gas is formed by removing at least a portion of a reactant gas flow from the first process gas.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: August 19, 2014
    Assignee: Lam Research Coporation
    Inventor: Keren Jacobs Kanarik
  • Patent number: 8809199
    Abstract: A processing method is provided for plasma etching features in a silicon nitride (SiN) film covered by a mask pattern. The method includes preparing a film stack on a substrate, the film stack containing a SiN film on the substrate and a mask pattern on the SiN film, forming a plasma from a process gas containing HBr gas, O2 gas, and a carbon-fluorine-containing gas, applying pulsed RF bias power to the substrate, and transferring the mask pattern to the SiN film by exposing the film stack to the plasma.
    Type: Grant
    Filed: February 12, 2011
    Date of Patent: August 19, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Tetsuya Nishizuka
  • Patent number: 8808558
    Abstract: The invention provides a system and method for alignment of nanoparticles on a substrate. The system includes: a substrate; a plurality of polypeptide templates formed on the substrate; and a plurality of nanoparticles formed on the polypeptide templates. The method includes: providing a substrate; forming a plurality of polypeptide templates on the substrate; and forming a plurality of nanoparticles on the polypeptide templates.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: August 19, 2014
    Assignee: National Sun Yat-Sen University
    Inventor: Shu-Chen Hsieh
  • Patent number: 8809194
    Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: August 19, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Kaushik Arun Kumar
  • Patent number: 8808563
    Abstract: Methods of etching exposed silicon on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and a hydrogen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon while very slowly removing other exposed materials. The silicon selectivity results, in part, from a preponderance of hydrogen-containing precursor in the remote plasma which hydrogen terminates surfaces on the patterned heterogeneous structures. A much lower flow of the fluorine-containing precursor progressively substitutes fluorine for hydrogen on the hydrogen-terminated silicon thereby selectively removing silicon from exposed regions of silicon.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Anchuan Wang, Jingchun Zhang, Nitin K. Ingle, Young S. Lee
  • Publication number: 20140224768
    Abstract: The invention relates to a method for removing carbon layers, in particular ta-C layers, from substrate surfaces of tools and components. The substrate to be de-coated is accordingly arranged on a substrate support in a vacuum chamber, the vacuum chamber is charged with at least one reactive gas assisting the evacuation of carbon in gaseous form and a low-voltage plasma discharge is created in the vacuum chamber to activate the reactive gas and hence assist the required chemical reaction or reactions to de-coat the coated substrate. The low-voltage plasma discharge is a dc low-volt arc discharge, the substrate surfaces to be de-coated are bombarded substantially exclusively with electrons and oxygen, nitrogen and hydrogen are used as reactive gas.
    Type: Application
    Filed: May 31, 2012
    Publication date: August 14, 2014
    Applicant: OERLIKON TRADING AG, TRUBBACH
    Inventors: Jürgen Ramm, Beno Widrig
  • Patent number: 8801951
    Abstract: In a plasma processing method for conducting etching on an object to be processed by generating plasma from depositional gas introduced into a processing chamber and exposing the object to be processed to the plasma in a state in which radio frequency power is applied, the object to be processed is etched under etching conditions that a deposit film on an inner wall of the processing chamber becomes amorphous by repeating a first period during which the object to be processed is exposed to plasma and a second period during which the object to be processed is exposed to plasma and an etching rate is lower as compared with the first period. Consequently, particles due to increase in the number of processed sheets of the object to be processed can be suppressed.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: August 12, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yoshiharu Inoue, Michikazu Morimoto, Tsuyoshi Matsumoto, Tetsuo Ono, Tadamitsu Kanekiyo, Mamoru Yakushiji, Masakazu Miyaji
  • Patent number: 8801943
    Abstract: The present disclosure describes a method for manufacturing a full wraparound shield damascene write head through the implementation of a three layered (tri-layered) hard mask. According to an embodiment of the invention, the various layers of hard mask are used for different purposes during the formation of a write head. The wraparound shield head of the present invention exhibits improved physical characteristics that further result in improved performance characteristics. Use of the hard mask layers according to the present invention allows for use of manufacturing processes that can be more closely controlled than those processes used in other processes. For example, smaller dimension lithographic techniques can be used. Also, reliance on certain CMP processes is not necessary where the use of CMP processes is not as well-controlled as deposition or lithographic techniques as is possible using the present invention.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: August 12, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Shiwen Huang, Fenglin Liu, Qiping Zhong, Kyusik Shin, Yingjian Chen
  • Patent number: 8801944
    Abstract: A method for manufacturing a magnetic write pole of a magnetic write head that achieves improved write pole definition reduced manufacturing cost and improves ease of photoresist mask re-work. The method includes the use of a novel bi-layer hard mask beneath a photoresist mask. The bi-layer mask includes a layer of silicon dielectric, and a layer of carbon over the layer of silicon dielectric. The carbon layer acts as an anti-reflective coating layer that is unaffected by the photolithographic patterning process used to pattern the write pole and also acts as an adhesion layer for resist patterning. In the event that the photoresist patterning is not within specs and a mask re-work must be performed, the bi-layer mask can remain intact and need not be removed and re-deposited. In addition, the low cost and ease of use silicon dielectric and carbon reduce manufacturing cost and increase throughput.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: August 12, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Guomin Mao, Yi Zheng
  • Patent number: 8795790
    Abstract: [Problem] An object is to provide a magnetic recording medium with improved HDI characteristics, such as impact resistance, and its manufacturing method. [Solution] A typical structure of a magnetic recording medium 100 according to the present invention includes, on a base, at least a magnetic recording layer 122, a protective layer 126, and a lubricating layer 128, wherein the magnetic recording layer 122 includes, in an in-plane direction, a magnetic recording part 136 configured of a magnetic material and a non-recording part 134 magnetically separating the magnetic recording part 136, and a surface corresponding to the non-recording part 134 protuberates more than a surface corresponding to the magnetic recording part 136.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: August 5, 2014
    Assignee: WD Media (Singapore) Pte. Ltd.
    Inventors: Yoshiaki Sonobe, Akira Shimada, Tsuyoshi Ozawa, Masanori Aniya
  • Publication number: 20140211294
    Abstract: A method of manufacturing an electrowetting display device includes forming a protection layer on a pixel electrode, forming a water-repellent layer on the protection layer, and removing the water-repellent layer from regions surrounding a display area of the pixel electrode. The water-repellent layer is formed by coating the protection layer with a hydrophilic material using a method such as slit coating. The water-repellent layer is removed using a method such as an edge bead removal method. The resulting water-repellent layer has a uniform thickness.
    Type: Application
    Filed: April 3, 2014
    Publication date: July 31, 2014
    Applicant: Liquavista B.V.
    Inventors: Dae Jin Park, Seong Gyu Kwon, Ji Seong Yang, Jun Heui Lee
  • Patent number: 8790525
    Abstract: A method of manufacturing a magnetic recording medium is provided. The method includes: forming a magnetic layer 2 on a non-magnetic substrate 1; forming a mask layer 3 on the magnetic layer 2; forming a resist layer 4 which is patterned into a predetermined shape on the mask layer 3; patterning the mask layer 3 into a shape corresponding to the resist layer 4 using the resist layer 4; patterning the magnetic layer 2 into a shape corresponding to the mask layer 3 using the patterned mask layer 3; and removing the mask layer 3 that remains on the magnetic layer 2 by reactive plasma etching. The reactive plasma etching is performed under an atmosphere containing an organic compound having at least one kind or plural kinds of functional groups selected from a hydroxyl group, a carbonyl group, a hydroxy carbonyl group, an alkoxy group, and an ether group.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: July 29, 2014
    Assignee: Showa Denko K.K.
    Inventors: Makoto Hiwatari, Akira Yamane, Tomoo Shige, Akira Sakawaki
  • Patent number: 8791021
    Abstract: Polycrystalline silicon germanium (SiGe) can offer excellent etch selectivity to silicon during cryogenic deep reactive ion etching in an SF6/O2 plasma. Etch selectivity of over 800:1 (Si:SiGe) may be achieved at etch temperatures from ?80 degrees Celsius to ?140 degrees Celsius. High aspect ratio structures with high resolution may be patterned into Si substrates using SiGe as a hard mask layer for construction of microelectromechanical systems (MEMS) devices and semiconductor devices.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 29, 2014
    Assignee: King Abdullah University of Science and Technology
    Inventors: Mohamed Serry, Andrew Rubin, Mohamed Refaat, Sherif Sedky, Mohammad Abdo
  • Patent number: 8790594
    Abstract: Systems and methods to pattern surfaces to create regions of variable adhesive force on a superhydrophobic paper surface. By taking advantage of high surface energy sticky islands on a non-sticky superhydrophobic surface, microliter water drops can be registered or confined at specific locations; selected drops can then be transferred to another patterned substrate and the drops mixed and/or allowed to react without the need for pipettes or other fluid transfer tool.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: July 29, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Dennis W. Hess, Balamurali Balu, Victor Breedveld
  • Patent number: 8790530
    Abstract: A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: July 29, 2014
    Assignee: Spansion LLC
    Inventors: Angela T. Hui, Gang Xue
  • Patent number: 8790529
    Abstract: A gas supply system for supplying a gas into a processing chamber for processing a substrate to be processed includes: a processing gas supply unit; a processing gas supply line; a first and a second branch line; a branch flow control unit; an additional gas supply unit; an additional gas supply line; and a control unit. The control unit performs, before processing the substrate to be processed, a processing gas supply control and an additional gas supply control by using the processing gas supply unit and the additional gas supply unit, respectively, wherein the additional gas supply control includes a control that supplies the additional gas at an initial flow rate greater than a set flow rate and then at the set flow rate after a lapse of a period of time.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: July 29, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shinichiro Hayasaka, Ken Horiuchi, Fumiko Yagi, Takeshi Yokouchi
  • Patent number: 8790524
    Abstract: A method and system for fabricating a magnetic transducer is described. The transducer has device and field regions, and a magnetoresistive stack. Hard mask layer and wet-etchable layers are provided on the magnetoresistive stack and hard mask layer, respectively. A hard mask and a wet-etchable mask are formed from the hard mask and the wet-etchable layers, respectively. The hard and wet-etchable masks each includes a sensor portion and a line frame. The sensor portion covers part of the magnetoresistive stack corresponding to a magnetoresistive structure. The line frame covers a part of the magnetoresistive stack in the device region. The magnetoresistive structure is defined in a track width direction. Hard bias material(s) are then provided. Part of the hard bias material(s) is adjacent to the magnetoresistive structure in the track width direction. The wet-etchable sensor portion and line frame, and hard bias material(s) thereon, are removed.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: July 29, 2014
    Assignee: Western Digital (Fremont), LLC
    Inventors: Guanghong Luo, Danning Yang, Ming Jiang
  • Patent number: 8784673
    Abstract: Methods for fabricating templates for nanoelement assembly and methods for fluid-guided assembly of nanoelements are provided. Templates are fabricated by plasma modification of surface hydrophilicity and production of a network of hydrophobic trenches having a hydrophilic bottom surface. Single-walled carbon nanotubes (SWNT) can be assembled into stable films, ribbons, and wires of nanoscale thickness and nanoscale or microscale width and length. The nanofilm assemblies prepared according to the invention are highly conductive and can be used in the fabrication of a wide variety of microscale and nanoscale electronic devices.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: July 22, 2014
    Assignee: Northeastern University
    Inventors: Xugang Xiong, Laila Jaberansari, Ahmed Busnaina, Yung Joon Jung, Sivasubramanian Somu, Moneesh Upmanyu
  • Patent number: 8784677
    Abstract: A plasma processing apparatus for applying an etching processing to a wafer by using at least two steps of the etching processing which operate with plasma formed within a pressure-reduced processing chamber, the wafer being located within the processing chamber inside a vacuum vessel, and having a mask on a silicon-composed substrate and a film structure, the film structure including processing-target films located under the mask, wherein the plasma processing apparatus is equipped with a function for processing another different wafer in such a manner that a processing condition at a precedent-stage step of the two steps of the etching processing in the processing of the different wafer is adjusted based on a result obtained by detecting a time which has elapsed until termination of a subsequent-stage step of the two steps of the etching processing.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: July 22, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Daisuke Shiraishi, Akira Kagoshima, Satomi Inoue, Shigeru Nakamoto
  • Patent number: 8784674
    Abstract: A perpendicular magnetic recording (PMR) head is fabricated with a pole tip shielded laterally by a graded side shield that is conformal to the shape of the pole tip at an upper portion of the shield but not conformal to the pole tip at a lower portion. The shield includes a trailing shield, that is conformal to the trailing edge of the pole tip and may include a leading edge shield that magnetically connects two bottom ends of the graded side shield.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: July 22, 2014
    Assignee: Headway Technologies, Inc.
    Inventors: Yan Wu, Zhigang Bai, Moris Dovek, Cherng-Chyi Han, Min Li, Jianing Zhou, Jiun-Ting Lee, Min Zheng
  • Patent number: 8786792
    Abstract: A mother substrate for a liquid crystal display device includes: a substrate; a plurality of unit array patterns on the substrate, each of the plurality of unit array patterns including a gate line, a data line crossing the gate line, a thin film transistor connected to the gate line and the data line and a pixel electrode connected to the thin film transistor; a first electrostatic discharge pattern surrounding the plurality of unit array patterns; a second electrostatic discharge pattern connected to the gate line and crossing the first electrostatic discharge pattern; and a third electrostatic discharge pattern connected to the data line and crossing the first electrostatic discharge pattern, the third electrostatic discharge pattern contacting the second electrostatic discharge pattern.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: July 22, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Jeong-yeop Lee, Jae-myung Seok, Jae-woo Jung, Young-seok Choi, Hyock-jae Shin
  • Publication number: 20140197135
    Abstract: A plasma processing method includes forming a silicon oxide film on a surface of a member provided within a chamber with plasma of a silicon-containing gas without oxygen while controlling a temperature of the member to be lower than a temperature of another member; performing a plasma process on a target object loaded into the chamber with plasma of a processing gas after the silicon oxide film is formed on the surface of the member; and removing the silicon oxide film from the surface of the member with plasma of a fluorine-containing gas after the target object on which the plasma process is performed is unloaded to an outside of the chamber.
    Type: Application
    Filed: January 14, 2014
    Publication date: July 17, 2014
    Inventors: Takayuki Katsunuma, Masanobu Honda, Hironobu Ichikawa
  • Patent number: 8778574
    Abstract: A method and apparatus for etching photomasks are provided herein. In one embodiment, a method of etching an ARC layer or an absorber layer disposed on a photomask includes transferring a film stack into an etching chamber, the film stack having an ARC layer or an absorber layer partially exposed through a patterned layer, providing a gas mixture including at least one fluorine containing gas in to a processing chamber, applying a source RF power to form a plasma from the gas mixture, applying a first type of RF bias power to the substrate for a first period of time, applying a second type of RF bias power away from the substrate for a second period of time, and etching the ARC layer or the absorber layer through the patterned layer in the presence of the plasma.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: July 15, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Keven Yu, Madhavi Chandrachood, Amitabh Sabharwal, Ajay Kumar
  • Patent number: 8778201
    Abstract: A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc?No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Toshiro Hiraoka, Yoshihiro Akasaka, Yasuyuki Hotta
  • Patent number: 8778194
    Abstract: A method is described for manufacturing a component having a through-connection. The method includes providing a substrate; forming a trench structure in the substrate, a substrate area which is completely surrounded by the trench structure being produced; forming a closing layer for closing off the trench structure, a cavity girded by the closing layer being formed in the area of the trench structure; removing substrate material from the substrate area surrounded by the closed-off trench structure; and at least partially filling the substrate area surrounded by the closed-off trench structure with a metallic material. A component having a through-connection is also described.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: July 15, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Jochen Reinmuth, Yvonne Bergmann
  • Patent number: 8778205
    Abstract: The present invention is a processing method including a processing step of performing predetermined processing for a workpiece; an unnecessary portion removal step of removing an unnecessary portion produced on a surface of the workpiece due to the predetermined processing; and a surface structure evaluation step of evaluating a surface structure of the workpiece from which the unnecessary portion has been removed by the unnecessary portion removal step.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: July 15, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tsuyoshi Ohno, Toshihiko Kikuchi, Machi Moriya, Yoshitaka Saita
  • Patent number: 8778204
    Abstract: A method and apparatus for monitoring a target layer in a plasma process having a photoresist layer is provided. The method is useful in removing noise associated with the photoresist layer, and is particularly useful when signals associated with the target layer is weak, such as when detecting an endpoint for a photomask etching process.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: July 15, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Michael N. Grimbergen
  • Patent number: 8776334
    Abstract: A method of manufacturing a piezoelectric thin film resonator which can reduce variations in resonant frequency and resonant resistance by uniformly planarizing a structural film. The method of manufacturing the piezoelectric thin film resonator includes the steps of forming sacrifice layer patterns on an upper surface of a mother substrate; forming a dielectric film on the sacrifice layer patterns; processing a surface of the dielectric film by a plasma treatment; forming vibration portions on the dielectric film, the vibration portions each being composed of two excitation electrodes and a piezoelectric thin film provided therebetween; etching the sacrifice layer patterns; and cutting the mother substrate into separate piezoelectric thin film resonators.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: July 15, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hidetoshi Fujii, Ryuichi Kubo
  • Patent number: 8778206
    Abstract: In a substrate processing method, a polysilicon layer 38 on a wafer W is etched with a bromine cation 45a and a bromine radical 45b in plasma generated from a processing gas containing a hydrogen bromide gas, an oxygen gas, and a nitrogen trifluoride gas, and then, is ashed with an oxygen radical 46 and a nitrogen radical 47 in plasma generated from a processing gas containing an oxygen gas and a nitrogen gas. Thereafter, the polysilicon layer 38 is etched with a fluorine cation 48a and a fluorine radical 48b in plasma generated from a processing gas containing an argon gas and a nitrogen trifluoride gas. While the polysilicon layer 38 is ashed, an oxidation process is performed on a silicon bromide generated by etching the polysilicon layer 38 with the bromine cation 45a.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: July 15, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Takashi Sone, Fumiko Yamashita
  • Patent number: 8771530
    Abstract: A method for producing a polarizing element includes: forming particulate materials of a metal halide on a glass substrate; forming a protective film that covers the particulate materials in a non-plasma environment; stretching the particulate materials by heating and stretching the glass substrate; and forming acicular metal particles by reducing the metal halide constituting the stretched particulate materials.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: July 8, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Yoshitomo Kumai
  • Patent number: 8772172
    Abstract: A semiconductor device manufacturing method includes a plasma etching step for etching an etching target film formed on a substrate accommodated in a processing chamber. In the plasma etching step, a processing gas including a gaseous mixture containing predetermined gases is supplied into the processing chamber, and a cycle including a first step in which a flow rate of at least one of the predetermined gases is set to a first value during a first time period and a second step in which the flow rate thereof is set to a second value that is different from the first value during a second time period is repeated consecutively at least three times without removing a plasma. The first time period and the second time period are set to about 1 to 15 seconds.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: July 8, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Masato Kushibiki, Eiichi Nishimura
  • Patent number: 8771537
    Abstract: Uniformity of a plasma process on a surface of a substrate is to be improved. In a plasma processing apparatus that processes a substrate by generating plasma from a processing gas introduced in a processing container, a ratio between an introducing amount of the processing gas introduced to a center portion of the substrate received in the processing container and an introducing amount of the processing gas introduced to a peripheral portion of the substrate received in the processing container is changed during a plasma process. Accordingly, a variation in an etching rate or the like between the center portion and the peripheral portion of the substrate may be reduced. Therefore, uniformity of the plasma process on the surface of the substrate is improved.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: July 8, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Toshihisa Ozu, Naoki Matsumoto, Takashi Tsukamoto, Kazuto Takai
  • Patent number: 8771539
    Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. The chemical reaction resulting from the combination produces reactants which etch the patterned heterogeneous structures to produce, in embodiments, a thin residual structure exhibiting little deformation. The methods may be used to conformally trim silicon oxide while removing little or no silicon, polysilicon, silicon nitride, titanium or titanium nitride. In an exemplary embodiment, the etch processes described herein have been found to remove mold oxide around a thin cylindrical conducting structure without causing the cylindrical structure to significantly deform.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: July 8, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jingchun Zhang, Anchuan Wang, Nitin K. Ingle
  • Patent number: 8771538
    Abstract: Embodiments of the present invention generally provide a plasma source apparatus, and method of using the same, that is able to generate radicals and/or gas ions in a plasma generation region that is symmetrically positioned around a magnetic core element by use of an electromagnetic energy source. In general, the orientation and shape of the plasma generation region and magnetic core allows for the effective and uniform coupling of the delivered electromagnetic energy to a gas disposed in the plasma generation region. In general, the improved characteristics of the plasma formed in the plasma generation region is able to improve deposition, etching and/or cleaning processes performed on a substrate or a portion of a processing chamber that is disposed downstream of the plasma generation region.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: July 8, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Dmitry Lubomirsky, Jang-Gyoo Yang, Matthew Miller, Jay Pinson, Kien Chuc
  • Patent number: RE45057
    Abstract: A method of manufacturing an ink jet recording head. The method includes providing a laminated structure in which a first electrode layer is located on a diaphragm, a piezoelectric layer is located on the first electrode layer, and a second electrode layer is located on the piezoelectric layer and etching the first electrode layer, the second electrode layer and the piezoelectric layer so that a portion of the diaphragm is exposed. In this method, at least the second electrode layer and the piezoelectric layer are etched simultaneously.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: August 5, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Tsutomu Hashizume, Tetsushi Takahashi