Using Plasma Patents (Class 216/67)
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Publication number: 20130264308Abstract: A chuck and a wafer supported thereon are rotated during a plasma process or a film deposition process to reduce thickness non-uniformity of a film processed or deposited on the wafer.Type: ApplicationFiled: April 4, 2012Publication date: October 10, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lung YANG, Ying XIAO, Chin-Hsiang LIN
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Patent number: 8551349Abstract: A method for producing a magnetic recording medium having a magnetically partitioned magnetic recording pattern on at least one surface of a nonmagnetic substrate, characterized by comprising a step of reacting portions of a magnetic layer, formed on the non-magnetic substrate, with ozone to modify magnetic properties of said portions of the magnetic layer for forming the magnetically partitioned magnetic recording pattern. The magnetic layer can be a two-layer structure comprising a magnetic layer having a granular structure and formed thereon a magnetic layer having a non-granular structure. The produced magnetic recording medium exhibits a greatly enhanced recording density while recording/reproducing characteristics equal to or better than those of the heretofore proposed magnetic recording mediums are maintained, and it can be produced with an enhanced efficiency.Type: GrantFiled: December 24, 2008Date of Patent: October 8, 2013Assignee: Showa Denko K.K.Inventors: Masato Fukushima, Akira Sakawaki, Akira Yamane
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Publication number: 20130256270Abstract: According to one embodiment, a plasma processing apparatus includes: a processing chamber; a decompression section configured to decompress inside of the processing chamber; a member including a control section to be inserted into a depression provided on mounting side of a workpiece, the control section being configured to thereby control at least one of in-plane distribution of capacitance of a region including the workpiece and in-plane distribution of temperature of the workpiece; a mounting section provided inside the processing chamber; a plasma generating section configured to supply electromagnetic energy to a region for generating a plasma for performing plasma processing on the workpiece; and a gas supply section configured to supply a process gas to the region for generating a plasma. The control section performs control so that at least one of the in-plane distribution of capacitance and the in-plane distribution of temperature is made uniform.Type: ApplicationFiled: March 19, 2013Publication date: October 3, 2013Applicants: KABUSHIKI KAISHA TOSHIBA, SHIBAURA MECHATRONICS CORPORATIONInventors: Takeharu MOTOKAWA, Tokuhisa OOIWA, Kensuke DEMURA, Tomoaki YOSHIMORI, Makoto KARYU, Yoshihisa KASE, Hidehito AZUMANO
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Publication number: 20130256269Abstract: The described embodiments relate generally to the manufacturing of consumer electronics and computing devices, and more particularly to providing mechanisms that modify the surface energy of a substrate to facilitate the forming of a bond between disparate materials. In one embodiment, the surface energy of a polyester substrate can be enhanced by exposing a surface of the polyester substrate to a plasma formed from approximately 90% atmospheric air, 5% carbon dioxide, and 5% argon. In another embodiment, contaminants can be removed from the surface of the polyester substrate and the surface energy of the substrate can be increased by exposing the polyester substrate first to an argon plasma etching process and second to a plasma formed from approximately 95% atmospheric air and 5% carbon dioxide.Type: ApplicationFiled: September 28, 2012Publication date: October 3, 2013Applicant: Apple Inc.Inventor: Michael M. NIKKHOO
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Publication number: 20130256268Abstract: A plasma processing system. The processing system comprises a process chamber having first and second ends arranged such that the first end opposes the second end. A substrate support is positioned at the first end of the process chamber and is configured to support a substrate. An exhaust system is positioned proximate the second end of the process chamber and draws a vacuum on the process chamber. Between the exhaust system and substrate support there is a plurality of super-Debye openings, and between the exhaust system and the plurality of super-Debye openings is a plurality of sub-Debye openings. The super-Debye openings are configured to limit diffusion of plasma while the sub-Debye openings are configured to quench plasma.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Lee Chen, Merritt Funk
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Patent number: 8546265Abstract: A method for manufacturing a silicon structure according to the present invention includes, in a so-called dry-etching process wherein gas-switching is employed, the steps of: etching a portion in the silicon region at a highest etching rate under a high-rate etching condition such that the portion does not reach the etch stop layer; subsequently etching under a transition etching condition in which an etching rate is decreased with time from the highest etching rate in the high-rate etching condition; and thereafter, etching the silicon region under a low-rate etching condition of a lowest etching rate in the transition etching condition.Type: GrantFiled: April 8, 2009Date of Patent: October 1, 2013Assignee: SPP Technologies Co., Ltd.Inventors: Yoshiyuki Nozawa, Takashi Yamamoto
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Patent number: 8545711Abstract: A processing method performs a predetermined process to an object by supplying a process gas at a prescribed flow rate into a process container to which a gas supply unit and an exhaust system are connected. The processing method includes a first process of setting the gas supply unit to supply a process gas at a flow rate greater than the prescribed flow rate of a predetermined process for a predetermined short time from a gas channel while exhausting an atmosphere in the process container through the exhaust system; and a second process of setting the gas supply unit to supply the process gas at the prescribed flow rate from the gas channel after the first process is completed.Type: GrantFiled: December 28, 2012Date of Patent: October 1, 2013Assignee: Tokyo Electron LimitedInventors: Toshihisa Nozawa, Koji Kotani, Kouji Tanaka
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Patent number: 8541312Abstract: A method of suppressing the etch rate for exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. The etch selectivity of silicon relative to silicon nitride and other silicon-and-nitrogen-containing material is increased using the method. The first stage of the remote plasma etch reacts plasma effluents with the patterned heterogeneous structures to form protective solid by-product on the silicon-and-nitrogen-containing material. The plasma effluents of the first stage are formed from a remote plasma of a combination of precursors, including nitrogen trifluoride and hydrogen (H2). The second stage of the remote plasma etch also reacts plasma effluents with the patterned heterogeneous structures to selectively remove material which lacks the protective solid by-product. The plasma effluents of the second stage are formed from a remote plasma of a fluorine-containing precursor.Type: GrantFiled: January 18, 2013Date of Patent: September 24, 2013Assignee: Applied Materials, Inc.Inventors: Yunyu Wang, Anchuan Wang, Jingchun Zhang, Nitin K. Ingle, Young S. Lee
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Patent number: 8540852Abstract: Disclosed are method and apparatus for manufacturing a magnetoresistive device which are suitable for manufacturing a high-quality magnetoresistive device by reducing damages caused during the processing of a multilayer magnetic film as a component of the magnetoresistive device, thereby preventing deterioration of magnetic characteristics due to such damages. Specifically disclosed is a method for manufacturing a magnetoresistive device, which includes processing a multilayer magnetic film by performing a reactive ion etching on a substrate which is provided with the multilayer magnetic film as a component of the magnetoresistive device. This method for manufacturing a magnetoresistive device includes irradiating the multilayer magnetic film with an ion beam after the reactive ion etching.Type: GrantFiled: September 13, 2006Date of Patent: September 24, 2013Assignee: Canon Anelva CorporationInventors: Naoki Watanabe, Yoshimitsu Kodaira, David D. Djayaprawira, Hiroki Maehara
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Patent number: 8536060Abstract: A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.Type: GrantFiled: May 10, 2012Date of Patent: September 17, 2013Assignee: United Microelectronics Corp.Inventors: Yen-Chu Chen, Teng-Chun Tsai, Chien-Chung Huang, Keng-Jen Liu
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Patent number: 8536061Abstract: According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).Type: GrantFiled: March 11, 2011Date of Patent: September 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hisataka Hayashi, Yusuke Kasahara, Tsubasa Imamura
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Patent number: 8535443Abstract: A system of gas lines for a processing chamber and a method of forming a gas line system for a processing chamber are provided. The system of gas lines includes electropolished multi-way valves that connect electropolished linear gas lines. By using multi-way valves rather than tee-fittings and electropolishing the linear gas lines, the nucleation of contaminating particles in the system of gas lines may be reduced.Type: GrantFiled: July 24, 2006Date of Patent: September 17, 2013Assignee: Applied Materials, Inc.Inventors: Wei Ti Lee, Ted Guo, Steve H. Chiao, Alan A. Ritchie
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Patent number: 8535551Abstract: A plasma etching method includes plasma-etching a silicon oxide layer through a mask using a process gas, the process gas containing oxygen gas and a fluorohydrocarbon shown by the formula (1), CxHyFz, wherein x is an integer from 4 to 6, y is an integer from 1 to 4, and z is a positive integer, provided that (y+z) is 2x or less. A contact hole having a very small diameter and a high aspect ratio can be formed in a substantially vertical shape without necking by plasma-etching the silicon oxide layer using a single process gas.Type: GrantFiled: September 26, 2008Date of Patent: September 17, 2013Assignee: Zeon CorporationInventors: Takefumi Suzuki, Tatsuya Sugimoto, Masahiro Nakamura
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Patent number: 8535549Abstract: A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The hardmask is removed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.Type: GrantFiled: July 19, 2011Date of Patent: September 17, 2013Assignee: Lam Research CorporationInventors: Qian Fu, Ce Qin, Hyun-Yong Yu
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Publication number: 20130233828Abstract: An atmospheric plasma irradiation unit has a discharge tube for ejecting a primary plasma formed of an inductively coupled plasma of an inert gas and a mixer for generating a secondary plasma formed of a mixed gas plasmanized by collisions of the primary plasma with a mixed gas region of a second inert gas and a reactive gas. The discharge tube and the mixer are included in a plasma head. A moving unit moves the plasma head so that an irradiation area of the secondary plasma to an object is moved on a circular or other-shaped locus.Type: ApplicationFiled: November 8, 2011Publication date: September 12, 2013Inventors: Masashi Matsumori, Shigeki Nakatsuka, Teppei Kojio
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Patent number: 8529783Abstract: A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, maintaining the focus ring at a temperature no greater than the substrate temperature during etching and cleaning the substrate using a two step plasma cleaning sequence that includes suspending the substrate above the chuck.Type: GrantFiled: March 30, 2010Date of Patent: September 10, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Ming Chen, Chun-Li Chou, Chao-Cheng Chen, Hun-Jan Tao
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Publication number: 20130228550Abstract: There is provided dry etching apparatus including a stage on which a wafer is placed, an antenna electrode, a high frequency power supply, a shower plate, and an RF bias power supply. Further, a bias path controller is provided on the side of the antenna electrode. The bias path controller resonates in series with the static reactance formed by the shower plate with respect to the frequency of the RF bias. Then, the bias path controller changes and grounds the impedance by the variable inductive reactance. With this mechanism, highly uniform etching can be achieved even if a shower plate of quartz is used for corrosive gases.Type: ApplicationFiled: August 9, 2012Publication date: September 5, 2013Applicant: Hitachi High-Technologies CorporationInventors: Masahito MORI, Masaru Izawa, Katsushi Yagi
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Patent number: 8524094Abstract: The object of the present invention is to provide a masking material for dry etching, which is suitable for fine processing of a magnetic film as thin as a few nm such as NiFe or CoFe constituting a TMR film and capable of simplifying the process for producing a TMR element and reducing production costs related to facilities and materials. This object was solved by a masking material for dry etching of a magnetic material by using a mixed gas of carbon monoxide and a nitrogenous compound as etching gas, which comprises a metal (tantalum, tungsten, zirconium or hafnium) with a melting or boiling point increasing upon conversion thereof into a nitride or carbide.Type: GrantFiled: July 16, 2008Date of Patent: September 3, 2013Assignees: National Institute for Materials Science, Japan Science and Technology Corporation, Anelva CorporationInventors: Isao Nakatani, Kimiko Mashimo, Naoko Matsui
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Patent number: 8524101Abstract: The present invention provides a method for manufacturing a semiconductor device. In the method, a connection hole such as a via hole is formed in an interlayer insulating film by plasma etching with high etching uniformity regardless of the array density of connection holes. In the method, an upper layer film having a mask pattern is formed on the interlayer insulating film present on a substrate. A gas required for dehydration is then supplied to the substrate under the condition that an upper surface of the interlayer insulating film is exposed in order to remove moisture from the interlayer insulating film. A portion of the interlayer insulating film is etched to form a connection hole in which an electrical connection portion is to be embedded.Type: GrantFiled: June 9, 2008Date of Patent: September 3, 2013Assignee: Tokyo Electron LimitedInventors: Yuki Chiba, Shigeru Tahara
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Patent number: 8524112Abstract: Elemental fluorine and carbonyl fluoride are suitable etchants for producing microelectromechanical devices (“MEMS”). They are preferably applied as mixtures with nitrogen and argon. If applied in Bosch-type process, C4F6 is a highly suitable passivating gas.Type: GrantFiled: December 16, 2008Date of Patent: September 3, 2013Assignee: Solvay Fluor GmbHInventor: Marcello Riva
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Patent number: 8524102Abstract: An ashing device and ashing method that can positively remove resist from a wafer while preventing degradation of the film material properties of exposed porous Low-K film on the wafer. The ashing device of the present invention introduces a gas to a dielectric plasma generating chamber 14, excites said gas to generate a plasma, and performs plasma processing using said gas plasma on a processing work S in use of a Low-K film. The ashing gas introduced from a gas regulator 20 is an inert gas to which H2 has been added. The configuration is formed so that plasma is generated from the gas blend, and the resist is removed by the hydrogen radicals generated.Type: GrantFiled: February 21, 2011Date of Patent: September 3, 2013Assignee: Shibaura Mechatronics CorporationInventor: Katsuhiro Yamazaki
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Patent number: 8524606Abstract: Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.Type: GrantFiled: January 25, 2011Date of Patent: September 3, 2013Assignees: International Business Machines Corporation, JSR CorporationInventors: Leslie Charns, John M. Cotte, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
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Publication number: 20130224442Abstract: A nano-structured block copolymer that includes a self-assembled block copolymer disposed on a substrate, wherein the block copolymer includes a plurality of block structural units, and at least two block structural units have a solubility parameter difference of greater than or equal to about 5 megaPascal1/2.Type: ApplicationFiled: September 26, 2012Publication date: August 29, 2013Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, SAMSUNG ELECTRONICS CO., LTD.Inventors: Mi-Jeong KIM, Yeon-Sik JUNG, Woon-Ik PARK, Jae-Won JEONG
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Patent number: 8518725Abstract: A method for processing a silicon substrate includes providing a combination of a first silicon substrate, a second silicon substrate, and an intermediate layer including a plurality of recessed portions, which is provided between the first silicon substrate and the second silicon substrate, forming a first through hole that goes through the first silicon substrate by executing etching of the first silicon substrate on a surface of the first silicon substrate opposite to a bonding surface with the intermediate layer by using a first mask, and exposing a portion of the intermediate layer corresponding to the plurality of recessed portions of the intermediate layer, forming a plurality of openings on the intermediate layer by removing a portion constituting a bottom of the plurality of recessed portions, and forming a second through hole that goes through the second silicon substrate by executing second etching of the second silicon substrate by using the intermediate layer on which the plurality of openings arType: GrantFiled: January 13, 2011Date of Patent: August 27, 2013Assignee: Canon Kabushiki KaishaInventors: Atsunori Terasaki, Masahiko Kubota, Ryoji Kanri, Yoshiyuki Fukumoto
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Patent number: 8518275Abstract: Methods for fabricating sub-lithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.Type: GrantFiled: February 14, 2012Date of Patent: August 27, 2013Assignee: Micron Technology, Inc.Inventors: Dan B. Millward, Donald Westmoreland
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Patent number: 8518282Abstract: A method for etching features of different aspect ratios in a tungsten containing layer is provided. An etch gas is provided containing a tungsten etch component and a deposition component. A plasma is formed from the provided etch gas. A tungsten containing layer patterned with wide and narrow features is etched with the provided plasma.Type: GrantFiled: November 13, 2008Date of Patent: August 27, 2013Assignee: Lam Research CorporationInventors: Wonchul Lee, Qian Fu, Shenjian Liu, Bryan Pu
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Patent number: 8518283Abstract: The present invention relates to a plasma etching method in which a special area for detecting an end point needs not to be set and an equipment therefor. At an etching step of forming SF6 gas into plasma to etch an etching ground on a Si film, the step is configured by two steps of: a large-amount supply step of supplying a large amount of SF6 gas; and a small-amount supply step of supplying a small amount of SF6 gas. An end-point detecting processor 34 measures an emission intensity of Si or SiFx in the plasma at the small-amount supply step, and determines that an etching end point is reached when the measured emission intensity becomes equal to or less than a previously set reference value.Type: GrantFiled: July 27, 2007Date of Patent: August 27, 2013Assignee: SPP Technologies Co., Ltd.Inventors: Takashi Yamamoto, Masahiko Tanaka, Yoshiyuki Nozawa, Shoichi Murakami
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Publication number: 20130213935Abstract: Methods for processing a substrate are provided herein. In some embodiments, a method of etching a dielectric layer includes generating a plasma by pulsing a first RF source signal having a first duty cycle; applying a second RF bias signal having a second duty cycle to the plasma; applying a third RF bias signal having a third duty cycle to the plasma, wherein the first, second, and third signals are synchronized; adjusting a phase variance between the first RF source signal and at least one of the second or third RF bias signals to control at least one of plasma ion density non-uniformity in the plasma or charge build-up on the dielectric layer; and etching the dielectric layer with the plasma.Type: ApplicationFiled: March 25, 2013Publication date: August 22, 2013Applicant: APPLIED MATERIALS, INC.Inventor: APPLIED MATERIALS, INC.
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Publication number: 20130213934Abstract: Methods and apparatus for processing a substrate in a multi-frequency plasma processing chamber are disclosed. The base RF signal pulses between a high power level and a low power level. Each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined power level and a second predefined power level as the base RF signal pulses. Alternatively or additionally, each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined RF frequency and a second predefined RF frequency as the base RF signal pulses. Techniques are disclosed for ascertaining in advance of production time the first and second predefined power levels and/or the first and second predefined RF frequencies for the non-base RF signals.Type: ApplicationFiled: June 22, 2012Publication date: August 22, 2013Inventors: John C. Valcore, JR., Bradford J. Lyndaker
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Patent number: 8513127Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.Type: GrantFiled: January 25, 2011Date of Patent: August 20, 2013Assignees: International Business Machines Corporation, JSR CorporationInventors: Josephine B. Chang, Leslie Charns, Jason E. Cummings, Michael A. Guillorn, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
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Patent number: 8512584Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.Type: GrantFiled: July 26, 2011Date of Patent: August 20, 2013Assignee: Texas Instruments IncorporatedInventor: Darwin Rusli
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Patent number: 8513125Abstract: A method for manufacturing a device comprising a structure with nanowires based on a semiconducting material such as Si and another structure with nanowires based on another semiconducting material such as SiGe, and is notably applied to the manufacturing of transistors.Type: GrantFiled: August 30, 2010Date of Patent: August 20, 2013Assignee: Commissariat a l'energie atomique et aux alternativesInventors: Emeline Saracco, Jean-Francois Damlencourt, Michel Heitzmann
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Patent number: 8513097Abstract: Disclosed is a plasma processing device that provides an object to be treated with plasma treatment. A wafer as an object to be treated, which is attached on the upper surface of adhesive sheet held by a holder frame, is mounted on a stage. In a vacuum chamber that covers the stage therein, plasma is generated, by which the wafer mounted on the stage undergoes plasma treatment. The plasma processing device contains a cover member made of dielectric material. During the plasma treatment on the wafer, the holder frame is covered with a cover member placed at a predetermined position above the stage, at the same time, the wafer is exposed from an opening formed in the center of the cover member.Type: GrantFiled: October 9, 2008Date of Patent: August 20, 2013Assignee: Panasonic CorporationInventor: Tetsuhiro Iwai
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Patent number: 8512582Abstract: A method of patterning a substrate in accordance with an embodiment of the invention includes forming a plurality of openings within at least one of photoresist and amorphous carbon. The openings are of common outermost cross sectional shape relative one another. Individual of the openings have at least one lateral open dimension having a degree of variability among the plurality. The photoresist with the plurality of openings is exposed to/treated with a plasma effective to both increase the lateral open size of the openings and at least reduce the degree of variability of said at least one open dimension among the openings. Other aspects and implementations are contemplated.Type: GrantFiled: September 15, 2008Date of Patent: August 20, 2013Assignee: Micron Technology, Inc.Inventors: Mark Kiehlbauch, Brett W. Busch, Tuman Earl Allen
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Publication number: 20130206725Abstract: Disclosed are methods and associated apparatus for depositing layers of material on a substrate (e.g., a semiconductor substrate) using ionized physical vapor deposition (iPVD). Also disclosed are methods and associated apparatus for plasma etching (e.g., resputtering) layers of material on a semiconductor substrate.Type: ApplicationFiled: March 16, 2010Publication date: August 15, 2013Inventors: Karl Leeser, Ishtak Karim, Alexandre de Chambrier, Liqi Wu, Chunming Zhou
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Publication number: 20130206720Abstract: Device for generating a plasma discharge near a substrate for patterning the surface of the substrate, comprising a first electrode having a first discharge portion and a second electrode having a second discharge portion, a high voltage source for generating a high voltage difference between the first and the second electrode, and positioning means for positioning the first electrode with respect to the substrate. The device is further provided with an intermediate structure that is, in use, arranged in between the first electrode and the substrate while allowing for positioning the first electrode with respect to the substrate.Type: ApplicationFiled: February 17, 2010Publication date: August 15, 2013Applicant: VISION DYNAMICS HOLDING B.V.Inventors: Paulus Petrus Maria Blom, Alquin Alphons Elisabeth Stevens, Laurentia Johanna Huijbregts, Hugo Anton Marie De Haan, Antonius Hubertus Van Schijndel, Edwin Te Sligte, Nicolaas Cornelis Josephus Van Hijningen, Tom Huiskamp
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Patent number: 8506834Abstract: The invention provides a dry etching method for processing a wafer having an Ru film formed on a thick Al2O3 film to be used for a magnetic head, capable of realizing high selectivity. In the etching of a wafer having disposed on an NiCr film 15 an Al2O3 film 14, an Ru film 13, an SiO2 film 12 and a resist mask 11, the Ru film 13 is etched via plasma using a processing gas containing Cl2 and O2 (FIG. 1(c)), and thereafter, the Ru film 13 is used as a mask to etch the Al2O3 film 14 via plasma using a gas mixture mainly containing BCl3 and also containing Cl2 and Ar (FIG. 1(d)).Type: GrantFiled: January 30, 2008Date of Patent: August 13, 2013Assignee: Hitachi High-Technologies CorporationInventors: Kentaro Yamada, Takeshi Shimada, Kotaro Fujimoto
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Patent number: 8501629Abstract: A method of etching silicon-containing material is described and includes a SiConi™ etch having a greater or lesser flow ratio of hydrogen compared to fluorine than that found in the prior art. Modifying the flow rate ratios in this way has been found to reduce roughness of the post-etch surface and to reduce the difference in etch-rate between densely and sparsely patterned areas. Alternative means of reducing post-etch surface roughness include pulsing the flows of the precursors and/or the plasma power, maintaining a relatively high substrate temperature and performing the SiConi™ in multiple steps. Each of these approaches, either alone or in combination, serve to reduce the roughness of the etched surface by limiting solid residue grain size.Type: GrantFiled: December 23, 2009Date of Patent: August 6, 2013Assignee: Applied Materials, Inc.Inventors: Jing Tang, Nitin Ingle, Dongqing Yang
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Patent number: 8501627Abstract: A method for etching a dielectric layer is provided. The dielectric layer is disposed over a substrate and below a patterned mask having a line-space pattern. The method includes (a) providing an etchant gas comprising CF4, COS, and an oxygen containing gas, (b) forming a plasma from the etchant gas, and (c) etching the dielectric layer into the line-space pattern through the mask with the plasma from the etchant gas. The gas flow rate of CF4 may have a ratio greater than 50% of a total gas flow rate of all reactive gas components. The gas flow rate of COS may be between 1% and 50%. The method reduces bowing in etching of the dielectric layer by adding COS to the etchant gas.Type: GrantFiled: September 16, 2008Date of Patent: August 6, 2013Assignee: Lam Research CorporationInventors: Kyeong-Koo Chi, Jonathan Kim
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Patent number: 8501024Abstract: The present invention provides a method of fabricating at least one single layer hexagonal boron nitride (h-BN). In an exemplary embodiment, the method includes (1) suspending at least one multilayer boron nitride across a gap of a support structure and (2) performing a reactive ion etch upon the multilayer boron nitride to produce the single layer hexagonal boron nitride suspended across the gap of the support structure. The present invention also provides a method of fabricating single layer hexagonal boron nitride. In an exemplary embodiment, the method includes (1) providing multilayer boron nitride suspended across a gap of a support structure and (2) performing a reactive ion etch upon the multilayer boron nitride to produce the single layer hexagonal boron nitride suspended across the gap of the support structure.Type: GrantFiled: September 30, 2010Date of Patent: August 6, 2013Assignee: The Regents of the University of CaliforniaInventor: Alexander K. Zettl
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Patent number: 8501630Abstract: A method for selectively etching a substrate is described. The method includes preparing a substrate comprising a silicon nitride layer overlying a silicon-containing contact region, and patterning the silicon nitride layer to expose the silicon-containing contact region using a plasma etching process in a plasma etching system. The plasma etching process uses a process composition having as incipient ingredients a process gas containing C, H and F, and a non-oxygen-containing additive gas, wherein the non-oxygen-containing additive gas includes H, or C, or both H and C, and excludes a halogen atom.Type: GrantFiled: September 28, 2010Date of Patent: August 6, 2013Assignee: Tokyo Electron LimitedInventors: Andrew W. Metz, Hongyun Cottle
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Patent number: 8501020Abstract: A method for making a three-dimensional nano-structure array includes following steps. First, a substrate is provided. Next, a mask is formed on the substrate. The mask is a monolayer nanosphere array or a film defining a number of holes arranged in an array. The mask is then tailored and simultaneously the substrate is etched by the mask. Lastly, the mask is removed.Type: GrantFiled: December 16, 2010Date of Patent: August 6, 2013Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Zhen-Dong Zhu, Qun-Qing Li, Shou-Shan Fan
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Patent number: 8497210Abstract: A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface.Type: GrantFiled: January 24, 2011Date of Patent: July 30, 2013Assignees: International Business Machines Corporation, JRS CorporationInventors: Leslie Charns, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
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Publication number: 20130186858Abstract: Etching is performed through the following process. A substrate is loaded into a processing chamber and mounted on a mounting table therein. Then, in the state where a ring member at least a surface of which is made of a same material as a main component of an etching target film is provided to surround the substrate, a processing gas is injected in a shower-like manner from a gas supply unit oppositely facing the substrate and the etching target film is etched by using a plasma of the processing gas; and evacuating the inside of the processing chamber through an exhaust path. Through this process, unbalanced distribution of plasma active species in the vicinity of a circumferential edge portion of the substrate can be suppressed.Type: ApplicationFiled: July 20, 2012Publication date: July 25, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Ayuta SUZUKI, Songyun Kang, Tsuyoshi Moriya, Nobutoshi Terasawa, Yoshiaki Okabe
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Patent number: 8492285Abstract: A dry etching method for texturing a surface of a substrate is disclosed. The method includes performing a first dry etching onto the surface of the substrate thereby forming a surface texture with spikes and valleys, the first dry etching comprising etching the surface of the substrate in a plasma comprising fluorine (F) radicals and oxygen (O) radicals, wherein the plasma comprises an excess of oxygen (O) radicals. The method may further include performing a second dry etching onto the surface texture thereby smoothening the surface texture, the second dry etching comprising chemical isotropic etching the surface texture, obtained after the first dry etching, in a plasma comprising fluorine (F) radicals, wherein the spikes are etched substantially faster than the valleys.Type: GrantFiled: September 15, 2011Date of Patent: July 23, 2013Assignee: IMECInventor: Boon Teik Chan
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Patent number: 8491803Abstract: A method of hydrophobizing a frontside surface of an integrated circuit. The method includes the steps of: (a) depositing a hydrophobic polymeric layer onto the frontside surface; (b) depositing a protective metal film onto the hydrophobic polymeric layer; (c) depositing a sacrificial material onto the metal film; (d) patterning the sacrificial material; (e) etching through the metal film, the hydrophobic polymeric layer and the frontside surface; (f) performing MEMS processing steps on a backside of the integrated circuit; (g) subjecting the integrated circuit to an oxidizing plasma, wherein the metal film protects the hydrophobic polymeric layer from the oxidizing plasma; and (h) removing the protective metal film to provide an integrated circuit having a relatively hydrophobic patterned frontside surface.Type: GrantFiled: August 17, 2011Date of Patent: July 23, 2013Assignee: Zamtec LtdInventors: Gregory John McAvoy, Emma Rose Kerr, Kia Silverbrook
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Patent number: 8491805Abstract: A semiconductor device manufacturing method includes a plasma etching step for etching an etching target film formed on a substrate accommodated in a processing chamber. In the plasma etching step, a processing gas including a gaseous mixture containing predetermined gases is supplied into the processing chamber, and a cycle including a first step in which a flow rate of at least one of the predetermined gases is set to a first value during a first time period and a second step in which the flow rate thereof is set to a second value that is different from the first value during a second time period is repeated consecutively at least three times without removing a plasma. The first time period and the second time period are set to about 1 to 15 seconds.Type: GrantFiled: February 2, 2011Date of Patent: July 23, 2013Assignee: Tokyo Electron LimitedInventors: Masato Kushibiki, Eiichi Nishimura
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Patent number: 8491799Abstract: A method for forming a magnetic tunnel junction cell includes forming a pinning layer, a pinned layer, a dielectric layer and a free layer over a first electrode, forming a second electrode on the free layer, etching the free layer and the dielectric layer using the second electrode as an etch barrier to form a first pattern, forming a prevention layer on a sidewall of the first pattern, and etching the pinned layer and the pinning layer using the second electrode and the prevention layer as an etch barrier to form a second pattern.Type: GrantFiled: June 30, 2008Date of Patent: July 23, 2013Assignee: Hynix Semiconductor Inc.Inventor: Jin-Ki Jung
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Patent number: 8492287Abstract: A silicon-containing film on a substrate is subjected to a plasma process using a process gas containing fluorine and carbon, and is thereafter subjected to plasma process using an ammonia gas, whereby ammonium silicofluoride having toxicity and hygroscopic property is adhered to the substrate. The harmful ammonium silicofluoride is removed by the inventive method. After conducting the plasma process using an ammonia gas, the substrate is heated to a temperature not lower than the decomposition temperature of the ammonium silicofluoride to decompose the ammonium silicofluoride in a process container in which the plasma process was conducted, or in a process container connected with the processing vessel which the plasma process was conducted therein and is isolated from a clean room atmosphere.Type: GrantFiled: May 2, 2011Date of Patent: July 23, 2013Assignee: Tokyo Electron LimitedInventor: Shigeru Tahara
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Publication number: 20130180953Abstract: The present invention is to achieve a reduction both in size of a plasma processing apparatus and an installation area thereof. A dry etching apparatus includes a stock unit that includes a cassette storing a tray that can be conveyed and that stores substrates. In a conveying unit storing a conveying apparatus of the tray, a rotary stage is provided. Rotational angular position adjustment of the tray is performed by rotating the rotary stage placed on the tray before being subjected to dry etching and detecting a notch by a notch detecting sensor.Type: ApplicationFiled: March 26, 2012Publication date: July 18, 2013Inventor: Tetsuhiro Iwai