Using Plasma Patents (Class 216/67)
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Patent number: 8771536Abstract: A method of etching exposed silicon-and-carbon-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-carbon-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-carbon-containing material from the exposed silicon-and-carbon-containing material regions while very slowly removing other exposed materials. The silicon-and-carbon-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.Type: GrantFiled: October 24, 2011Date of Patent: July 8, 2014Assignee: Applied Materials, Inc.Inventors: Jingchun Zhang, Anchuan Wang, Nitin K. Ingle, Yunyu Wang, Young Lee
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Patent number: 8764907Abstract: A method for servicing a plasma processing system. The plasma processing system may include a plasma chamber. The plasma chamber may include a top piece and a bottom piece, wherein the top piece may be disposed above the bottom piece. The method may include using a robot device to control a lift mechanism to lift the top piece from the bottom piece. The method may also include extending a first member of the robot device into the top piece to perform a first set of tasks according to a first set of service procedures. The method may also include extending a second member of the robot device into the bottom piece to perform a second set of tasks according to a second set of service procedures.Type: GrantFiled: September 29, 2009Date of Patent: July 1, 2014Assignee: Lam Research CorporationInventor: Andrew D. Bailey, III
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Patent number: 8764993Abstract: A method of making a porous SiOC membrane is provided. The method comprises disposing a SiOC layer on a porous substrate, and etching the SiOC layer to form through pores in the SiOC layer. A porous SiOC membrane having a network of pores extending through a thickness of the membrane is provided.Type: GrantFiled: April 3, 2008Date of Patent: July 1, 2014Assignee: General Electric CompanyInventors: Atanu Saha, Salil Mohan Joshi, An-Ping Zhang
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Patent number: 8759227Abstract: A method for processing a target object includes arranging a first electrode and a second electrode for supporting the target object in parallel to each other in a processing chamber and processing the target object supported by the second electrode by using a plasma of a processing gas supplied into the processing chamber, the plasma being generated between the first electrode and the second electrode by applying a high frequency power between the first electrode and the second electrode. The target object includes an organic film and a photoresist layer formed on the organic film. The processing gas contains H2 gas, and the organic film is etched by a plasma containing H2 by using the photoresist layer as a mask while applying a negative DC voltage to the first electrode.Type: GrantFiled: September 7, 2010Date of Patent: June 24, 2014Assignee: Tokyo Electron LimitedInventors: Kazuki Narishige, Kazuo Shigeta
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Patent number: 8758637Abstract: An apparatus of removing coatings of a line-shaped body of the invention includes a non-equilibrium atmospheric pressure plasma source with radicals controlled, having a plasma generating gas, a microwave, a micro gap; a line-shaped body holding portion for holding the line-shaped body within a range of 2 to 3 mm from an electrode to generate a plasma jet; and a moving stage for relatively moving the line-shaped body in the longitudinal direction thereof.Type: GrantFiled: September 30, 2008Date of Patent: June 24, 2014Assignees: The Furukawa Electric Co., Ltd.Inventors: Takeshi Hirayama, Imei Shu, Sadayuki Toda, Hisashi Koaizawa, Masaru Hori
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Patent number: 8760807Abstract: A method fabricates a magnetic transducer having a nonmagnetic layer and an ABS location corresponding to an ABS. Etch stop and nonmagnetic etchable layers are provided. A side shield layer is provided between the ABS location and the etch stop and etchable layers. A pole trench is formed in the side shield and etchable layers. The pole trench has a pole tip region in the side shield layer and a yoke region in the etchable layer. A nonmagnetic side gap layer, at least part of which is in the pole trench, is provided. A remaining portion of the pole trench has a location and profile for a pole and in which at least part of the pole is formed. A write gap and trailing shield are provided. At least part of the write gap is on the pole. At least part of the trailing shield is on the write gap.Type: GrantFiled: September 28, 2012Date of Patent: June 24, 2014Assignee: Western Digital (Fremont), LLCInventors: Jinqiu Zhang, Ying Hong, Feng Liu, Zhigang Bai
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Publication number: 20140166616Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber, a remote plasma source, and a showerhead. Inert gas ports within the showerhead assembly can be used to alter the concentration and energy of reactive radical or reactive neutral species generated by the remote plasma source in different regions of the showerhead. This allows the showerhead to be used to apply a surface treatment to different regions of the surface of a substrate. Varying parameters such as the remote plasma parameters, the inert gas flows, pressure, and the like allow different regions of the substrate to be treated in a combinatorial manner.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Applicant: INTERMOLECULAR, INC.Inventors: Sunil Shanker, Tony P. Chiang, Chi-I Lang, Sandip Niyogi
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Publication number: 20140166617Abstract: A method of etching exposed titanium oxide on heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flawed into a substrate processing region where the plasma effluents may combine with a nitrogen-containing precursor such as an amine (N:) containing precursor. Reactants thereby produced etch, the patterned heterogeneous structures with high titanium oxide selectivity while the substrate is at elevated temperature. Titanium oxide etch may alternatively involve supplying a fluorine-containing precursor and a source of nitrogen-and-hydrogen-containing precursor to the remote plasma. The methods may be used to remove titanium oxide while removing little or no low-K dielectric, polysilicon, silicon nitride or titanium nitride.Type: ApplicationFiled: March 8, 2013Publication date: June 19, 2014Applicant: Applied Materials, Inc.Inventors: Zhijun Chen, Seung Park, Mikhail Korolik, Anchuan Wang, Nitin K. Ingle
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Publication number: 20140166618Abstract: A system and method for reactive ion etching (RIE) system of a material is provided. The system includes a plasma chamber comprising a plasma source and a gas inlet, a diffusion chamber comprising a substrate holder for supporting a substrate with a surface comprising the material and a gas diffuser, and a source of a processing gas coupled to the gas diffuser. In the system and method, at least one radical of the processing gas is reactive with the material to perform etching of the material, the gas diffuser is configured to introduce the processing gas into the processing region, and the substrate holder comprises an electrode that can be selectively biased to draw ions generated by the plasma source into the processing region to interact with the at least one processing gas to generate the at least one radical at the surface.Type: ApplicationFiled: October 14, 2013Publication date: June 19, 2014Applicant: THE PENN STATE RESEARCH FOUNDATIONInventors: Srinivas TADIGADAPA, Gokhan HATIPOGLU
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Patent number: 8753526Abstract: The present application relates to a porous thin film having holes, wherein the holes are formed in the top part and/or the bottom part of the thin film and the holes are linked to the pores of the thin film; and the present invention also relates to a production method for a porous thin film having holes, comprising the use of a particle alignment layer as a mold.Type: GrantFiled: August 9, 2011Date of Patent: June 17, 2014Assignee: Industry-University Cooperation Foundation Sogang UniversityInventors: Kyung Byung Yoon, Hyun Sung Kim, Myunpyo Hong, Na Pi Ha
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Patent number: 8754527Abstract: A method of fabricating a semiconductor structure having a borderless contact, the method including providing a first semiconductor device adjacent to a second semiconductor device, the first and second semiconductor devices being formed on a semiconductor substrate, depositing a non-conductive liner on top of the semiconductor substrate and the first and second semiconductor devices, depositing a contact level dielectric layer on top of the non-conductive liner, etching a contact hole in the contact-level dielectric between the first semiconductor device and the second semiconductor device, and selective to the non-conductive liner, converting a portion of the non-conductive liner exposed in the contact hole into a conductive liner; and forming a metal contact in the contact hole.Type: GrantFiled: July 31, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Rahhavasimhan Sreenivasan
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Publication number: 20140162338Abstract: The invention relates to a special plasma source designated as a plasma intractor (PI) for producing a cold, homogeneous plasma under atmospheric pressure conditions, which plasma source can be used advantageously to excite and control reactive processes in flowing media. The device according to the invention is characterized in that the device comprises at least 6 elongated electrodes (2) and a molded body (1) made of insulating material, the molded body (1) being provided with an elongated cylindrical cavity (7) and with additional holes, which are guided parallel to the cavity (7) and arranged symmetrical to the axis of the cavity and equidistant to one another, and the electrodes (2) are embedded in holes of the molded body (1) and are connected to an AC high-voltage supply in such a way that the polarities of respective adjacent electrodes are opposite in each phase of the voltage period.Type: ApplicationFiled: May 29, 2012Publication date: June 12, 2014Applicant: Leibniz-Institut fuer Plasmaforschung und Technologie e.V.Inventors: Jan Schaefer, Stefan Horn, Ronny Brandenburg, Ruediger Foest, Manfred Stieber, Klaus-Dieter Weltmann
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Publication number: 20140151333Abstract: A plasma deposition chamber is disclosed. A substrate support for supporting a surface to be processed is in the chamber. A processing head including an array of plasma microchambers is also in the chamber. Each of the plasma microchambers includes an open side disposed over at least a first portion of the surface to be processed. The open side has an area less than an entire area of the surface to be processed. A process gas source is coupled to the chamber to provide a process gas the array of plasma microchambers. A radio frequency power supply is connected to at least one electrode of the processing head. The array of plasma microchambers is configured to generate a plasma using the process gas to deposit a layer over the at least first portion of the surface to be processed. A method for performing a plasma deposition is also disclosed.Type: ApplicationFiled: February 10, 2014Publication date: June 5, 2014Applicant: Lam Research CorporationInventors: Richard Gottscho, Rajinder Dhindsa, Mukund Srinivasan
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Publication number: 20140151332Abstract: An apparatus for treating a substrate may include a process chamber. The process chamber may include a reaction space and an opening portion for receiving the substrate into the reaction space. The apparatus may further include a dielectric layer. The apparatus may further include a plurality of support elements disposed on the dielectric layer and configured to contact a bottom surface of the substrate for supporting the substrate. The plurality of support elements may include a first support element and a second support element immediately neighboring the first support element.Type: ApplicationFiled: July 1, 2013Publication date: June 5, 2014Inventor: Takayuki FUKASAWA
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Publication number: 20140151331Abstract: Methods and apparatus for plasma processing of substrates are provided herein. In some embodiments, a deposition shield for use in processing a substrate having a given width may include a first plate having a first plurality of holes disposed through a thickness of the first plate; and a second plate disposed below the first plate and having a second plurality of holes disposed through a thickness of the second plate, wherein individual holes in the first plurality of holes and the second plurality of holes are not aligned.Type: ApplicationFiled: February 27, 2013Publication date: June 5, 2014Applicant: APPLIED MATERIALS, INC.Inventors: VALENTIN N. TODOROW, MICHAEL D. WILLWERTH, YING-SHENG LIN, DAVID PALAGASHVILI
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Patent number: 8741160Abstract: Disclosed are a method for manufacturing a solar cell by processing a surface of a silicon substrate for a solar cell, a solar cell manufactured by the method, and a substrate processing system for performing the method. The method for manufacturing a solar cell comprises protrusion forming step including wet-etching process and for forming a plurality of minute protrusions on a light receiving surface of a crystalline silicon substrate, and planarization step of planarizing the bottom surface, the opposite surface to the light receiving surface of the substrate during or after the protrusion forming step.Type: GrantFiled: December 20, 2010Date of Patent: June 3, 2014Assignee: Wonik IPS Co., Ltd.Inventor: Byung-Jun Kim
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Patent number: 8742665Abstract: Embodiments of the present invention generally provide a plasma source apparatus, and method of using the same, that is able to generate radicals and/or gas ions in a plasma generation region that is symmetrically positioned around a magnetic core element by use of an electromagnetic energy source. In general, the orientation and shape of the plasma generation region and magnetic core allows for the effective and uniform coupling of the delivered electromagnetic energy to a gas disposed in the plasma generation region. In general, the improved characteristics of the plasma formed in the plasma generation region is able to improve deposition, etching and/or cleaning processes performed on a substrate or a portion of a processing chamber that is disposed downstream of the plasma generation region.Type: GrantFiled: October 15, 2010Date of Patent: June 3, 2014Assignee: Applied Materials, Inc.Inventors: Dmitry Lubomirsky, Jang-Gyoo Yang, Matthew Miller, Jay Pinson, Kien Chuc
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Patent number: 8741165Abstract: An apparatus for etching a dielectric layer contained by a substrate is provided. An etch reactor comprises a top electrode and a bottom electrode. An etch gas source supplies an etch gas into the etch reactor. A first Radio Frequency (RF) source generates a first RF power with a first frequency and supplies the first RF power into the etch reactor, whereas the first frequency is between 100 kilo Hertz (kHz) and 600 kHz. A second RF source generates a second RF power with a second frequency and supplies the second RF power into the etch reactor, whereas the second frequency is at least 10 mega Hertz (MHz).Type: GrantFiled: October 7, 2010Date of Patent: June 3, 2014Assignee: Lam Research CorporationInventors: Bing Ji, Erik A. Edelberg, Takumi Yanagawa
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Publication number: 20140144876Abstract: A plasma etching method using a plasma etching apparatus including a lower electrode and an upper electrode is provided. The plasma etching method includes a first etching step of performing plasma etching using a first process gas and a second etching step of performing the plasma etching using a second process gas. The adhesion of a radical of the second process gas to an object of processing is less than the adhesion of a radical of the first process gas to the object of processing. While alternately repeating a first condition of turning on high-frequency electric power for plasma generation and a second condition of turning off the high-frequency electric power, the second etching step applies a negative direct-current voltage to the upper electrode so that the absolute value of the applied voltage is greater in a period of the second condition than in a period of the first condition.Type: ApplicationFiled: July 30, 2012Publication date: May 29, 2014Applicant: Tokyo Electron LimitedInventors: Akira Nakagawa, Fumio Yamazaki, Hiromi Mochizuki
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Publication number: 20140144877Abstract: One possible embodiment of the invention could be a plasma reactor chamber and method of operating same wherein the plasma reactor chamber comprises a set of chamber walls and a door that when closed seals the plasma reactor chamber air-tight; one or more RF electrodes with at least one RF electrode being a power RF electrode; and a structure that moves one or more specimens proximate to the one or more RF electrodes.Type: ApplicationFiled: November 25, 2013Publication date: May 29, 2014Inventor: Gregory DeLarge
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Patent number: 8734664Abstract: A method of controlling distribution of a plasma parameter in a plasma reactor having an RF-driven electrode and two (or more) counter electrodes opposite the RF driven electrode and facing different portions of the process zones. The method includes providing two (or more) variable reactances connected between respective ones of the counter electrodes and ground, and governing the variable reactances to change distribution of a plasma parameter such as plasma ion density or ion energy.Type: GrantFiled: August 5, 2013Date of Patent: May 27, 2014Assignee: Applied Materials, Inc.Inventors: Yang Yang, Kartik Ramaswamy, Kenneth S. Collins, Steven Lane, Douglas A. Buchberger, Jr., Lawrence Wong, Nipun Misra
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Patent number: 8735291Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).Type: GrantFiled: August 25, 2011Date of Patent: May 27, 2014Assignee: Tokyo Electron LimitedInventors: Alok Ranjan, Akiteru Ko
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Patent number: 8734662Abstract: A method for manufacturing a semiconductor device includes forming a patterned photoresist layer over a substrate, performing a plasma ashing process to the patterned photoresist layer, thereby removing a portion of the patterned photoresist layer, exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone, thereby removing other portions of the patterned photoresist layer, and performing a cleaning of the patterned photoresist layer after exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone.Type: GrantFiled: December 6, 2011Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Rung Hsu, Sung Hsun Wu, Kuo Bin Huang
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Publication number: 20140138356Abstract: A plasma processing apparatus includes a first electrode and a second electrode so arranged in the upper portion of a processing chamber as to face a mounting table, a gas supply unit for supplying a processing gas between the first electrode and the second electrode, a RF power supply unit for applying a RF power between the first electrode and the second electrode for converting the process gas supplied between the electrodes into a plasma, and a gas exhaust unit for evacuating the inside of the processing chamber to a vacuum level from the lower portion of the processing chamber. Since the electron temperature in the plasma is low near a substrate on the mounting table, damage to the substrate caused by the plasma can be suppressed. In addition, since a metal can be used as a material for the processing chamber, the processing chamber can have good temperature controllability.Type: ApplicationFiled: January 27, 2014Publication date: May 22, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Ikuo Sawada, Peter Ventzek, Tatsuro Ohshita, Kazuyoshi Matsuzaki, Songyun Kang
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Publication number: 20140139049Abstract: Methods and apparatus for plasma processing of a substrate to improve process results are proposed. The apparatus pertains to multi-layer segmented electrodes and methods to form and operate such electrodes. The multi-layer segmented electrode includes a first layer comprising a first plurality of electrode segments, whereby electrode segments of the first plurality of electrode segments spatially separated from one another along a first direction. There is also included a second layer comprising a second plurality of electrode segments, whereby the second layer is spatially separated from the first layer along a second direction perpendicular to the first direction and whereby at least two segmented electrodes of the first plurality of electrode segments are individually controllable with respect to one or more electrical parameters.Type: ApplicationFiled: November 29, 2012Publication date: May 22, 2014Applicant: LAM RESEARCH CORPORATIONInventors: Andreas Fischer, Dave Jacob
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Patent number: 8726475Abstract: A method for producing a piezoelectric thin-film resonator includes forming a sacrificial layer on a substrate, performing a plasma treatment on the sacrificial layer so that the surface roughness (Ra) of end surface portions of the sacrificial layer is about 5 nm or less, forming a strip-shaped dielectric film so as to be continuously disposed on the surface of the substrate and the end surface portions and the principal surface of the sacrificial layer, forming a piezoelectric thin-film area including a lower electrode, an upper electrode, and a piezoelectric thin-film disposed therebetween so that a portion of the lower electrode and a portion of the upper electrode surface each other at an area on the dielectric film, the area being disposed on the upper portion of the sacrificial layer, and removing the sacrificial layer to form an air-gap between the substrate and the dielectric film.Type: GrantFiled: September 3, 2008Date of Patent: May 20, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Hidetoshi Fujii, Ryuichi Kubo
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Patent number: 8728335Abstract: A silsesquioxane resin is applied over the patterned photo-resist and cured at the pattern surface to produce a cured silsesquioxane resin on the pattern surface. The uncured silsesquioxane resin layer is then removed leaving the cured silsesquioxane resin on the pattern surface. The cured silsesquioxane resin on horizontal surfaces is removed to expose the underlying photo-resist. This photo-resist is removed leaving a pattern of cured silsesquioxane. Optionally, the new pattern can be transferred into the underlying layer(s).Type: GrantFiled: June 22, 2010Date of Patent: May 20, 2014Assignee: Dow Corning CorporationInventors: Peng-Fei Fu, Eric Scott Moyer, Jason D. Suhr
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Patent number: 8728584Abstract: The invention provides a method for patterning a polymer surface. A polymer layer is formed on a substrate. A conductive grid with a mesh pattern is placed on the polymer layer. The mesh pattern is transferred to the polymer layer by a plasma treatment. The conductive grid is then removed.Type: GrantFiled: October 9, 2009Date of Patent: May 20, 2014Assignee: National Sun Yat-Sen UniversityInventor: Shu-Chen Hsieh
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Patent number: 8728333Abstract: A three step ion beam etch (IBE) sequence involving low energy (<300 eV) is disclosed for trimming a sensor critical dimension (free layer width=FLW) to less than 50 nm. A first IBE step has a steep incident angle with respect to the sensor sidewall and accounts for 60% to 90% of the FLW reduction. The second IBE step has a shallow incident angle and a sweeping motion to remove residue from the first IBE step and further trim the sidewall. The third IBE step has a steep incident angle to remove damaged sidewall portions from the second step and accounts for 10% to 40% of the FLW reduction. As a result, FLW approaching 30 nm is realized while maintaining high MR ratio of over 60% and low RA of 1.2 ohm-?m2. Sidewall angle is manipulated by changing one or more ion beam incident angles.Type: GrantFiled: February 12, 2010Date of Patent: May 20, 2014Assignee: Headway Technologies, Inc.Inventors: Hui-Chuan Wang, Tong Zhao, Min Zheng, Minghui Yu, Min Li, Cherng Chyi Han
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Patent number: 8721905Abstract: A method for forming a minute pattern mask includes forming an etching target layer on a substrate. A convex pattern including a plurality of convex parts is formed on the etching target layer. A resin composition is coated on the convex pattern to form a resin layer including a first region neighboring the convex part and a second region positioned between the neighboring convex parts. The resin layer is ashed or etched to form the plurality of first resin patterns. The plurality of first resin patterns is processed to form a minute pattern mask including a plurality of second resin patterns. The etching target layer is etched using the plurality of second resin patterns as an etch mask to form a minute pattern.Type: GrantFiled: March 27, 2012Date of Patent: May 13, 2014Assignees: Samsung Display Co., Ltd., SNU R & DB FountdationInventors: Se-Hwan Yu, Ji Seon Lee, Yoon Ho Khang, Kahp Yang Suh, Hyoung Sick Um, Jae Jun Chae, Sung Hun Lee
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Patent number: 8721901Abstract: Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material.Type: GrantFiled: October 5, 2007Date of Patent: May 13, 2014Assignee: Micron Technology, Inc.Inventors: Nishant Sinha, Gurtej S. Sandhu
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Patent number: 8721833Abstract: A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated of a ferroelectric material.Type: GrantFiled: February 5, 2012Date of Patent: May 13, 2014Assignee: Tokyo Electron LimitedInventors: Zhiying Chen, Jianping Zhao, Lee Chen, Merritt Funk, Radha Sundararajan
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Patent number: 8721906Abstract: An embodiment of the present inventions provides a method for preconditioning a semiconductor fabrication component using a plasma etching process and an optional enhanced ultrasonic and/or megasonic preconditioning step in order to eliminate the need for a burn-in period typically associated with said components, as well as extend the useful life of the component during its wear-out phase.Type: GrantFiled: June 2, 2009Date of Patent: May 13, 2014Assignee: Poco Graphite, Inc.Inventor: Wayne Hambek
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Patent number: 8721908Abstract: A bevel etcher incorporating a vacuum chuck used for cleaning the bevel edge and for reducing the bending curvature of a semiconductor substrate. The bevel etcher includes a vacuum chuck and a plasma generation unit which energizes process gas into a plasma state. The vacuum chuck includes a chuck body and a support ring. The top surface of the chuck body and inner periphery of the support ring form a vacuum region enclosed by the bottom surface of a substrate mounted on the support ring. A vacuum pump evacuates the vacuum region during operation. The vacuum chuck is operative to hold the substrate in place by the pressure difference between the top and bottom surfaces of the substrate. The pressure difference also generates a bending force to reduce the bending curvature of the substrate.Type: GrantFiled: October 7, 2013Date of Patent: May 13, 2014Assignee: Lam Research CorporationInventors: Andrew D. Bailey, III, Alan M. Schoepp, Gregory Sexton, William S. Kennedy
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Patent number: 8715515Abstract: A sequence of process steps having balanced process times are implemented in sequence of etch chambers coupled linearly and isolated one from the other, resulting in the optimization of island to trench ratio for a patterned media. A biased chemical etching using active etching gas is used to descum and trim the resist patterns. An inert gas sputter etch is performed on the magnetic layers, resulting in the patterned magnetic layer on the disk. A final step of stripping is then performed to remove the residual capping resist and carbon hard mask on top of un-etched magnetic islands. The effective magnetic material remaining on the disk surface can be optimized by adjusting the conditions of chemical etch and sputter etch conditions. Relevant process conditions that may be adjusted include: pressure, bias, time, and the type of gas in each step.Type: GrantFiled: March 23, 2010Date of Patent: May 6, 2014Assignee: Intevac, Inc.Inventors: Houng T. Nguyen, Ren Xu, Michael S. Barnes
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Patent number: 8715472Abstract: A substrate processing method may include forming a plasma; extracting ions from the plasma and accelerating the ions to have uniform or substantially uniform directivity using a grid system; irradiating the ions at a reflector, wherein the reflector includes a plurality of reflecting plates each having a metal plate and an insulating layer on the metal plate, wherein the reflecting plates are parallel or substantially parallel such that the insulating layers are exposed to the ions; reflecting the ions incident on the reflecting plates away from the insulating layers of the reflecting plates; colliding the ions reflected away from the insulating layers with the metal plates to convert the ions into neutral beams; and irradiating the neutral beams onto a substrate to process the substrate.Type: GrantFiled: March 4, 2010Date of Patent: May 6, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Wook Hwang, Chul-Ho Shin
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Patent number: 8715520Abstract: There is provided a substrate processing method capable of etching a layer containing, at least, platinum without using a halogen gas. When etching the platinum-manganese layer on a wafer W by using a tantalum (Ta) layer 38 having a certain pattern shape, a processing gas containing, at least, a carbon monoxide gas, a hydrogen gas, and a rare gas is used, and a ratio of a gas flow rate of the hydrogen gas to a total gas flow rate of the carbon monoxide gas and the hydrogen gas is in a range of from about 50% to about 75%.Type: GrantFiled: March 21, 2012Date of Patent: May 6, 2014Assignee: Tokyo Electron LimitedInventors: Takashi Sone, Eiichi Nishimura
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Patent number: 8709952Abstract: Provided is an etching method capable of etching even a silicon film that is included in a multi-layered structure by using a resist film or an organic film as a mask, and also capable of integrally etching the silicon film and a silicon oxide film disposed under the silicon film. The etching method which etches the multi-layered structure including the silicon oxide film and the silicon film formed on the silicon oxide film, includes: integrally etching the silicon film and the silicon oxide film included in the multi-layered structure by using a resist film or an organic film as an etching mask and using an etching gas containing a CH2F2 gas as an etching gas, when the silicon film and the silicon oxide film in the multi-layered structure are etched.Type: GrantFiled: March 14, 2012Date of Patent: April 29, 2014Assignee: Tokyo Electron LimitedInventor: Aki Akiba
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Patent number: 8709270Abstract: A chamber for combinatorially processing a substrate is provided. The chamber includes a first mask and a second mask that share a common central axis. The first mask and the second mask are independently rotatable around the common central axis. The first mask has a first plurality of radial apertures and the second mask has a second plurality of radial apertures. An axis of the first plurality of radial apertures is offset from an axis of the second plurality of radial apertures. A substrate support that is operable to support a substrate below the first and second masks is included. The substrate support shares the common central axis.Type: GrantFiled: December 13, 2011Date of Patent: April 29, 2014Assignee: Intermolecular, Inc.Inventor: Peter Satitpunwaycha
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Patent number: 8709953Abstract: Ultrathin material layers are plasma etched with an etch system configured for cryogenic cooling of a substrate to reduce the diffusion coefficients of foreign and intrinsic stop layer atoms (e.g., of the bombarded crystal lattice), and further configured for plasma pulsing to reduce the energy of the impinging ions with cryogenic wafer temperatures. Substrate temperatures of ?50° C. or more are employed to reduce the susceptibility of a stop layer material to damage associated with ion impact. Ion energy is reduced to below the threshold where stop layer lattice atoms are displaced or ions are implanted into the bulk lattice. In embodiments, a plasma of an etchant gas having ion energies less than 10 eV are achieved through plasma pulsing, which when directed at the low temperature substrate may controllably etch ultra-thin material layers.Type: GrantFiled: October 17, 2012Date of Patent: April 29, 2014Assignee: Applied Materials, Inc.Inventors: Thorsten Lill, Klaus Schuegraf, Dmitry Lubomirsky
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Publication number: 20140112112Abstract: The invention relates to a method of manufacturing an element comprising the following steps: a) forming a body made of oxide based ceramic; b) exposing at least one portion of the external surface of the body to a reduction reaction, to remove oxygen atoms to a predetermined depth in order to make the at least one portion electrically conductive; c) depositing a metallic material starting from the at least one electrically conductive portion; d) machining the body and/or the metallic material in order to provide the element with an aesthetic finish. The invention concerns the field of timepieces.Type: ApplicationFiled: October 18, 2013Publication date: April 24, 2014Applicant: The Swatch Group Research and Development Ltd.Inventors: Guido PLANKERT, Pierry Vuille
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Publication number: 20140110374Abstract: Embodiments provide a method for removing a dielectric layer from a bottom of a trench while maintaining the dielectric layer on sidewalls of the trench. The method includes etching the dielectric layer at the bottom of the trench and generating a passivation layer on the dielectric layer at an upper portion of the trench by adjusting the conditions of a plasma etch process to a first mode; and a step of etching the dielectric layer at the bottom of the trench and etching the passivation layer at the upper portion of the trench by adjusting the conditions of the plasma etch process to a second mode before the dielectric layer at the bottom of the trench is completely removed.Type: ApplicationFiled: October 19, 2012Publication date: April 24, 2014Applicant: Infineon Technologies AGInventors: Lothar Brencher, Carsten Moritz
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Publication number: 20140110375Abstract: In the present invention, the form in which roughness is formed on the surface of an article being processed through plasma exposure is controlled by varying the frequency for a main voltage applied to two discharge electrodes, a conductive housing and a rod shaped electrode, provided in a plasma generating unit and the frequency for a bias voltage applied between the conductive housing (2) and the article being processed.Type: ApplicationFiled: June 13, 2011Publication date: April 24, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takehito Kobayashi, Noriyuki Ueno, Katsuya Kurachi
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Patent number: 8703001Abstract: A grid assembly for use in an etching system for etching at least a wafer. The grid assembly may include a first grid member, a second grid member, and a third grid member. When the grid assembly is used in etching the wafer, the first grid member may be electrically grounded, the second grid member may be electrically negative relative to the first grid member, and the third grid member may be electrically positive relative to the first grid member. The second grid member may be disposed between the first grid member and the third grid member. The first grid member may be thicker than at least one of the second grid member and the third grid member.Type: GrantFiled: October 2, 2008Date of Patent: April 22, 2014Assignee: Sarpangala Hari Harakeshava HegdeInventor: Hari Hegde
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Patent number: 8703617Abstract: The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer.Type: GrantFiled: February 17, 2011Date of Patent: April 22, 2014Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huaxiang Yin, Qiuxia Xu, Lingkuan Meng, Tao Yang, Dapeng Chen
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Patent number: 8703002Abstract: A plasma processing apparatus includes a first radio frequency (RF) power supply unit for applying a first RF power for generating a plasma from a processing gas to at least one of a first and a second electrode which are disposed facing each other in an evacuable processing chamber. The first RF power supply unit is controlled by a control unit so that a first phase at which the first RF power has a first amplitude for generating a plasma and a second phase at which the first RF power has a second amplitude for generating substantially no plasma are alternately repeated at predetermined intervals.Type: GrantFiled: January 9, 2013Date of Patent: April 22, 2014Assignee: Tokyo Electron LimitedInventors: Tatsuo Matsudo, Shinji Himori, Noriaki Imai, Takeshi Ohse, Jun Abe, Takayuki Katsunuma
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Patent number: 8703000Abstract: A slimming method includes transferring an object to be processed on which a patterned carbon-containing thin film is formed into a process chamber in an oxidation apparatus; and oxidizing and removing the surface of the carbon-containing thin film by an oxidizing gas while supplying moisture into the process chamber, to reduce widths of the protruded portions on the pattern of the carbon-containing thin film.Type: GrantFiled: December 19, 2011Date of Patent: April 22, 2014Assignee: Tokyo Electron LimitedInventors: Jun Sato, Masayuki Hasegawa
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Publication number: 20140106571Abstract: A plasma processing apparatus includes a process chamber housing defining a process chamber, a platen positioned in the process chamber for supporting a workpiece, a source configured to generate plasma in the process chamber, and a biasing system. The biasing system is configured to bias the platen to attract ions from the plasma towards the workpiece during a first processing time interval and configured to bias the platen to repel ions from the platen towards interior surfaces of the process chamber housing during a cleaning time interval. The cleaning time interval is separate from the first processing time interval and occurring after the first processing time interval.Type: ApplicationFiled: October 11, 2012Publication date: April 17, 2014Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Bon-Woong Koo, Richard M. White
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Patent number: 8696921Abstract: In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.Type: GrantFiled: January 15, 2010Date of Patent: April 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Ho Park, Gil-Heyun Choi, Byung-Lyul Park, Jong-Myeong Lee, Zung-Sun Choi, Hye-Kyung Jung
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Patent number: 8697581Abstract: A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications.Type: GrantFiled: July 9, 2008Date of Patent: April 15, 2014Assignee: International Rectifier CorporationInventors: Robert Beach, Paul Bridger