Superlattice Patents (Class 257/15)
  • Patent number: 6130441
    Abstract: By using wafer fusion, various structures for photodetectors and photodetectors integrated with other electronics can be achieved. The use of silicon as a multiplication region and III-V compounds as an absorption region create photodetectors that are highly efficient and tailored to specific applications. Devices responsive to different regions of the optical spectrum, or that have higher efficiencies are created.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: October 10, 2000
    Assignee: The Regents of the University of California
    Inventors: John E. Bowers, Aaron R. Hawkins
  • Patent number: 6104049
    Abstract: A coating of liquid precursor containing a metal is applied to a first electrode, baked on a hot plate in oxygen ambient at a temperature not exceeding 300.degree. C. for five minutes, then RTP annealed at 675.degree. C. for 30 seconds. The coating is then annealed in oxygen or nitrogen ambient at 700.degree. C. for one hour to form a thin film of layered superlattice material with a thickness not exceeding 90 nm. A second electrode is applied to form a capacitor, and a post-anneal is performed in oxygen or nitrogen ambient at a temperature not exceeding 700.degree. C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8.ltoreq.u.ltoreq.1.0, 2.0.ltoreq.v.ltoreq.2.3, and 1.9.ltoreq.w.ltoreq.2.1.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: August 15, 2000
    Assignee: Symetrix Corporation
    Inventors: Narayan Solayappan, Vikram Joshi, Carlos A. Paz de Araujo, Larry D. McMillan, Shinichiro Hayashi, Tatsuo Otsuki
  • Patent number: 6072202
    Abstract: A layer structure for a II-VI compound semiconductor device is formed on a GaAs substrate of III-V compound, wherein lattice mismatching is prevented by a first layer interposed between the GaAs substrate and a II-VI compound semiconductor active layer and made of III-V compound semiconductor including In element as a constituent element thereof. The thickness of the first layer is less than the critical thickness allowing coherent growth. Alternatively, the III-V compound of the first layer has a lattice constant substantially equal to the lattice constant of the GaAs substrate. The first layer may be a superlattice layer.
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: June 6, 2000
    Assignee: NEC Corporation
    Inventor: Koichi Naniwae
  • Patent number: 6060656
    Abstract: A superlattice structure for use in thermoelectric power generation systems includes m layers of a first one of Silicon and Antimony doped Silicon-Germanium alternating with n layers of Silicon-Germanium which provides a superlattice structure having a thermoelectric figure of merit which increases with increasing temperature above the maximum thermoelectric figure of merit achievable for bulk SiGe alloys.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: May 9, 2000
    Assignee: Regents of the University of California
    Inventors: Mildred S. Dresselhaus, Theodore C. Harman, Stephen B. Cronin, Takaaki Koga, Xiangzhong Sun, Kang L. Wang
  • Patent number: 6060743
    Abstract: The semiconductor device comprises a first insulating layer formed on the semiconductor substrate, at least one double-deck semiconductor nanocrystal formed on the first insulating layer, the at least one double-deck semiconductor nanocrystal comprising a first semiconductor nanocrystal and a second semiconductor nanocrystal stacked one upon the other via a second insulating layer, and a third insulating layer selectively formed on the first insulating layer so as to cover the at least one double-deck semiconductor nanocrystal.
    Type: Grant
    Filed: May 20, 1998
    Date of Patent: May 9, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoharu Sugiyama, Tsutomu Tezuka, Riichi Katoh, Atsushi Kurobe, Tetsufumi Tanamoto
  • Patent number: 6060657
    Abstract: A superlattice structure having a relatively high thermoelectric figure of merit and suitable for usage in power generation systems, and in heating and/or cooling applications is described. The superlattice structure includes a first plurality of layers formed from material D.sub.z J.sub.1-z, a second plurality of layers formed from material L.sub.x M.sub.1-x D.sub.z J.sub.1-z and a third plurality of layers formed from material L.sub.x M.sub.1-x D.sub.z J.sub.1-z wherein D is a non-metal chalcogen, and wherein J is a non-metal chalcogen, and wherein L is a group IV metal selected from the group of Pb, Sn, and Ge, and wherein M is a Group IV metal selected from the group of Pb, Sn, and Ge, and wherein D is not the same as J, and wherein L is not the same as M, and wherein 0.ltoreq.x.ltoreq.1 and 0.ltoreq.z.ltoreq.1.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: May 9, 2000
    Assignee: Massachusetts Institute of Technology
    Inventor: Theodore C. Harman
  • Patent number: 6057559
    Abstract: A laser diode for emitting a coherent beam of light in the blue and/or green portions of the spectrum. The laser diode includes a plurality of layers of II-VI semiconductor forming a pn junction, including at least a first light-guiding layer. A short-period strained-layer superlattice (SPSLS) CdZnSe quantum well active layer is positioned within the pn junction. The layers of II-VI semiconductor are supported by a substrate. First and second electrodes on opposite sides of the layers of II-VI semiconductor couple electrical energy to the laser diode.
    Type: Grant
    Filed: January 31, 1995
    Date of Patent: May 2, 2000
    Assignee: 3M Innovative Properties Company
    Inventors: Hwa Cheng, James M. DePuydt, Michael A. Haase, Jun Qiu
  • Patent number: 6057563
    Abstract: Disclosed is a light transparent window layer for light transmitting diodes. The light transparent window layer is formed by growing a plurality of AlGaInP superlattice layers such that the uniformity of current distribution within LED chip can be enhanced, and the size of light-emitting area can be increased. The manufacturing process is also simplified.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: May 2, 2000
    Assignee: Lite-on Electonics, Inc.
    Inventors: Hsi-Ming Chen, Szutsun S. Ou
  • Patent number: 6044100
    Abstract: A VCSEL comprises a pair of multi-layered mirrors forming an optical cavity resonator having its axis perpendicular to the layers of the mirrors, an active region disposed within the resonator, and a current guide for directing pumping current through an aperture to generate stimulated emission of radiation which propagates along the resonator axis. A portion of the radiation forms an output signal which emerges through at least one of the mirrors. The current guide includes a lateral injection structure disposed between one of the mirrors and the current aperture. The lateral injection structure comprises at least one relatively thin, highly doped semiconductor layer, each of the highly doped layer(s) being located at a node of the standing wave of the intracavity radiation, at least one lower doped semiconductor layer disposed adjacent each of the highly doped layers (e.g.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: March 28, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: William Scott Hobson, Daryoosh Vakhshoori
  • Patent number: 6040588
    Abstract: A semiconductor light-emitting device involving the steps of: forming a first semiconductor layer; forming a light-emitting layer of superlattice structure by laminating a barrier layer being made of In.sub.Y1 Ga.sub.1-Y1 N (Y1.gtoreq.0) and a quantum well layer being made of In.sub.Y2 Ga.sub.1-Y1 N (Y2>Y1 and Y2>0) on the first semiconductor layer; and forming a second semiconductor layer on the light-emitting layer, an uppermost barrier layer, which will become an uppermost layer of the light-emitting layer, is made thicker than the other barrier layers. Further, at the time of forming the second semiconductor layer, an upper surface of such uppermost barrier layer is caused to disappear so that the thickness of the uppermost barrier layer becomes substantially equal to those of the other barrier layers.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: March 21, 2000
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Norikatsu Koide, Shinya Asami, Junichi Umezaki, Masayoshi Koike, Shiro Yamasaki, Seiji Nagai
  • Patent number: 6031256
    Abstract: Structure of a wide voltage operation regime double heterojunction bipolar transistor, specifically a modified InGaP/GaAs double heterojunction bipolar transistor featuring a very broad collector-emitter voltage operation range, an invention of high speed, low power consumption and high breakdown voltage rated microwave power transistor. Unique in the incorporation of In.sub.0.49 Ga.sub.0.51 P collector layer, GaAs delta-doping sheet and undoped GaAs spacer in the collector zone. The introduction of a spacer with a delta doping sheet into the effective base-collector heterojunction serves to eliminate potential spike from appearing at base-collector interfacing any more, thus effectively precludes electron blocking effect. In the emitter zone the inventive design comprises a five-period In.sub.0.49 Ga.sub.0.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: February 29, 2000
    Assignee: National Science Council of Republic of China
    Inventors: Wen-Chan Liu, Shiou-Ying Cheng
  • Patent number: 6022749
    Abstract: A method is provided for determining the temperature of a semiconductor fabrication process in which a resistivity versus temperature calibration curve for a superlattice structure is created. A plurality of similar superlattice structures which include alternating layers of a conductor and a semiconductor may be annealed at different temperatures. The resistivity of each superlattice structure may then be measured after the superlattice structures have been cooled to room temperature in order to form the calibration curve. A similar superlattice structure may then be subjected to the temperature at which the semiconductor fabrication process is typically performed, causing the resistivity of the superlattice structure to change. Based on the resulting resistivity of the superlattice structure, the calibration curve may be used to determine the process temperature of the superlattice structure during the fabrication process.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: February 8, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bradley M. Davis, Shengnian Davis Song, Sey-Ping Sun
  • Patent number: 6005259
    Abstract: The invention concerns an InAs/GaSb superlattice infrared detector that is prepared on a GaSb or a GaAs substrate by low pressure organometaleic chemical vapor deposition. The thickness of well and barrier modulated in the superlattice is used to control the wavelength of absorption. As the superlattice is sandwiched by the Si-doped InAs layer, the wavelength of absorption is in the 8.about.14 .mu.m range. As the superlattice is sandwiched by the Zn-doped GaSb layer, the wavelength of absorption is in the 3.about.5 .mu.m range.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: December 21, 1999
    Assignee: National Science Council
    Inventors: Yan-Kuin Su, Shoou-Jinn Chang, Shi-Ming Chen, Chuing-Liang Lin
  • Patent number: 5994639
    Abstract: Thermodynamically metastable skutterudite crystalline-structured compounds are disclosed having preselected stoichiometric compositions and superior and optimizable thermoelectric properties. The compounds are formed at low nucleation temperatures and satisfy the formula:M.sub.1-x M'.sub.4-y Co.sub.y M".sub.12wherein:M=any metal, metalloid, or mixture thereof, except for La, Ce, Pr, Nd, and Eu when x=0, and M'=Fe, Ru, or Os, and M"=Sb, P, or As;M'=Fe, Ru, Os, Rh, or mixture thereof;M"Sb, As, P, Bi, Ge.sub.0.5-w Se.sub.0.5+w, wherein w=0 to 0.5 or mixture thereof;x=0 to 1;y=0 to 4; andwherein M' and/or M" are doped or undoped. These compounds generally have the crystalline structure of a skutterudite, wherein the crystalline structure is cubic with 34 atoms in the unit-cell in the space group Im3. The M".sub.12 atoms occupy unit-cell sites 24(g), the M'.sub.4-y atoms form a cubic sublattice occupying unit-cell sites 8(c), and the M.sub.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: November 30, 1999
    Assignee: The State of Oregon Acting by and Through the State Board of Higher Education on Behalf of the University of Oregon
    Inventors: David C. Johnson, Marc Hornbostel
  • Patent number: 5978397
    Abstract: In a novel tunable semiconductor laser, the lasing transition is a non-resonant tunneling transition, with the frequency of the emitted photon depending on the electrical bias across the multi-period active region of the laser. The laser can be designed to emit in the mid-IR, and can advantageously be used for, e.g., trace gas sensing.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: November 2, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Federico Capasso, Alfred Yi Cho, Jerome Faist, Albert Lee Hutchinson, Carlo Sirtori, Deborah Lee Sivco
  • Patent number: 5960018
    Abstract: Several methods are used in novel ways with newly identified and viable parameters to decrease the peak transition energies of the pseudomorphic InGaAs/GaAs heterostructures. These techniques, taken separately or in combination, suffice to permit operation of light emitting devices at wavelengths of 1.3 .mu.m or greater of light-emitting electro-optic devices. These methods or techniques, by example, include: (1) utilizing new superlattice structures having high In concentrations in the active region, (2) utilizing strain compensation to increase the usable layer thickness for quantum wells with appropriately high In concentrations, (3) utilizing appropriately small amounts of nitrogen (N) in the pseudomorphic InGaAsN/GaAs laser structure, and (4) sue of nominal (111) oriented substrates to increase the usable layer thickness for quantum wells with appropriately high In concentrations.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: September 28, 1999
    Assignee: Picolight Incorporated
    Inventors: Jack L. Jewell, Henryk Temkin
  • Patent number: 5955742
    Abstract: A compound semiconductor device includes a compound semiconductor layer having an upper major surface formed with a multi-step structure, wherein said multi-step structure includes a plurality of steps each having a step height of at least 5 atomic layers and a step width of 300 nm or more.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: September 21, 1999
    Assignee: Fujitsu Limited
    Inventor: Toshihide Kikkawa
  • Patent number: 5952672
    Abstract: The semiconductor device comprises an (Al.sub.x Ga.sub.1-x)InP layer 20 epitaxially grown on a semiconductor substrate 10 and having a region where the (Al.sub.x Ga.sub.1-x)InP layer 20 has a spontaneous superlattice broken to have a disordered configuration of Al, In and Ga in plane of a Group III atomic layer; and a semiconductor layer 22 epitaxially grown on the (Al.sub.x Ga.sub.1-x)InP layer 20 and having the same conductivity type as the (Al.sub.x Ga.sub.1-x)InP layer 20. In forming the semiconductor layer on the (Al.sub.x Ga.sub.1-x)InP layer, the spontaneous superlattice of the ground (Al.sub.x Ga.sub.1-x)InP layer is broken, whereby the interface between the (Al.sub.x Ga.sub.1-x)InP layer and the semiconductor layer has less traps. Accordingly, low contact resistance can be obtained between the (Al.sub.x Ga.sub.1-x)InP layer and the semiconductor layer.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: September 14, 1999
    Assignee: Fujitsu Limited
    Inventor: Toshihide Kikkawa
  • Patent number: 5953362
    Abstract: A vertical cavity surface emitting laser is formed by eutectically bonding a laser cavity, defined by an active layer disposed between first and second, stacked mirror assemblies, to a host substrate which has a predetermined anisotropic coefficient of thermal expansion. During the forming process, a uniaxial strain is induced within the laser cavity. With this arrangement, large arrays of vertical cavity surface emitting lasers can be formed with predetermined polarization states that are based on the selected anisotropic host substrate.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: September 14, 1999
    Inventors: Jagadeesh Pamulapati, Paul H. Shen
  • Patent number: 5942764
    Abstract: There is provided a semiconductor memory device including a memory cell array having a plurality of multiple logical value memory cells arranged in a matrix, each memory cell storing a plurality of charge conditions each representing a logical value, a word line for selecting a memory cell in a column direction, a bit line for selecting a memory cell in a row direction, and a reading circuit for reading data stored in a selected memory, wherein the reading circuit includes a semiconductor superlattice including at least two sub-band levels under a continuation band, the semiconductor superlattice receiving bit line signals transmitted from the bit line, and transmitting an output signal each time when the bit line signal passes over each of the sub-band levels, and a counter for counting the output signals to output read logical values.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: August 24, 1999
    Assignee: NEC Corporation
    Inventor: Ryuichi Oikawa
  • Patent number: 5932890
    Abstract: A field effect transistor having an excellent transfer conductance and an improved gate leakage current and breakdown voltage is provided. In the transistor, a multiquantum barrier structure 4 is arranged between a gate and a channel layer 3 along a channel layer 3 and having an effect of reflecting incident overflowing carriers a s waves in with with phase conditions of total reflection allowing mutual enhancement of the incident and reflected wave in a region between a channel layer 3 and a gate electrode 10 and/or in a region opposite to the gate electrode 10 relative to the channel layer 3.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: August 3, 1999
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Michinori Irikawa, Kenichi Iga
  • Patent number: 5932899
    Abstract: A semiconductor having enhanced acceptor activation is disclosed. The semiconductor comprises a ternary compound having a non-abruptly varying composition that is uniformly doped. The modulation of the chemical composition leads to a variation of the valence band energy. The modulation of the valence band results in a strong enhancement of the acceptor activation. A method for making a semiconductor having enhanced acceptor activation comprises two steps. They are (1) forming a ternary compound semiconductor having a non-abruptly varying composition, and (2) uniformly doping said semiconductor with a dopant. These two steps may be conducted simultaneously.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: August 3, 1999
    Assignee: Trustees of Boston University
    Inventor: E. Fred Schubert
  • Patent number: 5929461
    Abstract: A surface emission semiconductor laser device has a semiconductor laminate mirror constituted of a plurality of pairs of InGaAS/InAlP films epitaxially grown on a GaAs or InGaAs substrate and a laser element bonded to the laminate mirror. The InAlP films of the laminate mirror are lattice-matched or not lattice-matched due to the amount of Al in the InAlP films. The laminate mirror has a high relative refractive index between the InGaAs and InAlP films and thus has a high reflectance to thereby improve the emission efficiency of the surface emission laser device.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: July 27, 1999
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Takeharu Yamaguchi, Michio Ohkubo, Takao Ninomiya
  • Patent number: 5929462
    Abstract: A semiconductor laser has a multiple-quantum well (MQW) structure overlying a first III-V compound semiconductor. The MQW includes a plurality of layer combinations including a strained well layer and a strained barrier layer, which are formed in a cyclic order. An ultra-thin intermediate film made of the first III-V compound semiconductor and having a thickness corresponding to from monoatomic layer to ten atomic layer is interposed between each strained well layer and each strained barrier layer. The intermediate film functions for preventing formation of mixed crystal formed between the well layer and the barrier layer, thereby improving current density threshold and other characteristics of the semiconductor laser.
    Type: Grant
    Filed: May 23, 1996
    Date of Patent: July 27, 1999
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Akihiko Kasukawa, Michio Ohkubo, Nobumitsu Yamanaka
  • Patent number: 5900642
    Abstract: On a first cladding layer formed of n-type Al.sub.0.7 Ga.sub.0.3 P, an active region having a staggered-type (type II) heterojunction superlattice structure is disposed. The active region includes 50 light emitting layers formed of Al.sub.0.1 Ga.sub.0.9 P doped with nitrogen and 50 barrier layers formed of Al.sub.0.7 Ga.sub.0.3 P. The 50 light emitting layers and the 50 barrier layers formed of such materials are stacked alternately to form 50 pairs. On the active region, a second cladding layer formed of Al.sub.0.1 Ga.sub.0.9 P is disposed. In the formation of the active layers the composition of the light emitting layer and the barrier layer end the thickness of the barrier layer are controlled so that the isoelectronic level in the light emitting layer and the quantum level in the barrier layer will fulfill the resonance conditions.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: May 4, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Nakatsu, Jun-ichi Nakamura
  • Patent number: 5895930
    Abstract: This invention provides infrared sensing photodetector and a method therefor which provides a structure for effectively absorbing a light incident in a normal direction on a substrate, and a method compatible with existing processes for making integrated circuitry.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: April 20, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eung-Gie Oh, Jeon-Wook Yang, Chul-Soon Park, Kwang-Eui Pyun
  • Patent number: 5889295
    Abstract: Disclosed is a long-life GaN-based semiconductor device which is achieved by reducing the operating voltage of the semiconductor device comprising a GaN-based or a ZnSe-based compound semiconductor formed on a sapphire substrate and by preventing the electromigration of metal atoms from an electrode into compound semiconductor layers. The operating voltage of the GaN-based or ZnSe-based semiconductor device formed on a sapphire substrate or a SiC substrate can be greatly reduced by employing a ZnO layer doped with a significant amount of Al as a material for forming ohmic contact to p- or n- compound semiconductor layers. The long-life GaN-based semiconductor device can be attained by preventing electromigration of atoms from a metallic electrode by use of ZnO layer. If a superlattice including the ZnO layer is employed as an optical guide layer or if the superlattice including the ZnO layer as an active layer, a long-life laser diode with a low operating voltage and a wide wavelength range can be obtained.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: March 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: John Rennie, Genichi Hatakoshi
  • Patent number: 5886360
    Abstract: A semiconductor device includes a semiconductor substrate; a semiconductor laminated structure including a first barrier layer, a conduction layer including a natural superlattice, and a second barrier layer, disposed on the semiconductor substrate. The first barrier layer, the conduction layer, and the second barrier layer produce heterojunctions that confine charge carriers within the conduction layer. The first barrier layer has steps at the surface contacting the conduction layer, the steps including, alternatingly arranged, a first crystal plane having a first orientation and a second crystal plane having a second orientation. The conduction layer includes first portions where the natural superlattice is ordered and second portions where the natural superlattice is disordered, the first and second portions being disposed on the first and second crystal planes, respectively. The degree of order in the conduction layer is higher in the first portions than in the second portions.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: March 23, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Seiji Ochi
  • Patent number: 5847409
    Abstract: A semiconductor device that enables to prevent the electron transport property of a semiconductor active layer from degrading even if a semiconductor compositionally-graded buffer layer is used. This device contains a semiconductor substrate, a semiconductor active layer lattice-mismatched with the substrate, and a semiconductor compositionally-graded buffer layer formed between the substrate and the active layer. The compositionally-graded buffer layer has a semiconductor superlattice structure including first semiconductor sublayers and second semiconductor sublayers that are alternately stacked in a direction perpendicular to the substrate. Each of the first sublayers is made of a first semiconductor material. Each of the second sublayers is made of a second semiconductor material different in composition from the first semiconductor material. The lattice constant of the first and second sublayers decreases or increases stepwise from a side near the substrate and the other side near the active layer.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: December 8, 1998
    Assignee: NEC Corporation
    Inventor: Tatsuo Nakayama
  • Patent number: 5831277
    Abstract: The subject invention involves the p-type doping of Al.sub.x Ga.sub.1-x N thin films with a III-nitride composition and specifically a {Al.sub.x Ga.sub.1-x N/GaN} short-period superlattice structure of less than 5000 .ANG. thickness in total in which both the barriers and the wells are p-type doped with Mg.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: November 3, 1998
    Assignee: Northwestern University
    Inventor: Manijeh Razeghi
  • Patent number: 5825049
    Abstract: A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation.
    Type: Grant
    Filed: October 9, 1996
    Date of Patent: October 20, 1998
    Assignee: Sandia Corporation
    Inventors: Jerry A. Simmons, Marc E. Sherwin, Timothy J. Drummond, Mark V. Weckwerth
  • Patent number: 5825057
    Abstract: A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: October 20, 1998
    Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.
    Inventors: Hitoshi Watanabe, Carlos A. Paz De Araujo, Hiroyuki Yoshimori, Michael C. Scott, Takashi Mihara, Joseph D. Cuchiaro, Larry D. McMillan
  • Patent number: 5818073
    Abstract: A semiconductor device includes a III-V compound semiconductor layer including two or more Group III elements and containing dopant impurities, including a spontaneous superlattice, and having a stripe shape with two ends, and electrodes disposed on the ends of the stripe shaped semiconductor layer to form a resistor element. Because of the spontaneous superlattice, electrons are one-dimensionally confined within the III-V compound semiconductor layer, i.e., the electrons flow easier in the direction perpendicular to the periodic direction of the spontaneous superlattice than in the direction parallel to it, resulting in anisotropic of electrical resistivity. Therefore, the orientation of the resistor element with respect to the periodic direction of the spontaneous superlattice becomes another factor in determining the resistance of the resistor element.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: October 6, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Seiji Ochi, Tatuya Kimura
  • Patent number: 5789760
    Abstract: There is provided a semiconductor device comprising a Schottky junction having a very low leakage current and a high forward voltage. The device comprises a Schottky junction realized by a semiconductor 4 and a metal 6 and a multiquantum barrier structure 5 disposed on the interface of said semiconductor 4 and said metal 6 and having an effect of reflecting incident carriers as waves ?in phase conditions capable of allowing mutual enhancement of the incident and reflected waves!.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: August 4, 1998
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Michinori Irikawa, Kenichi Iga
  • Patent number: 5786603
    Abstract: At an n--n hetero-interface in a ZnSe-based or GaN-based multilayered semiconductor laser and light-emitting diode, an excessive voltage drop causing the operating voltage to increased is reduced, thereby lengthening the service life of the device. A single or plurality of n-type intermediate layers are provided in the n--n hetero-interface region where the excessive voltage drop develops. The excessive voltage drop developing at the n--n hetero-interface is decreased by setting the energy value at the edge of the conduction band of each intermediate layer to a mid-value between the energy values at the edges of the conduction bands of the n-type compound semiconductors adjoining both sides of the intermediate layer. The configuration of a GaN-based MQW laser including the intermediate layer formed on sapphire substrate is shown.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: July 28, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: John Rennie, Genichi Hatakoshi, Shinji Saito
  • Patent number: 5783292
    Abstract: In order to fabricate an organic electroluminescent device with good thermal stability and such high durability that its light emission efficiency is retained over a predetermined level for a long time, an anode is formed on a substrate, one or more organic-inorganic compound layers are formed on the anode, and a cathode is formed on the organic compound layers, sequentially. At least one of the organic compound layers comprises a mixed thin film composed of an organic compound dispersed uniformly in an inorganic compound, or a superlattice structure made of an organic compound and an inorganic compound for preventing the thermal degradation of a fluorescent organic compound constituting an emission layer.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: July 21, 1998
    Assignee: Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Shizuo Tokito, Yasunori Taga
  • Patent number: 5768303
    Abstract: A semiconductor device includes a first conductivity type cladding layer; a second conductivity type cladding layer; an active layer of a semiconductor sandwiched between the first conductivity type cladding layer and the second conductivity type cladding layer; and a second conductivity type superlattice barrier layer sandwiched between the active layer and the second conductivity type cladding layer and having a superlattice structure including a first compound semiconductor having a larger energy band gap than the active layer and a second compound semiconductor having a smaller energy difference in the conduction band than the first compound semiconductor and a larger energy difference in the valence band than the first compound semiconductor, the first and second conductivity type compound semiconductors being alternatingly laminated in at least one pair of layers.
    Type: Grant
    Filed: February 6, 1997
    Date of Patent: June 16, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Motoda, Kenichi Ono
  • Patent number: 5763897
    Abstract: In the structure of the device of the invention, a supper-lattice buffer layer is formed between the undoped layer and doped layers. This super-lattice buffer layer serves as a carrier-piling up layer in place of the undoped layer in the conventional device. Thus, the amounts of the piled-up carriers in the undoped layer can be greatly reduced and hence no band filling effect occurs in the undoped layer. Consequently, an optical device having a flat frequency characteristic can be produced without losing its modulating characteristic.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: June 9, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hirohisa Sano, Tatemi Ido
  • Patent number: 5763896
    Abstract: A separate absorption thermal conduction band infrared photocathode fabricated with an engineered material system having energy band gaps specifically selected to provide an energy barrier that is selectively tuned to the momentum and energy of the photogenerated carriers. Such a material system produces an infrared detector having a substantially reduced dark current.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: June 9, 1998
    Assignee: ITT Industries, Inc.
    Inventor: Arlynn Walter Smith
  • Patent number: 5757024
    Abstract: Monocrystalline semiconductor lattices with a buried porous semiconductor layer having different chemical composition. Also monocrystalline semiconductor superlattices with a buried porous semiconductor layers having different chemical composition than that of its monocrystalline semiconductor superlattice. Lattices of alternating layers of monocrystalline silicon and porous silicon-germanium have been produced. These single crystal lattices have been fabricated by epitaxial growth of Si and Si-Ge layers followed by patterning into mesa structures. The mesa structures are stain etched resulting in porosification of the Si-Ge layers with a minor amount of porosification of the monocrystalline Si layers. Thicker Si-Ge layers produced in a similar manner emitted visible light at room temperature.
    Type: Grant
    Filed: July 10, 1996
    Date of Patent: May 26, 1998
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Robert W. Fathauer, Thomas George, Eric W. Jones
  • Patent number: 5751014
    Abstract: On a first cladding layer formed of n-type Al.sub.0.7 Ga.sub.0.3 P, an active region having a staggered-type (type II) heterojunction superlattice structure is disposed. The active region includes 50 light emitting layers formed of Al.sub.0.1 Ga.sub.0.9 P doped with nitrogen and 50 barrier layers formed of Al.sub.0.7 Ga.sub.0.3 P. The 50 light emitting layers and the 50 barrier layers formed of such materials are stacked alternately to form 50 pairs. On the active region, a second cladding layer formed of Al.sub.0.1 Ga.sub.0.9 P is disposed. In the formation of the active layer, the composition of the light emitting layer and the barrier layer and the thickness of the barrier layer are controlled so that the isoelectronic level in the light emitting layer and the quantum level in the barrier layer will fulfill the resonance conditions.
    Type: Grant
    Filed: May 22, 1997
    Date of Patent: May 12, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Nakatsu, Jun-ichi Nakamura
  • Patent number: 5747827
    Abstract: An optoelectronic semiconductor device is provided in which carrier transport towards the active region thereof is enhanced by the formation of a miniband within a superlattice region of the device having a repeating pattern of first and second semiconductor regions. The minimum energy level of the miniband is equal to or greater than the energy level of a guiding region between the active region and the superlattice region.
    Type: Grant
    Filed: March 7, 1996
    Date of Patent: May 5, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Geoffrey Duggan, Nobuaki Teraguchi, Judy Megan Rorison, Yoshitaka Tomomura
  • Patent number: 5734670
    Abstract: A semiconductor device includes a semiconductor substrate having a surface; and a strained superlattice structure including first semiconductor layers having a first strain in a direction with respect to the semiconductor substrate and second semiconductor layers having a second strain in the same direction as and different in magnitude from the first strain, the first semiconductor layers and the second semiconductor layers being alternatingly laminated. The difference in strains between the first semiconductor layers and the second semiconductor layers is reduced, so that the crystalline quality of the strained superlattice structure is improved.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: March 31, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenichi Ono, Takashi Motoda
  • Patent number: 5731596
    Abstract: A method of increasing the saturation threshold of a super lattice optical absorber, and a resulting super lattice optical absorber, involves decreasing the electrical resistance of the substrate adjacent the super lattice structure based on a series resistance model.
    Type: Grant
    Filed: November 2, 1995
    Date of Patent: March 24, 1998
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventor: Magnus Jandel
  • Patent number: 5719895
    Abstract: Several methods are used in novel ways with newly identified and viable parameters to decrease the peak transition energies of the pseudomorphic InGaAs/GaAs heterostructures. These techniques, taken separately or in combination, suffice to permit operation of light emitting devices at wavelengths of 1.3 .mu.m or greater of light-emitting electro-optic devices. These methods or techniques, by example, include: (1) utilizing new superlattice structures having high In concentrations in the active region, (2) utilizing strain compensation to increase the usable layer thickness for quantum wells with appropriately high In concentrations, (3) utilizing appropriately small amounts of nitrogen (N) in the pseudomorphic InGaAsN/GaAs laser structure, and (4) sue of nominal (111) oriented substrates to increase the usable layer thickness for quantum wells with appropriately high In concentrations.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: February 17, 1998
    Assignee: Picolight Incorporated
    Inventors: Jack L. Jewell, Henryk Temkin
  • Patent number: 5684737
    Abstract: A static random access memory (SRAM) cell includes a bistable diode and a load device serially connectable between two voltage potentials (VDD, Ground) with a gate device (field effect transistor) connected between a bit line and a common terminal of the bistable diode and load device and a control terminal of the gate device connected to a word line. The bistable diode includes a GeSi structure between a p-doped semiconductor region and a spaced n-doped semiconductor region. The GeSi structure can be a GeSi/Si superlattice and a .delta.-doped tunnel junction, a Ge.sub.x Si.sub.1-x multiple well structure, or a .delta.-doped tunnel junction.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: November 4, 1997
    Assignee: The Regents of the University of California
    Inventors: Kang L. Wang, Xinyu Zheng, Timothy K. Carns
  • Patent number: 5679961
    Abstract: According to the present invention, there is provided a correlation tunnel device capable of achieving a low power consumption without decreasing a drive force when a large-scale-integrated circuit is constituted.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: October 21, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Higurashi, Akira Toriumi, Fumiko Yamaguchi, Kiyoshi Kawamura, Alfred Hubler
  • Patent number: 5656821
    Abstract: A semiconductor device is provided, including a semiconductor substrate of zinc blend structure, defined by a principal surface substantially coinciding to a {111}A-oriented crystal surface; an etch pit of the shape of a triangular pyramid, formed on the principal surface of the substrate, the etch pit being defined by side walls merging at an apex of said triangular pyramid, each two of the side walls merging at a valley of the triangular pyramid; and an active part formed on the etch pit; wherein the active part includes a quantum well layer having a first bandgap and provided along the side walls of the etch pit, and a pair of barrier layers having a second, larger bandgap and provided so as to sandwich the quantum well layer.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: August 12, 1997
    Assignee: Fujitsu Limited
    Inventor: Yoshiki Sakuma
  • Patent number: 5656831
    Abstract: A semiconductor photo detector has its construction such that on a substrate made of InP are formed light absorption layer having a supperlattice structure made of n- type InGaAsP and InAsP, an intermediate layer made of n- type InGaAs, a multiplication layer made of n- type InP and a layer made of p- type layer. The light having a wavelength 1.65 .mu.m being made incident into the detector from the p- type InP layer is absorbed in the superlattice structure light absorption layer of n- type InGaAs/InAsP and changed into carriers, which flowed out an external circuit. Since the superlattice of InGaAs and InAsP makes a lattice matching to InP, it may be possible to prevent that a dark current is generated by a lattice mismatching. The carriers generated by the absorbed light in the light absorption layer pass from the p type side electrode 11 into an external circuit via the n type InGaAsP intermediate layer 4, n+ type InP multiplication layer 5 and p+ type InP layer 8.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: August 12, 1997
    Assignee: NEC Corporation
    Inventor: Atsuhiko Kusakabe
  • Patent number: 5608229
    Abstract: A semiconductor device having: an underlie having a semiconductor surface capable of growing thereon single crystal; and a first semiconductor layer, the first semiconductor layer including: a first region of group III-V compound semiconductor epitaxially grown on generally the whole area of the semiconductor surface; and second regions of group III-V compound semiconductor disposed and scattered in the first region, the second region having a different composition ratio of constituent elements from the first region, wherein lattice constants of the first and second regions in no strain state differ from a lattice constant of the semiconductor surface, and a difference between the lattice constant of the second region in no strain state and the lattice constant of the semiconductor surface is greater than a difference between the lattice constant of the first region in no strain state and the lattice constant of the semiconductor surface.
    Type: Grant
    Filed: July 26, 1995
    Date of Patent: March 4, 1997
    Assignee: Fujitsu Limited
    Inventors: Kohki Mukai, Nobuyuki Ohtsuka