Abstract: A method of manufacturing epitaxial material used for GaN based LED with low polarization effect, which includes steps of growing n-type InGaAlN layer composed of GaN buffer layer (2) and n-type GaN layer (3), low polarizing active layer composed of InGaAlN multi-quantum well structure polarized regulating and controlling layer (4) and InGaAlN multi-quantum well structure light emitting layer (5) and p-type InGaAlN layer (6) on sapphire or SiC substrate (1) in turn. The method adds InGaAlN multi-quantum well structure polarized regulating and controlling layer, thus reduces polarization effect of quantum well active region.

Abstract: A microelectromechanical system (MEMS) device may include a substrate and at least one movable member supported by the substrate. The at least one movable member may include a superlattice including a plurality of stacked groups of layers with each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A field effect transistor (FET) includes a semiconductor region of a first conductivity type and a well region of a second conductivity type extending over the semiconductor region. A gate electrode is adjacent to but insulated from the well region, and a source region of the first conductivity type is in the well region. A heavy body region is in electrical contact with the well region, and includes a material having a lower energy gap than the well region.

Abstract: A thermoelectric conversion material includes a superlattice structure produced by laminating a barrier layer containing insulating SrTiO3, and a quantum well layer containing SrTiO3 which has been converted into a semiconductor by doping an n-type impurity therein. The quantum well layer has a thickness 4 times or less the unit lattice thickness of SrTiO3 which has been converted into a semiconductor by doping an n-type impurity therein.

Abstract: A method of fabricating a light emitting device includes modulating a crystal growth parameter to grow a quantum well layer that is inhomogeneous and that has a non-random composition fluctuation across the quantum well layer.

Abstract: The present invention relates to a I?-nitride compound semiconductor light emitting device comprising an active layer with the multi-quantum wells interposed between an n-InxAlyGazN(x+y+z=1, 0<x<1, 0<y<1, 0<z?1) layer and a p-InxAlyGazN(x+y+z=1, 0<x<1, 0<y<1, 0<z<1) layer, wherein the active layer comprises an alternate stacking of a quantum-well layer made of InxGa1-xN(0.05<x<1) and a sandwich barrier layer, the sandwich barrier layer comprising a first outer barrier layer of InaGa1-aN(0<a<0.05), a middle barrier layer of AlyGa1-yN(0<y<1) formed on the first outer barrier layer and a second outer barrier layer of InbGa1-bN(0<b<0.05) formed on the middle barrier layer, thereby a high-efficiency/high-output light emitting device with high-current and high-temperature properties can be obtained, and it is possible to easily achieve a high-efficiency green light emission at a wavelength equal to or over 500 nm, and high-efficiency near UV light emission.

Abstract: A light source is provided including an LED component having an emitting surface, which may include: i) an LED capable of emitting light at a first wavelength; and ii) a re-emitting semiconductor construction which includes a second potential well not located within a pn junction having an emitting surface; or which may alternately include a first potential well located within a pn junction and a second potential well not located within a pn junction; and which additionally includes a converging optical element.

Abstract: A light emitting diode (LED) and a method for fabricating the same, capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer disposed on a sapphire substrate; a GaN layer disposed on the buffer layer; a doped GaN layer disposed on the GaN layer; a GaN layer having indium disposed on the GaN layer; an active layer disposed on the GaN layer having indium; and a P-type GaN disposed on the active layer. Here, an empirical formula of the GaN layer having indium is given by In(x)Ga(1-x)N and a range of x is given by 0<x<2, and a thickness of the GaN layer having indium is 50-200 ?.

Abstract: A gallium nitride-based device has a first GaN layer and a type II quantum well active region over the GaN layer. The type II quantum well active region comprises at least one InGaN layer and at least one GaNAs layer comprising 1.5 to 8% As concentration. The type II quantum well emits in the 400 to 700 nm region with reduced polarization affect.

Abstract: In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described.

Abstract: A semiconductor device comprises an active layer formed on a substrate, a superlattice layer formed on the active layer, and an ohmic electrode formed on the superlattice layer. In the superlattice layer, a first thin film and a second thin film are alternately laminated. The second thin film is made of a semiconductor which has polarization characteristics different from those of the first thin film and a band gap larger than that of the first thin film. An interface region between an upper surface of the first thin film and a lower surface of the second thin film or an interface region between a lower surface of the first thin film and an upper surface of the second thin film, is doped with an impurity.

Abstract: A spin coherent, single photon detector has a body of semiconductor material with a quantum well region formed in barrier material in the body. The body has a first electrode forming an isolation electrode for defining, when negatively energized, an extent of the quantum well in the body and a second electrode positioned above a location where an electrostatic quantum dot is defined in said quantum well when positively energized. The quantum well occurs in three layers of material: a central quantum well layer and two outer quantum well layers, the two outer quantum well layers having a relatively low conduction band minimum and the barrier having a relatively high conduction band minimum while the central quantum well layer having a conduction band minimum between the relatively high and relatively low conduction band minimums.

Abstract: In a calibration method, the relation between dopant concentrations of ?-doping layers in a multilayered semiconductor structure and process parameters is determined S1 based on multiple bulk specimens of the material in which the ?-doping layers are located. A desired dopant concentration is selected S2, and the semiconductor structure with predetermined doping levels can be generated S3 based on the relation between the process parameters and the predetermined doping concentrations.

Abstract: A semiconductor device having high reliability, a long lifetime and superior light emitting characteristics by applying a novel material to a p-type cladding layer is provided. A semiconductor device includes a p-type semiconductor layer on an InP substrate, in which the p-type semiconductor layer has a laminate structure formed by alternately laminating a first semiconductor layer mainly including Bex1Mgx2Znx3Te (0<x1<1, 0<x2<1, 0<x3<1, x1+x2+x3=1) and a second semiconductor layer mainly including Bex4Mgx5Znx6Te (0<x4<1, 0<x5<1, 0<x6<1, x4+x5+x6=1).

Abstract: An optical semiconductor device includes an active layer having a quantum well structure including alternately stacked well layers and barrier layers with a larger band gap than the well layers. The band gap of each of the well layers and the barrier layers is constant, each well layer is uniformly provided with compression strain and each barrier layer is provided with large extension strain in a center portion thereof along the thickness direction and small extension strain in portions thereof in the vicinity of the well layers.

Abstract: A semiconductor device including quantum dots comprises a barrier layer of a semiconductor crystal having a first lattice constant and a quantum dot layer including a plurality of quantum dots of a semiconductor crystal having a second lattice constant formed on the barrier layer and a side barrier layer of a semiconductor crystal having a third lattice constant, which is formed in contact with the side faces of the plurality of quantum dots, in which the barrier layer, the quantum dots and the side barrier layer are configured so that the difference between the values of the first lattice constant and the second lattice constant has a sign opposite to that of the difference between values of the first lattice constant and the third lattice constant.

Abstract: The invention provides a device having a substrate, a buffer region positioned upon the substrate, wherein the buffer region has an upper buffer region and a lower buffer region, a heterojunction region positioned upon the buffer region, and a superlattice positioned between the lower buffer region and the upper buffer region, wherein the device is configured to function as a heterojunction field effect transistor.

Abstract: An electronic device may include first and second integrated circuits including respective first and second active optical devices establishing an optical communications link therebetween. The first active optical device may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Also, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

Abstract: A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon.

Abstract: An integrated circuit may include at least one active optical device including a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The integrated circuit may further include a waveguide coupled to the at least one active optical device.

Abstract: A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.

Abstract: A micrometer-scale ion trap, fabricated on a monolithic chip using semiconductor micro-electromechanical systems (MEMS) technology. A single 111Cd+ ion is confined, laser cooled, and the heating measured in an integrated radiofrequency trap etched from a doped gallium arsenide (GaAs) heterostructure. Single 111Cd+ qubit ions are confined in a radiofrequency linear ion trap on a semiconductor chip by applying a combination of static and oscillating electric potentials to integrated electrodes. The electrodes are lithographically patterned from a monolithic semiconductor substrate, eliminating the need for manual assembly and alignment of individual electrodes. The scaling of this structure to hundreds or thousands of electrodes is possible with existing semiconductor fabrication technology.

Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.

Abstract: An active layer having a p-type quantum dot structure is disposed over a lower cladding layer made of semiconductor material of a first conductivity type. An upper cladding layer is disposed over the active layer. The upper cladding layer is made of semiconductor material, and includes a ridge portion and a cover portion. The ridge portion extends in one direction, and the cover portion covers the surface on both sides of the ridge portion. A capacitance reducing region is disposed on both sides of the ridge portion and reaching at least the lower surface of the cover portion. The capacitance reducing region has the first conductivity type or a higher resistivity than that of the ridge portion, and the ridge portion has a second conductivity type. If the lower cladding layer is an n-type, the capacitance reducing region reaches at least the upper surface of the lower cladding layer.

Abstract: This disclosure relates to a system and method for creating nanowires. A nanowire can be created by exposing layers of material in a superlattice and dissolving and transferring material from edges of the exposed layers onto a substrate. The nanowire can also be created by exposing layers of material in a superlattice and depositing material onto edges of the exposed layers.

Abstract: A light-emitting element using GaN. On a substrate (10), formed are an SiN buffer layer (12), a GaN buffer layer (14), an undoped GaN layer (16), an Si-doped n-GaN layer (18), an SLS layer (20), an undoped GaN layer (22), an MQW light-emitting layer (24), an SLS layer (26), and a p-GaN layer (28), forming a p electrode (30) and an n electrode (32). The MQW light-emitting layer (24) has a structure in which InGaN well layers and AlGaN barrier layers are alternated. The Al content ratios of the SLS layers (20, and 26) are more than 5% and less than 24%. The In content ratio of the well layer in the MQW light-emitting layer (24) is more than 3% and less than 20%. The Al content ratio of the barrier layer is more than 1% and less than 30%. By adjusting the content ratio and film thickness of each layer to a desired value, the light luminous efficiency for wavelength of less than 400 nm is improved.

Abstract: Subwells are added to quantum wells of light emitting semiconductor structures to shift their emission wavelengths to longer wavelengths. Typical applications of the invention are to InGaAs, InGaAsSb, InP and GaN material systems, for example.

Abstract: The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory cells. The stacked non-volatile memory cells are formed on a semiconductor wafer, having a bulk semi-conductive substrate and an SOI semi-conductive layer and are arranged as a bulk FinFET transistor and an SOI FinFet transistor being arranged on top of the bulk FinFET transistor. Both the FinFET transistor and the SOI FinFet transistor are attached to a common charge-trapping layer. A word line with sidewalls is arranged on top of said patterned charge-trapping layer and a spacer oxide layer is arranged on the sidewalls of said word line.

Abstract: A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.

Abstract: The semiconductor layer structure comprises a superlattice (9) composed of alternately stacked layers (9a, 9b) of III-V semiconductor compounds of a first composition (a) and at least one second composition (b). The layers (9a, 9b) of the superlattice (9) contain dopants in predetermined concentrations, with regard to which the concentrations of the dopants are different at least two layers of a same composition in the superlattice (9), the concentration of the dopants is graded within at least one layer (9a, 9b) of the superlattice (9), and the superlattice (9) comprises layers that are doped with different dopants or comprise at least one layer (9a, 9b) that is undoped. The electrical and optical properties of the superlattice (9) can be adapted to given requirements in the best possible manner in this way.

Abstract: The present invention relates to a semiconductor device having a multi-layered structure comprising an emitter layer, a base layer, and a collector layer, each composed of a group III-V n-type compound semiconductor in this order; a quantum dot barrier layer disposed between the emitter layer and the base layer; a collector electrode, a base electrode and the emitter layer all connected to an emitter electrode; the quantum dot barrier layer having a plurality of quantum dots being sandwiched between first and second barrier layers from the emitter layer side and the base layer side, respectively and each having a portion that is convex to the base layer; a base layer side interface in the second barrier layer, and collector layer side and emitter layer side interfaces in the base layer having curvatures that are convex to the collector layer corresponding to the convex portions of the quantum dots.

Abstract: An LED having vertical topology and a method of making the same is capable of improving a luminous efficiency and reliability, and is also capable of achieving mass productivity. The method includes forming a semiconductor layer on a substrate; forming a first electrode on the semiconductor layer; forming a supporting layer on the first electrode; generating an acoustic stress wave at the interface between the substrate and semiconductor layer, thereby separating the substrate from the semiconductor layer; and forming a second electrode on the semiconductor layer exposed by the separation of the substrate.

Abstract: An integrated circuit may include at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: An improved THz detection mechanism includes a heterojunction thyristor structure logically formed by an n-type quantum-well-base bipolar transistor and p-type quantum-wellbase bipolar transistor arranged vertically to share a common collector region. Antenna elements, which are adapted to receive electromagnetic radiation in a desired portion of the THz region, are electrically coupled (or integrally formed with) the p-channel injector electrodes of the heterojunction thyristor device such the that antenna elements are electrically connected to the p-type modulation doped quantum well interface of the device. THz radiation supplied by the antenna elements to the p-type quantum well interface increases electron temperature of a two-dimensional electron gas at the p-type modulation doped quantum well interface thereby producing a current resulting from thermionic emission over a potential barrier provided by said first-type modulation doped quantum well interface.

Abstract: Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

Abstract: To reduce a current loss through a channel and improve electron mobility, a first semiconductor layer and a second semiconductor layer (sequentially formed on a semiconductor substrate) have different lattice properties. The first semiconductor layer and the second semiconductor layer may be etched to form a first semiconductor pattern. A third semiconductor layer having a lattice property substantially identical to that of the first semiconductor layer may be formed over the first semiconductor pattern. The third semiconductor layer may then be etched to form a second semiconductor pattern. A gate may be formed on the second semiconductor pattern. The contact surface between the second semiconductor pattern and the gate pattern may consequently increased to reduce a current loss. Further, the lattice properties may be changed to improve electron mobility of the semiconductor layers.

Abstract: A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The semiconductor device may further include a semiconductor layer adjacent the superlattice and comprising at least one first region therein including a first conductivity type dopant. The superlattice may also include at least one second region therein including a second conductivity type dopant to define, with the at least one first region, at least one semiconductor junction.

Abstract: A nitride semiconductor device including a light emitting device comprises a n-type region of one or more nitride semiconductor layers having n-type conductivity, a p-type region of one or more nitride semiconductor layers having p-type conductivity and an active layer between the n-type region and the p-type region. In such devices, there is provided with a super lattice layer comprising first layers and second layers which are nitride semiconductors having a different composition respectively. The super lattice structure makes working current and voltage of the device lowered, resulting in realization of more efficient devices.

Abstract: A semiconductor device may include at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A nitride compound semiconductor element having improved characteristics, productivity and yield. A nitride compound semiconductor element includes: a sapphire substrate; a first single crystalline layer of AlN formed on said sapphire substrate; a second single crystalline layer formed on said first single crystalline layer, said second single crystalline layer being made of AlxGa1-xN (0.8?x?0.97) and having a thickness of equal to or more than 0.3 ?m and equal to or less than 6 ?m; and a device structure section of a nitride semiconductor formed on said second single crystalline layer.

Abstract: A semiconductor device includes a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure, and a fourth plurality of layers including a p-type ohmic contact layer. Etch stop layers are used to form contacts to the n-type ohmic contact layer and contacts to the n-type modulation doped quantum well structure. Thin capping layers are also provided to protect certain layers from oxidation. Preferably, each such etch stop layer is made sufficiently thin to permit current tunneling therethrough during operation of optoelectronic/electronic devices realized from this structure (including heterojunction thyristor devices, n-channel HFET devices, p-channel HFET devices, p-type quantum-well-base bipolar transistor devices, and n-type quantum-well-base bipolar transistor devices).

Abstract: A superlattice nanocrystal Si—SiO2 electroluminescence (EL) device and fabrication method have been provided. The method comprises: providing a Si substrate; forming an initial SiO2 layer overlying the Si substrate; forming an initial polysilicon layer overlying the initial SiO2 layer; forming SiO2 layer overlying the initial polysilicon layer; repeating the polysilicon and SiO2 layer formation, forming a superlattice; doping the superlattice with a rare earth element; depositing an electrode overlying the doped superlattice; and, forming an EL device. In one aspect, the polysilicon layers are formed by using a chemical vapor deposition (CVD) process to deposit an amorphous silicon layer, and annealing. Alternately, a DC-sputtering process deposits each amorphous silicon layer, and following the forming of the superlattice, polysilicon is formed by annealing the amorphous silicon layers. Silicon dioxide can be formed by either thermal annealing or by deposition using a DC-sputtering process.

Abstract: Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by the thicknesses of alternating layers of different materials that are in the form of a superlattice. Wires are created by evaporating the desired material onto the superlattice that has been selectively etched to provide height contrast between layers. The wires thus formed upon one set of superlattice layers are then transferred to a substrate.

Abstract: A GaN LED structure with a short period superlattice contacting layer is provided. The LED structure comprises, from the bottom to top, a substrate, a double buffer layer, an n-type GaN layer, a short period superlattice contacting layer, an active layer, a p-type shielding layer, and a contacting layer. The feature is to avoid the cracks or pin holes in the thick n-type GaN layer caused during the fabrication of heavily doped (n>1×1019 cm?3) thick n-type GaN contacting layer, so that the quality of the GaN contacting layer is assured. In addition, by using short period heavily silicon doped Al1-x-yGaxInyN (n++-Al1-x-yGaxInyN) to grow a superlattice structure to become a short period superlattice contacting layer structure, which is used as a low resistive n-type contacting layer in a GaInN/GaN MQW LED. In the following steps, it is easier to form an n-type ohmic contacting layer, and the overall electrical characteristics are improved.

Abstract: A device for generating terahertz radiation. The device comprising a dipole generating layer, a coupling block and an extraction block. The coupling block is transparent to laser light and is in contact with the surface of the dipole generating layer to couple light from a laser to the surface of the dipole generating layer, when the device is in use. The extraction block is located in contact with the surface of the dipole generating layer to provide an emission extraction surface. The refractive indices of the dipole forming layer, the coupling block and the extraction block are substantially equal. In this way, the dipole which is generated upon illumination of the dipole generating layer by a laser, has an axis which is not perpendicular to the emission.

Abstract: The invention relates to a semiconductor structure for use in the near infrared region, preferably in the range from 1.3 to 1.6 ?m, said structure comprising an active zone consisting of a plurality of epitaxially grown alternating layers of Si and Ge, a base layer of a first conductivity type disposed on one side of said active zone, and a cladding layer of the opposite conductivity type to the base layer, the cladding layer being provided on the opposite side of said active zone from said base layer, wherein the alternating Si and Ge layers of said active zone form a superlattice so that holes are located in quantized energy levels associated with a valance band and electrons are localized in a miniband associated with the conduction band and resulting from the superlattice structure. The invention is also directed to a method of manufacturing aforementioned structure.

Abstract: A nitride semiconductor is grown on a silicon substrate by depositing a few mono-layers of aluminum to protect the silicon substrate from ammonia used during the growth process, and then forming a nucleation layer from aluminum nitride and a buffer structure including multiple superlattices of AlRGa(1-R)N semiconductors having different compositions and an intermediate layer of GaN or other Ga-rich nitride semiconductor. The resulting structure has superior crystal quality. The silicon substrate used in epitaxial growth is removed before completion of the device so as to provide superior electrical properties in devices such as high-electron mobility transistors.

Abstract: A practically realizable semiconductor magnetic body having a flat-band structure is disclosed. The semiconductor magnetic body is formed by semiconductor quantum dots arranged on lattice points such that electrons can transfer between neighboring quantum dots and the electron energy band contains a flat-band structure, where each quantum dot is a structure in which electrons are confined inside a region which is surrounded by high energy potential regions, and the flat-band structure is a band structure in which energy dispersion of electrons has hardly any wave number dependency.