Abstract: A device having a sensor die with a sensor and a control circuit die with at least one control circuit disposed therein, the control circuit die on the sensor die. A plurality of mounting pads is disposed on a second side of the sensor die. A first electrical connection connects a first one of the plurality of mounting pads to a first control circuit of the at least one sensor control circuit and a second electrical connection connects the first control circuit to the sensor. A third electrical connection connects the sensor to a second control circuit of the at least one control circuit and a fourth electrical connection connects the second control circuit to second one of the plurality of mounting pads.

Abstract: A pixel comprises a high-response photodiode that collects photocharge, a first transfer gate that enables the charge to be transferred off the high-response photodiode, completely emptying it onto a low-response photodiode, a second transfer gate enables the charge to be transferred off the low-response photodiode, completely emptying it onto floating diffusion, a third transfer gate for anti-blooming; the floating diffusion collects the transferred charge creating a change of voltage, a means of resetting the floating diffusion. A source-follower is modulated by the voltage on floating diffusion to control bit-line voltage and column-amplifier output. In examples, photocharge is integrated onto both the high-response photodiode and onto the low-response photodiode.

Abstract: An image sensor includes a substrate including a pixel array region and a logic region where a surface of the pixel array region is higher than a surface of the logic region, and a light shielding pattern formed over the substrate of the logic region and having a surface on substantially the same plane as a surface of the substrate.

Abstract: A global shutter image sensor formed on an n-type bulk substrate and including pixels having pinned n-type photodiodes and memory nodes formed in designated n-doped epitaxial layer regions that are separated from the bulk substrate by a p-type vertical (potential) barrier implant. Each memory node includes both a buried channel portion and a contiguous pinned diode portion having different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion during global charge transfer from an adjacent photodiode. The p-type vertical (potential) barrier implant is coupled to ground, and the bulk substrate is switched between a low integration voltage level during integration periods, and a high reset voltage level, whereby the photodiodes are globally reset without requiring reset transistors. P-type sinker implant sections and p-type vertical barrier implants form box-like diffusions around each pixel's photodiode and memory node.

Abstract: An image sensor includes a plurality of photoelectric detectors, a plurality of color filters, and at least one pixel isolation region between adjacent ones of the photoelectric detectors. The color filters include a white color filter, and the color filters correspond to respective ones of the photoelectric detectors. The at least one pixel isolation region serves to physically and at least partially optically separate the photoelectric detectors from one another.

Abstract: An embodiment provides an imaging device including a pixel that includes a first photoelectric conversion portion, a second photoelectric conversion portion, a first transfer transistor, a second transfer transistor, and a floating diffusion portion. The first transfer transistor transfers a signal charge in the first photoelectric conversion portion to the floating diffusion portion. The second transfer transistor transfers a signal charge in the second photoelectric conversion portion to the floating diffusion portion. A potential at the first photoelectric conversion portion for the signal charge is higher than a potential at the second photoelectric conversion portion for the signal charge.

Abstract: A chip package includes a chip, an insulating layer, a flowing insulating material layer and conductive layer. The chip has a conductive pad, a side surface, a first surface and a second surface opposite to the first surface, which the side surface is between the first surface and the second surface, and the conductive is below the first surface and protruded from the side surface. The insulating layer covers the second surface and the side surface, and the flowing insulating material layer is disposed below the insulating layer, and the flowing insulating material layer has a trench exposing the conductive pad protruded form the side surface. The conductive layer is disposed below the flowing insulating material layer and extended into the trench to contact the conductive pad.

Abstract: A package for a device to be inserted into a solid structure may include a building material that includes particles of one of micrometric and sub-micrometric dimensions. The device may include an integrated detection module having at least one integrated sensor and the package arranged to coat at least one portion of the device including the integrated detection module. A method aspect includes a method of manufacturing the device. A system aspect is for monitoring parameters in a solid structure that includes the device.

Abstract: A solid-state imaging device includes a first and second pixel regions. In the first pixel region, a photoelectric conversion unit, a floating diffusion region (FD), and a transferring transistor are provided. In the second pixel region, an amplifying transistor, and a resetting transistor are provided. A first element isolation portion is provided in the first pixel region, while a second element isolation portion is provided in the second pixel region. An amount of protrusion of an insulating film into a semiconductor substrate in the first element isolation portion is smaller, than that in the second element isolation portion.

Abstract: An optical apparatus includes plural optical lens groups, an optical sensor, at least one lighting member and a casing. After a light beam passes through any of the plural optical lens groups, a travelling direction of the light beam is changed. After the light beam passes through at least one of the plural optical lens groups, the light beam is sensed and converted into an image signal by the optical sensor. The lighting member outputs a source beam. The plural optical lens groups, the optical sensor and the lighting member are accommodated within the casing. The optical apparatus has a single optical lens module, and is able to implement different optical functions simultaneously. Consequently, the overall volume of the optical apparatus is minimized, the fabricating cost of the optical apparatus is reduced, the assembling process is simplified, and the number of components to be assembled is reduced.

Abstract: An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection. The integrated photo detector includes a first photodiode formed in the SOI substrate and associated with a first p-electrode and a first n-electrode. Additionally, the integrated photo detector includes a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays. Moreover, the integrated photo detector includes a first electrode and a second electrode disposed respectively on the SOI substrate. The first/second electrode is respectively connected to the first p/n-electrode via a first/second metallic layer patterned with a reduced width from the first/second electrode to the first p/n-electrode and connected to the second p/n-electrode via a first/second metallic wire to make a parallel coupling between the first photodiode and the second photodiode with an ESD threshold of about 100V.

Abstract: The semiconductor device includes a semiconductor substrate, an isolation feature, a photodiode and a transistor gate. The isolation feature is disposed in the semiconductor substrate. The photodiode is disposed in the semiconductor substrate and adjacent to the isolation feature. The photodiode includes a first pinned photodiode (PPD) with a first dopant type and a second PPD with a second dopant type. The second PPD is embedded in the first PPD, and is different from the first dopant type. The transistor gate is disposed over the photodiode and includes a first portion and a second portion. The first portion with the first dopant type is used for controlling the operation of the semiconductor device. The second portion with the second dopant type is adjacent to the first portion. The second portion covers the photodiode and extends toward the isolation feature.

Abstract: A signal processing device includes a control unit that suspends supplying of a signal to an A/D conversion unit which performs A/D conversion, during an A/D conversion period in which the A/D conversion is performed on the signal that depends on an electric charge read from a pixel; and a maintenance unit that maintains a signal value of the signal in a state where the signal is supplied by the control unit to the A/D conversion unit and that supplies the maintained signal value to the A/D conversion unit in a state where the supplying of the signal to the A/D conversion unit is suspended by the control unit.

Abstract: A semiconductor device including a substrate, at least one sensor, a dielectric layer, at least one light pipe structure, at least one pad, a shielding layer, and a protection layer is provided. The sensor is located in the substrate of a first region. The dielectric layer is located on the substrate. The light pipe structure is located in the dielectric layer of the first region. The light pipe structure corresponds to the sensor. The pad is located in the dielectric layer of a second region. The shielding layer is located on the dielectric layer, wherein the light pipe structure is surrounded by the shielding layer. The protection layer is located on the shielding layer. At least one pad opening is disposed in the dielectric layer, the shielding layer, and the protection layer above the pad. The pad opening exposes a top surface of the corresponding pad.

Abstract: Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate.

Abstract: The present invention provides an array substrate and a manufacturing method thereof, a display panel and a display device. The manufacturing method of an array substrate in the present invention comprises: forming light-shielding layers on the base substrate through a patterning process by using a light-shielding layer-doping multiplexing mask plate; and performing doping of CMOS transistors by using the light-shielding layer-doping multiplexing mask plate. In the invention, two mask plates used in manufacturing the light-shielding layer and the doping process in the prior art are replaced with one light-shielding layer-doping multiplexing mask plate, therefore the number of the mask plates during manufacturing is reduced and the cost is decreased. Meanwhile, providing of the light-shielding layer below the N type transistors in the driving region of the array substrate may prevent light-induced leakage current from being generated in the conductive region.

Abstract: An image sensor includes at least one pixel with a transfer gate that is controllable among at least three biasing conditions, including a first biasing condition in which electrons are transferable from a photodiode to a potential well under the transfer gate, a second biasing condition in which the electrons are confined in the potential well under the transfer gate, and a third biasing condition in which the electrons are transferable out of the potential well under the transfer gate. The pixel includes a p+ type doped barrier implant located at least partially under a portion of the transfer gate, and a pinned charge transfer barrier located on the opposite side of the transfer gate from the photodiode that includes a p+ type doped region and an n-type doped region. The image sensor can operate in a global shutter mode and/or a rolling shutter mode.

Abstract: A semiconductor device including a substrate, at least one sensor, a dielectric layer, at least one light pipe structure, at least one pad, a shielding layer, and a protection layer is provided. The sensor is located in the substrate of a first region. The dielectric layer is located on the substrate. The light pipe structure is located in the dielectric layer of the first region. The light pipe structure corresponds to the sensor. The pad is located in the dielectric layer of a second region. The shielding layer is located on the dielectric layer, wherein the light pipe structure is surrounded by the shielding layer. The protection layer is located on the shielding layer. At least one pad opening is disposed in the dielectric layer, the shielding layer, and the protection layer above the pad. The pad opening exposes a top surface of the corresponding pad.

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: A solid-state imaging device includes a photodiode that generates a signal charge by photoelectric conversion according to received light, a floating diffusion that accumulates the signal charge generated by the photodiode, an amplification transistor that amplifies and outputs a power source voltage according to the signal charge accumulated in the floating diffusion, a dummy transistor having the same characteristics as the amplification transistor, and a negative feedback circuit that applies a negative feedback to the dummy transistor such that respective source currents of the amplification transistor and the dummy transistor are equal to each other. The respective source currents of the amplification transistor and the dummy transistor are controlled so as to coincide with each other by the negative feedback circuit.

Abstract: An imaging device including a plurality of pixels and a control circuit to apply a signal to the pixels, wherein the pixels include a photodiode formed on a substrate and a first terminal and a second terminal, a shift switching unit to be connected to the first terminal, a first storage node, a transfer switching unit, a second storage node, and a reset switching unit, when an operating mode is set as a first mode, the control circuit allows charges integrated in the photodiode to be shifted to the first storage node during a first interval and the second terminal during a second interval, and when the operating mode is set as a second mode, the charges integrated in the photodiode are not shifted to the second terminal.

Abstract: An image sensor includes a plurality of photoelectric detectors, a plurality of color filters, and at least one pixel isolation region between adjacent ones of the photoelectric detectors. The color filters include a white color filter, and the color filters correspond to respective ones of the photoelectric detectors. The at least one pixel isolation region serves to physically and at least partially optically separate the photoelectric detectors from one another.

Abstract: As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.

Abstract: A backside illuminated (BSI) image sensor device includes: a first substrate including a front side and a back side; a second substrate bonded with the first substrate on the front side; and a blocking layer between the first substrate and the second substrate. The first substrate includes an image sensor, and the image sensor is configured to collect incident light entering from the back side. The second substrate includes a circuit coupled with the image sensor. The blocking layer is configured to block radiation induced by the circuit.

Abstract: Described herein is a pinned photodiode pixel architecture having a p-type substrate that is independently biased with respect to a pixel area to provide an avalanche region between an n-type region and a p-type region formed on the substrate. Such a pinned photodiode pixel can be used in imaging sensors that are used in low light level conditions.

Abstract: A pixel cell includes a photodiode disposed in a semiconductor material to accumulate image charge in response to incident light directed to the photodiode. A global shutter gate transistor disposed in the semiconductor material and is coupled to the photodiode to selectively deplete the image charge from the photodiode. A storage transistor is disposed in the semiconductor material to store the image charge. An optical isolation structure is disposed in the semiconductor material proximate to the storage transistor to isolate a sidewall of the storage transistor from stray light and stray charge in the semiconductor material outside of the storage transistor. The optical isolation structure is filled with tungsten.

Abstract: A solid-state imaging device includes a first and second pixel regions. In the first pixel region, a photoelectric conversion unit, a floating diffusion region (FD), and a transferring transistor are provided. In the second pixel region, an amplifying transistor, and a resetting transistor are provided. A first element isolation portion is provided in the first pixel region, while a second element isolation portion is provided in the second pixel region. An amount of protrusion of an insulating film into a semiconductor substrate in the first element isolation portion is smaller, than that in the second element isolation portion.

Abstract: A CMOS image sensor has a photodiode including first and second impurity layers sequentially formed on a substrate, an isolation layer on the second impurity layer, and a transfer gate structure through the second impurity layer. The transfer gate structure contacts a top surface of the first impurity layer and a portion of the second impurity layer and includes a bottom surface having a step shape.

Abstract: A method of forming a conductive bridging memory cell can include forming an active electrode layer above a barrier layer formed on a lower conductive layer; forming at least one ion conductor layer over an active electrode layer; incorporating conductive ions into the ion conductor layer to create a switch memory layer that changes impedance in response to an electric field; and the active electrode layer is a source of conductive ions for the ion conductor, and the barrier layer substantially prevents a movement of conductive ions therethrough.

Abstract: Certain embodiments provide a solid-state imaging device including a pixel portion including a first light receiving layer, a charge accumulation portion including a first charge accumulation layer which accumulates a charge, a first transfer gate portion, a charge detection portion and a second transfer gate portion. The first transfer gate portion transfers the charge from the pixel portion to the charge accumulation portion, and the second transfer gate portion transfers the charge from the charge accumulation portion to the charge detection portion. The charge detection portion causes a voltage drop corresponding to an amount of the charge transferred to this region. An impurity layer of a ring shape which includes an opening portion is provided on a surface of at least one of the first light reception layer of the pixel portion and the first charge accumulation layer of the charge accumulation portion.

Abstract: Certain embodiments provide a solid-state imaging device including a pixel portion, a charge storage portion, a first transfer gate portion, a charge detecting portion, a second transfer gate portion, and an offset gate portion. The charge storage portion stores the electrical charges generated in the pixel portion. The first transfer gate portion transfers electrical charges from the pixel portion to the charge storage portion, and the second transfer gate portion transfers the electrical charges from the charge storage portion to the charge detecting portion. The offset gate portion is provided between the second transfer gate portion and the charge detecting portion and is applied with a predetermined constant voltage. This offset gate portion includes an offset gate layer that has a plurality of projections formed at positions adjacent to the second transfer gate portion and an offset gate electrode.

Abstract: A correlated double sampling (CDS) circuit included in an image sensor includes a sampling unit and a timing controlled band-limitation (TCBL) unit. The sampling unit is configured to generate an output signal by performing a CDS operation with respect to a reset component of an input signal and an image component of the input signal based on a ramp signal, the input signal being provided from a pixel array included in the image sensor. The TCBL unit is connected to the sampling unit, and is configured to remove noise from the output signal based on a timing control signal. The timing control signal is activated during a first comparison duration, in which a first comparison operation is performed with respect to the ramp signal and the reset component of the input signal, and during a second comparison duration, in which a second comparison operation is performed with respect to the ramp signal and the image component of the input signal.

Abstract: In the field of image sensors, more particularly time-delay integration linear sensors or TDI sensors, a sensor comprises rows of photodiodes alternating with rows of gates adjacent to the photodiodes. The gates are asymmetric, adjacent on one side to a photodiode and having, on the other side, narrow gate fingers extending toward another photodiode. Owing to their very narrow width, the fingers endow the transfer of charges with a directionality. Between two successive photodiodes there are two gates, the two being adjacent to the two photodiodes, the first having its narrow fingers turned toward the first photodiode, the second having its narrow fingers turned toward the second photodiode. The direction of transfer of the charges in the sensor may be chosen by neutralizing either the first gate or the second gate, the other gate receiving alternating potentials allowing the transfer of charges from one photodiode to the other.

Abstract: A solid-state image sensor includes a semiconductor region including a plurality of photoelectric converters from which signals are allowed to be independently read out; a first microlens; and a second microlens which is arranged between the first microlens and the semiconductor region, wherein the second microlens includes a central portion and a peripheral portion that surrounds the central portion, and a power of the peripheral portion is a positive value and larger than a power of the central portion.

Abstract: A pixel cell includes a photodiode, a storage transistor, a transfer transistor and an output transistor disposed in a semiconductor substrate. The transfer transistor selectively transfers image charge accumulated in the photodiode from the photodiode to the storage transistor. The output transistor selectively transfers the image charge from the storage transistor to a readout node. A first isolation fence is disposed over the semiconductor substrate separating a transfer gate of the transfer transistor from a storage gate of the storage transistor. A second isolation fence is disposed over the semiconductor substrate separating the storage gate from an output gate of the output transistor. Thicknesses of the first and second isolation fences are substantially equal to spacing distances between the transfer gate and the storage gate, and between the storage gate and the output gate, respectively.

Abstract: A solid-state image pickup device includes a plurality of pixels, each of the pixels including a photoelectric conversion portion, a charge holding portion, a floating diffusion, and a transfer portion. The pixel also includes a beneath-holding-portion isolation layer and a pixel isolation layer. An end portion on a photoelectric conversion portion side of the pixel isolation layer is away from the photoelectric conversion portion compared to an end portion on a photoelectric conversion portion side of the beneath-holding-portion isolation layer, and an N-type semiconductor region constituting part of the photoelectric conversion portion is disposed under at least part of the beneath-holding-portion isolation layer.

Abstract: A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a second pull-up transistor, and a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor. A conductive feature includes a first leg having a first longitudinal direction, wherein the first leg interconnects a drain of the first pull-up transistor and a drain of the first pull-down transistor. The conductive feature further includes a second leg having a second extending direction. The first longitudinal direction and the second extending direction are un-perpendicular and un-parallel to each other. The second leg interconnects the drain of the first pull-up transistor and a gate of the second pull-up transistor.

Abstract: A unit pixel of an image sensor includes a photoelectric conversion region, an isolation region, a floating diffusion region and a transfer gate. The photoelectric conversion region is formed in a semiconductor substrate. The isolation region surrounds the photoelectric conversion region, extends substantially vertically with respect to a first surface of the semiconductor substrate, and crosses the incident side of the photoelectric conversion region so as to block leakage light and diffusion carriers. The floating diffusion region is disposed in the semiconductor substrate above the photoelectric conversion region. The transfer gate is disposed adjacent to the photoelectric conversion region and the floating diffusion region, extends substantially vertically with respect to the first surface of the semiconductor substrate, and transmits the photo-charges from the photoelectric conversion region to the floating diffusion region.

Abstract: The present invention relates to a solid-state image pickup device. The device includes a first substrate including a photoelectric conversion element and a transfer gate electrode configured to transfer charge from the photoelectric conversion element, a second substrate having a peripheral circuit portion including a circuit configured to read a signal based charge generated in the photoelectric conversion element, the first and second substrates being laminated. The device further includes a multilayer interconnect structure, disposed on the first substrate, including an aluminum interconnect and a multilayer interconnect structure, disposed on the second substrate, including a copper interconnect.

Abstract: A solid-state imaging device including a photoelectric conversion element operable to generate electric charge according to the amount of incident light and to accumulate the electric charge in the inside thereof, an electric-charge holding region in which the electric charge generated through photoelectric conversion by the photoelectric conversion element is held until read out, and a transfer gate having a complete transfer path through which the electric charge accumulated in the photoelectric conversion element is completely transferred into the electric-charge holding region, and an intermediate transfer path through which the electric charge generated by the photoelectric conversion element during an exposure period and being in excess of a predetermined charge amount is transferred into the electric-charge holding region. The complete transfer path and the intermediate transfer path are formed in different regions.

Abstract: Provided is a solid-state imaging device including: a photodiode which converts an optical signal to signal charges; a transfer gate which transfers the signal charges from the photodiode; an impurity diffusion layer to which the signal charges are transferred by the transfer gate; and a MOS transistor of which a gate is connected to the impurity diffusion layer. The impurity diffusion layer has a first conduction type semiconductor layer and a second conduction type semiconductor layer which is formed in the first conduction type semiconductor layer and under an end portion of the transfer gate.

Abstract: An organic image sensor includes a first organic photoelectric conversion pixel circuit on an active region of a substrate and a second organic photoelectric conversion pixel circuit on an optical black region of the substrate. The first organic photoelectric conversion pixel circuit includes a first organic photoelectric conversion element configured to generate charges responding to incident light and a first readout circuit configured to receive a first input signal including the charges generated in the first organic photoelectric conversion element. The second organic photoelectric conversion pixel circuit includes a second organic photoelectric conversion element and a second readout circuit configured to receive a second input signal generated irrespective of the incident light.

Abstract: In a photoelectric conversion apparatus including a charge holding portion, a part of an element isolation region contacting with a semiconductor region constituting the charge holding portion extends from a reference surface including the light receiving surface of a photoelectric conversion element into a semiconductor substrate at a level equal to or deeper than the depth of the semiconductor region in comparison with the semiconductor region.

Abstract: A heterojunction III-V photovoltaic (PV) cell includes a base layer comprising a III-V substrate, the base layer being less than about 20 microns thick; an intrinsic layer located on the base layer; an amorphous silicon layer located on the intrinsic layer; and a transparent conducting oxide layer located on the amorphous silicon layer.

Abstract: A photo detector comprising a first doped impurity region (adapted to receive a first voltage) disposed in or on a substrate; a body region, juxtaposed the first doped impurity region; a gate (adapted to receive a second voltage) spaced from a first portion of the body region; a light absorbing region, juxtaposed a second portion of the body region, includes a material which, in response to light incident thereon, generates carrier pairs including a first and second type carriers; a contact region (adapted to receive a third voltage) juxtaposed the light absorbing region; wherein, in response to incident light, the gate attracts first type carriers of the carrier pairs to the first portion of the body region which causes second carriers from the first doped impurity region to flow to the contact region, and the contact region attracts second type carriers.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films.

Abstract: A semiconductor device including a semiconductor substrate having a surface including an active semiconductor device including one of a laser and a photodiode; and a visual indicator disposed on the semiconductor body and at least adjacent to a portion of said active semiconductor device, the indicator having a state that shows if damage to the active semiconductor device may have occurred.

Abstract: Method for manufacturing a microelectronic device from a first substrate (10), including the production of at least one electronic component in the semi-conductor substrate after transferring the first substrate (10) onto a second substrate (20), characterized in that it comprises: a first phase carried out prior to the transfer, and including forming at least one pattern made of a sacrificial material in a layer of the first substrate (10), a second phase carried out after the transfer and including the substitution of the electronic component for the pattern.

Abstract: An imaging device includes at least one pixel having a phototransistor which converts light energy into signal charge and varies an amplification factor relative to the intensity of the received light energy, wherein the signal charge of the phototransistor is read out while receiving the light energy with the phototransistor for each pixel.

Abstract: A thin film diode (100A) includes a semiconductor layer (130) having first, second, and third semiconductor regions, a first insulating layer (122) formed on the semiconductor layer (130), and a second insulating layer (123) formed on the first insulating layer (122). The first semiconductor region (134A) contains an impurity of a first-conductivity type at a first concentration; the second semiconductor region (135A) contains an impurity of a second-conductivity type different from the first conductivity type at a second concentration; and the third semiconductor region (133A) contains the first-conductivity type impurity at a third concentration lower than the first concentration, or contains the second-conductivity type impurity at a third concentration lower than the second concentration. The first semiconductor region (134A) conforms to an aperture pattern in the second insulating layer (123), or the second semiconductor region (135A) conforms to an aperture pattern in the second insulating layer (123).