Stacked Capacitor Patents (Class 257/306)
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Patent number: 8299517Abstract: A semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same is disclosed. A semiconductor substrate has an active region. A trench structure is defined within the active region. The trench structure includes an upper trench region adjacent to a surface of the active region, a lower trench region and a buffer trench region interposed between the upper trench region and the lower trench region. A width of the lower trench region may be greater than a width of the upper trench region. An inner wall of the trench structure may include a convex region interposed between the upper trench region and the buffer trench region and another convex region interposed between the buffer trench region and the lower trench region. A gate electrode is disposed in the trench structure. A gate dielectric layer is interposed between the gate electrode and the trench structure.Type: GrantFiled: February 20, 2008Date of Patent: October 30, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Ho Jang, Yong-Jin Choi, Min-Sung Kang, Kwang-Woo Lee
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Patent number: 8283235Abstract: A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern.Type: GrantFiled: July 31, 2009Date of Patent: October 9, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Satoru Mihara
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Patent number: 8278694Abstract: The present invention provides a semiconductor device having a plurality of vertical transistors, which includes, on a substrate, a semiconductor pillar 5; gate electrode 11 provided on the side of the pillar via gate insulating film 10; first diffusion layer 9 connected to the bottom of the pillar; and second diffusion layer 16 connected to the top of the pillar, second diffusion layer 16 includes first portion 14 formed within the area over the pillar, and second portion 15 which is an epitaxial growth layer, formed on the first portion and contacting with insulating film 17 which is provided between adjacent vertical transistors.Type: GrantFiled: February 14, 2011Date of Patent: October 2, 2012Assignee: Elpida Memory, Inc.Inventors: Yoshinori Ikebuchi, Yoshihiro Takaishi
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Patent number: 8273261Abstract: The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.Type: GrantFiled: March 30, 2010Date of Patent: September 25, 2012Assignee: Micron Technology, Inc.Inventor: Prashant Raghu
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Patent number: 8273652Abstract: A method of manufacturing a semiconductor device includes providing a substrate having junction regions and contact plugs formed thereon. A second insulating layer is formed over a first insulating layer and includes first and second pad holes extending in different directions and exposing the contact plugs. First and second conductive pads are formed in the first and second pad holes, respectively. A third insulating layer is formed and includes dual damascene patterns and pad contact holes. The dual damascene pattern exposes the first conductive pad, and each pad contact hole exposes a second conductive pad. First pad contact plugs and a first bit line are formed in the dual damascene pattern and a second pad contact plug is formed in each pad contact hole. A fourth insulating layer including trenches is formed. Each trench exposes a second pad contact plug. A second bit line is formed in each trench.Type: GrantFiled: September 27, 2011Date of Patent: September 25, 2012Assignee: Hynix Semiconductor Inc.Inventor: Sang Min Kim
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Patent number: 8269330Abstract: A MOSFET pair with a stack capacitor is disclosed herein. It can regulate the input voltage and optimize a short EMI loop. It has a bottom lead frame and an up lead frame, which can simultaneously dissipate the heat generated by two MOSFETs to achieve excellent thermal-dissipation. It can adopt solder, Ag epoxy, or gold balls to implement the electrical bonding of two MOSFETs with the bottom lead frame and the up lead frame to achieve excellent structural flexibility. A device, such as an IGBT, a diode, an inductor, a choke, and a heat sink, can be stacked above the up lead frame to form a powerful SiP module. A corresponding method of manufacturing the MOSFET pair with a stack capacitor is also disclosed herein, which is simple, time-saving, flexible, cost-effective, and facile.Type: GrantFiled: April 22, 2011Date of Patent: September 18, 2012Assignee: Cyntec Co., Ltd.Inventors: Han-Hsiang Lee, Yi-Cheng Lin, Da-Jung Chen
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Publication number: 20120228690Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.Type: ApplicationFiled: May 14, 2012Publication date: September 13, 2012Inventors: Satoshi MAEDA, Yasushi Sekine, Tetsuya Watanabe
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Patent number: 8264062Abstract: A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film.Type: GrantFiled: August 18, 2006Date of Patent: September 11, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Kenichi Watanabe
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Publication number: 20120211815Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first groove; and a plurality of first pillars over the substrate. The plurality of first pillars is disposed beside the first groove. A first insulator is disposed in the first groove. A bit contact is disposed in the first groove and over the first insulator. The bit contact is coupled to side surfaces of the plurality of first pillars.Type: ApplicationFiled: February 16, 2012Publication date: August 23, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Noriaki MIKASA
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Patent number: 8247855Abstract: A ferroelectric device employs ferroelectric electrodes as local interconnect(s). One or more circuit features are formed within or on a semiconductor body. A first dielectric layer is formed over the semiconductor body. Lower contacts are formed within the first dielectric layer. A bottom electrode is formed over the first dielectric layer and on the lower contacts. A ferroelectric layer is formed on the bottom electrode. A top electrode is formed on the ferroelectric layer. A second dielectric layer is formed over the first dielectric layer. Upper contacts are formed within the second dielectric layer and in contact with the top electrode. Conductive features are formed on the upper contacts.Type: GrantFiled: September 12, 2006Date of Patent: August 21, 2012Assignee: Texas Instruments IncorporatedInventor: Scott R. Summerfelt
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Patent number: 8242551Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.Type: GrantFiled: March 4, 2009Date of Patent: August 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Kuo-Chi Tu, Chun-Yao Chen
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Publication number: 20120199842Abstract: A highly integrated DRAM is provided. A bit line is formed over a first insulator, a second insulator is formed over the bit line, third insulators which are in a stripe shape and the like are formed over the second insulator, and a semiconductor region and a gate insulator are formed to cover one of the third insulators. The bit line is connected to the semiconductor region through first contact plugs. Then, a conductive film is formed and subjected to anisotropic etching to form word lines at side surfaces of the third insulators, and a second contact plug is formed to be connected to a capacitor at a top of the one of the third insulators. By synchronizing the word lines, electric charge is accumulated or released through the capacitor. With such a structure, the area of a memory cell can be 4F2.Type: ApplicationFiled: January 27, 2012Publication date: August 9, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Yasuhiko TAKEMURA
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Patent number: 8237209Abstract: A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate and a MIM capacitor over the substrate. The MIM capacitor includes a bottom plate, an insulating layer over the bottom plate, and a top plate over the insulating layer. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate and a metal-containing gate electrode free from polysilicon on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material and has a same thickness as the bottom plate.Type: GrantFiled: August 23, 2011Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Long Chang, David Ding-Chung Lu, Chia-Yi Chen, I-Lu Wu
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Patent number: 8237244Abstract: A method of manufacturing a semiconductor device includes forming a lower electrode on a semiconductor substrate, applying a photoresist on the lower electrode, forming an opening in the photoresist spaced from the periphery of the lower electrode, forming a high-dielectric constant film of a high-k material having a dielectric constant of 10 or more, performing liftoff so that the high-dielectric-constant film remains on the lower electrode, and forming an upper electrode on the high-dielectric-constant film remaining after the liftoff.Type: GrantFiled: October 19, 2010Date of Patent: August 7, 2012Assignee: Mitsubishi Electric CorporationInventor: Masahiro Totsuka
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Patent number: 8237208Abstract: Provided is a semiconductor device including a MIM capacitor, and having excellent waterproof property and antioxidant property even when being formed between wiring layers. The semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first wiring layer embedded in the first insulating film, a wiring cap film for covering the first wiring layer, the MIM capacitor formed on the wiring cap film, a hydrogen barrier film for covering the MIM capacitor, a second insulating film formed on the hydrogen barrier film, conductive plugs passing through the second insulating film and the hydrogen barrier film, one of which being connected to an upper electrode of the MIM capacitor and the other of which being connected to a lower electrode of the MIM capacitor, and a second wiring layer connected to the conductive plugs, and the upper and lower electrodes of the MIM capacitor.Type: GrantFiled: November 5, 2008Date of Patent: August 7, 2012Assignee: Renesas Electronics CorporationInventor: Takayuki Iwaki
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Publication number: 20120193697Abstract: A highly integrated DRAM is provided. A circuit for driving a memory cell array is formed over a substrate, a bit line is formed thereover, and a semiconductor region, word lines, and a capacitor are formed over the bit line. Since the bit line is located below the semiconductor region, and the word lines and the capacitor are located above the semiconductor region, the degree of freedom of the arrangement of the bit line is high. When an open-bit-line DRAM is formed, an area per memory cell less than or equal to 6F2, or when a special structure is employed for a cell transistor, an area per memory cell less than or equal to 4F2 can be achieved.Type: ApplicationFiled: January 26, 2012Publication date: August 2, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Yasuhiko TAKEMURA
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Publication number: 20120193696Abstract: In order to achieve the reduction of contact resistance by forming a metal silicide layer with a sufficient thickness in an interface between a polycrystalline silicon plug and an upper conductive plug, the polycrystalline silicon plug contains germanium, which is ion-implanted before forming the metal silicide layer.Type: ApplicationFiled: January 25, 2012Publication date: August 2, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Yoichi FUKUSHIMA
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Patent number: 8232189Abstract: The present invention provides a manufacturing method of a dielectric film which reduces a leak current value while suppressing the reduction of a relative permittivity, suppresses the reduction of a deposition rate caused by the reduction of a sputtering rate, and also provides excellent planar uniformity. A dielectric film manufacturing method according to an embodiment of the present invention is forms a dielectric film of a metal oxide mainly containing Al, Si, and O on a substrate, and comprises steps of forming the metal oxide having an amorphous structure in which a molar fraction between an Al element and a Si element, Si/(Si+Al), is 0<Si/(Si+Al)?0.1, and subjecting the metal oxide having the amorphous structure to annealing treatment at a temperature of 1000° C. or more to form the metal oxide including a crystalline phase.Type: GrantFiled: December 21, 2010Date of Patent: July 31, 2012Assignee: Canon Anelva CorporationInventors: Junko Ono, Naomu Kitano, Takashi Nakagawa
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Patent number: 8227849Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.Type: GrantFiled: February 17, 2010Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Ebenezer E Eshun, Ronald J Bolam, Douglas D Coolbaugh, Keith E Downes, Natalie B Feilchenfeld, Zhong-Xiang He
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Patent number: 8222683Abstract: To realize miniaturization/high integration and increase in the amount of accumulated charges, and to give a memory structure having a high reliability. A 1 transistor 1 capacitor (1T1C) structure having 1 ferroelectric capacitor structure and 1 selection transistor every memory cell is adopted, and respective capacitor structures are disposed respectively in either one layer of interlayer insulating films of 2 layers having different heights from the surface of a semiconductor substrate.Type: GrantFiled: September 6, 2006Date of Patent: July 17, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Yoshimasa Horii
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Patent number: 8217439Abstract: Some embodiments include methods of forming capacitors. A first capacitor storage node may be formed within a first opening in a first sacrificial material. A second sacrificial material may be formed over the first capacitor storage node and over the first sacrificial material, and a retaining structure may be formed over the second sacrificial material. A second opening may be formed through the retaining structure and the second sacrificial material, and a second capacitor storage node may be formed within the second opening and against the first storage node. The first and second sacrificial materials may be removed, and then capacitor dielectric material may be formed along the first and second storage nodes. Capacitor electrode material may then be formed along the capacitor dielectric material. Some embodiments include methods of forming DRAM unit cells, and some embodiments include DRAM unit cell constructions.Type: GrantFiled: April 5, 2011Date of Patent: July 10, 2012Assignee: Micron Technology, Inc.Inventor: John Kennedy
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Patent number: 8212299Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1?x)O2(0<x<1), (Zry, Ti1?y)O2(0<y<1), (Hfz, Ti1?z)O2(0<z<1), (Zrk,Til, Hfm)O2(0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.Type: GrantFiled: June 13, 2002Date of Patent: July 3, 2012Assignee: Renesas Electronics CorporationInventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
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Patent number: 8207563Abstract: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure comprising a fluid pervious material. A capacitor dielectric material is deposited over the capacitor electrodes through the fluid pervious material of the retaining structure effective to deposit capacitor dielectric material over portions of the sidewalls received below the retaining structure. Capacitor electrode material is deposited over the capacitor dielectric material through the fluid pervious material of the retaining structure effective to deposit capacitor electrode material over at least some of the capacitor dielectric material received below the retaining structure. Integrated circuitry independent of method of fabrication is also contemplated.Type: GrantFiled: December 13, 2006Date of Patent: June 26, 2012Assignee: Round Rock Research, LLCInventors: Cem Basceri, Gurtej S. Sandhu
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Patent number: 8207568Abstract: Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.Type: GrantFiled: September 19, 2005Date of Patent: June 26, 2012Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Keith E. Downes, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Anthony K. Stamper
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Patent number: 8207567Abstract: A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.Type: GrantFiled: November 19, 2008Date of Patent: June 26, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Chi Chin, Ming-Chu King, Chen Cheng Chou
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Patent number: 8207565Abstract: A semiconductor device includes: a stacked body including a conductive layer and an insulating layer alternately stacked on a base body; a pair of wall portions formed on the base body with a height equivalent to or larger than a thickness of the stacked body and opposed with a spacing wider than a thickness for one layer of the conductive layer; a contact layer interposed between the wall portions and connected to the conductive layer in the stacked body through an open end between the wall portions; and a contact electrode provided on the contact layer and connected to the contact layer.Type: GrantFiled: November 20, 2009Date of Patent: June 26, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Koichi Sato
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Publication number: 20120153371Abstract: A dynamic random access memory cell having vertical channel transistor includes a semiconductor pillar, a drain layer, an assisted gate, a control gate, a source layer, and a capacitor. The vertical channel transistor has an active region formed by the semiconductor pillar. The drain layer is formed at the bottom of the semiconductor pillar. The assisted gate is formed beside the drain layer, and separated from the drain layer by a first gate dielectric layer. The control gate is formed beside the semiconductor pillar, and separated from the active region by a second gate dielectric layer. The source layer is formed at the top of the semiconductor pillar. The capacitor is formed to electrical connect to the source layer.Type: ApplicationFiled: February 17, 2011Publication date: June 21, 2012Applicant: POWERCHIP TECHNOLOGY CORPORATIONInventors: Hui-Huang Chen, Chih-Yuan Chen, Sheng-Fu Yang, Chun-Cheng Chen
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Patent number: 8198664Abstract: A semiconductor memory device including a plurality of supports extending parallel to each other in a first direction on a semiconductor substrate, and capacitor lower electrode rows including a plurality of capacitor lower electrodes arranged in a line along the first direction between two adjacent supports from among the plurality of supports, each capacitor lower electrode including outside walls, wherein each of the capacitor lower electrodes includes two support contact surfaces on the outside walls of the capacitor lower electrode, the support contact surfaces respectively contacting the two adjacent supports from among the plurality of supports.Type: GrantFiled: October 28, 2009Date of Patent: June 12, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Gil-sub Kim
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Patent number: 8193569Abstract: A non-volatile semiconductor memory device having an ion conductive layer, and methods of fabricating and operating the same are disclosed. The non-volatile memory device may include a substrate, a switching element formed in the substrate, and a storage node connected to the switching element, the storage node may include a lower electrode connected to the switching element, and used as an ion source; a data storage layer formed on the lower electrode, a portion thereof being spaced from the lower electrode; a side electrode spaced from the lower electrode, a side surface thereof being connected to a portion of the data storage layer spaced from the lower electrode; and an upper electrode formed on the data storage layer, or may include a lower electrode connected to the switching element, and used as an ion source; and a data storage layer formed on the lower electrode; an upper electrode formed on the data storage layer.Type: GrantFiled: August 24, 2006Date of Patent: June 5, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Jung-hyun Lee
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Patent number: 8188527Abstract: A semiconductor device with an embedded capacitor structure. A dielectric layer is disposed on a substrate, having a contact opening exposing the substrate and a trench opening above the contact opening. A first metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings. A second metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings. A capacitor dielectric layer is interposed between the first and second metal electrode layers. A method for fabricating the semiconductor device is also disclosed.Type: GrantFiled: June 7, 2006Date of Patent: May 29, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Chyi Liu, Chi-Hsin Lo
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Patent number: 8188529Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.Type: GrantFiled: January 7, 2009Date of Patent: May 29, 2012Assignee: Elpida Memory, Inc.Inventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda
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Publication number: 20120126301Abstract: One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed.Type: ApplicationFiled: January 30, 2012Publication date: May 24, 2012Applicant: Qimonda AGInventors: Gerhard Kunkel, Peter Baars
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Patent number: 8183616Abstract: Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.Type: GrantFiled: September 1, 2010Date of Patent: May 22, 2012Assignee: Renesas Electronics CorporationInventors: Tsuyoshi Fujiwara, Toshinori Imai, Takeshi Saikawa, Yoshinori Kawasaki, Mitsuhiro Toya, Shunji Mori, Yoshiyuki Okabe
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Patent number: 8183615Abstract: A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.Type: GrantFiled: October 29, 2010Date of Patent: May 22, 2012Assignee: Micron Technology, Inc.Inventor: Anton P. Eppich
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Patent number: 8183614Abstract: The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.Type: GrantFiled: November 11, 2011Date of Patent: May 22, 2012Assignee: Nanya Technology CorporationInventor: Shin-Yu Nieh
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Publication number: 20120119279Abstract: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.Type: ApplicationFiled: January 24, 2012Publication date: May 17, 2012Inventor: Leonard Forbes
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Publication number: 20120119278Abstract: A semiconductor device includes a semiconductor substrate and a first gate structure. The semiconductor substrate has a first groove and a first pillar defined by the first groove. The first groove and the first pillar are adjacent to each other. The first gate structure is disposed in the first groove. The first gate structure includes a first gate insulating film and a first gate electrode. The first gate structure is separated by a first gap from the first pillar.Type: ApplicationFiled: November 15, 2011Publication date: May 17, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Noriaki MIKASA
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Patent number: 8178404Abstract: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode.Type: GrantFiled: October 24, 2008Date of Patent: May 15, 2012Assignee: NXP B.V.Inventors: Michael Olewine, Kevin Saiz
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Patent number: 8169014Abstract: System and method for an improved interdigitated capacitive structure for an integrated circuit. A preferred embodiment comprises a first layer of a sequence of substantially parallel interdigitated strips, each strip of either a first polarity or a second polarity, the sequence alternating between a strip of the first polarity and a strip of the second polarity. A first dielectric layer is deposited over each strip of the first layer of strips. A first extension layer of a sequence of substantially interdigitated extension strips is deposited over the first dielectric layer, each extension strip deposited over a strip of the first layer of the opposite polarity. A first sequence of vias is coupled to the first extension layer, each via deposited over an extension strip of the same polarity. A second layer of a sequence of substantially parallel interdigitated strips can be coupled to the first sequence of vias.Type: GrantFiled: January 9, 2006Date of Patent: May 1, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yueh-You Chen, Chung-Long Chang, Chih-Ping Chao
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Patent number: 8169013Abstract: A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)o2 (0<y<1), (Hfz, Ti1-z)92 (0<z<1 and (Zrk, Til, Hfm)o2 (0<k, l, m<1, k+l+m?1), wherein each of the first and second transistors has a refractory metal silicide layer formed over each of the source and drain regions thereof and the lower metal electrode is connected through a metal plug to the refractory metal silicide layer formed over one oType: GrantFiled: December 12, 2006Date of Patent: May 1, 2012Assignee: Renesas Electronics CorporationInventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
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Patent number: 8169012Abstract: A semiconductor device and a method of fabricating a semiconductor device provide high quality cylindrical capacitors. The semiconductor device includes a substrate defining a cell region and a peripheral circuit region, a plurality of capacitors in the cell region, and supports for supporting lower electrodes of the capacitors. The lower electrodes are disposed in a plurality of rows each extending in a first direction. A dielectric layer is disposed on the lower electrodes, and an upper electrode is disposed on the dielectric layer. The supports are in the form of stripes extending longitudinally in the first direction and spaced from each other along a second direction. Each of the supports engages the lower electrodes of a respective plurality of adjacent rows of the lower electrodes. Each one of the supports is also disposed at a different level in the device from the support that is adjacent thereto in the second direction.Type: GrantFiled: October 8, 2008Date of Patent: May 1, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-kug Bae, Si-hyeung Lee, Tae-hyuk Ahn, Seok-hwan Oh
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Patent number: 8164120Abstract: An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor. In forming a capacitor and a fuse on a semiconductor substrate by a conventional method, at least three etching masks are selectively used to pattern respective layers to form the capacitor and fuse before wiring connection. The number of etching masks can be reduced in manufacturing a semiconductor device having capacitors, fuses and MOS field effect transistors so that the number of processes can be reduced and it becomes easy to improve the productivity and reduce the manufacture cost.Type: GrantFiled: November 18, 2010Date of Patent: April 24, 2012Assignee: Yamaha CorporationInventor: Masayoshi Omura
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Patent number: 8164129Abstract: A semiconductor device includes a plurality of MOS transistors and wiring connected to a source electrode or a drain electrode of the plurality of MOS transistors and, the wiring being provided in the same layer as the source electrode and the drain electrode in a substrate, or in a position deeper than a surface of the substrate.Type: GrantFiled: July 1, 2009Date of Patent: April 24, 2012Assignee: Elpida Memory, Inc.Inventor: Hiroyuki Uchiyama
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Patent number: 8159012Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.Type: GrantFiled: September 26, 2008Date of Patent: April 17, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-cheol Lee, Jun-noh Lee, Ki-vin Im, Ki-yeon Park, Sung-hae Lee, Sang-yeol Kang
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Publication number: 20120086065Abstract: Provided is a semiconductor device having a vertical channel transistor and method of fabricating the same. The semiconductor device includes first and second field effect transistors, wherein a channel region of the first field effect transistor serves as source/drain electrodes of the second field effect transistor, and a channel region of the second field effect transistor serves as source/drain electrodes of the first field effect transistor.Type: ApplicationFiled: April 29, 2011Publication date: April 12, 2012Inventors: Daeik KIM, Yongchul Oh, Yoosang Hwang, Hyun-Woo Chung, Young-Seung Cho
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Publication number: 20120086066Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern.Type: ApplicationFiled: April 29, 2011Publication date: April 12, 2012Inventors: Daeik KIM, HyeongSun HONG, Yoosang HWANG, Hyun-Woo CHUNG
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Patent number: 8148216Abstract: A nonvolatile semiconductor memory of an aspect of the present invention comprises a semiconductor substrate, a pillar-shaped semiconductor layer extending in the vertical direction with respect to the surface of the semiconductor substrate, a plurality of memory cells arranged in the vertical direction on the side surface of the semiconductor layer and having a charge storage layer and a control gate electrode, a first select gate transistor arranged on the semiconductor layer at an end of the memory cells on the side of the semiconductor substrate, and a second select gate transistor arranged on the semiconductor layer on the other end of the memory cells opposite to the side of the semiconductor substrate, wherein the first select gate transistor includes a diffusion layer in the semiconductor substrate and is electrically connected to the pillar-shaped semiconductor layer by way of the diffusion layer that serves as the drain region.Type: GrantFiled: December 21, 2010Date of Patent: April 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Fumitaka Arai, Riichiro Shirota
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Patent number: 8148764Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conducive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.Type: GrantFiled: July 19, 2011Date of Patent: April 3, 2012Assignee: Hynix Semiconductor Inc.Inventors: Cheol Hwan Park, Ho Jin Cho, Dong Kyun Lee
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Patent number: 8143723Abstract: A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or metal silicide, and the second insulating film being a silicon nitride film formed to cover the first insulating film and the upper surface and side wall of the conductive pattern. The first insulating film may be formed to cover the upper surface and side wall of the conductive pattern. A semiconductor device and its manufacture method are provided which can realize high integrated DRAMs of 256 M or larger without degrading reliability and stability.Type: GrantFiled: December 3, 2008Date of Patent: March 27, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Shinichiroh Ikemasu, Narumi Okawa
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Patent number: 8143698Abstract: A problem of an increased manufacturing cost is caused in conventional semiconductor devices. A semiconductor device 1 includes: a lower electrode 102 provided on a semiconductor substrate 101; an insulating film 105, provided on the lower electrode 102 so as to be in contact with the lower electrode 102; an upper electrode 103, provided on the insulating film 105 so as to be in contact with the insulating film 105; an opening portion 121, provided in the lower electrode 102 and extending through the lower electrode 102; and an opening portion 122, provided in the upper electrode 103 and extending through the upper electrode 103. The insulating film 123 is embedded in the opening portion 121 that is provided in the lower electrode 102. Similarly, the insulating film 124 is embedded in the opening portion 122 that is provided in the upper electrode 103.Type: GrantFiled: August 4, 2009Date of Patent: March 27, 2012Assignee: Renesas Electronics CorporationInventor: Chikashi Yoshinaga