Abstract: First of all, a semiconductor substrate is provided. On the semiconductor substrate, a word line is formed and covered with a insulating layer. Next, forming a connected device in the insulating layer to connect with the first conducting line layer. In order, a pinned layer is then deposited along the first insulating layer and the connected device. On top of the pinned layer, an insulating tunnel barrier layer is formed. Then a free layer is deposited on the insulating tunnel barrier layer. There is a single large MTJ that covers the entire surface of the first insulating layer on the conducting line layer. This large MTJ is then patterned into a small MTJ by etching process and through the free layer to the surface of the insulating tunnel barrier layer. Subsequently, the small MTJ are then covered with a second insulating layer. Afterward, opening a contact hole in the second insulating layer to the top of the small MTJ.

Abstract: A memory device includes a plurality of cells, each having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away from the first location on the semiconductor material and a plurality of islands of semiconductor material. The islands have a maximum dimension of three to five nanometers and are surrounded by an insulator having a thickness of between five and twenty nanometers. The islands and the surrounding insulator are formed in pores extending into the semiconductor material between the first and second electrodes. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.

Abstract: Described in the disclosure is a method for fabricating high-capacitance capacitive elements that are integrated in a semiconductor substrate. First a dielectric layer is formed over the surface of the substrate and a metal layer is deposited thereon. The metal layer is patterned and etched to form lower plates of the capacitive elements, as well as to form interconnection pads. Then, an intermediate dielectric layer is deposited on the lower plates and interconnection pads, and over the entire exposed surface of the substrate. Following that, a sacrificial conductive layer is deposited onto the intermediate dielectric layer, and the upper plates of the capacitive elements are formed out of the sacrificial conductive layer. Then, an upper dielectric layer is formed over the entire semiconductor, and openings are formed in this layer for the upper plates and the interconnection pads.

Abstract: A magnetic random access memory (RAM) is implemented by a gate electrode formed on an active region in a semiconductor substrate and being a word line used as a write line, a ground line formed in one side of the word line, a lower lead layer formed in the other side of the word line, a seed layer connected to the lower lead layer and overlapped with the word line, a magnetic tunnel junction (MTJ) cell made on the seed layer and located in an upper portion of the word line and an upper lead layer being a bit line formed connected to the MTJ cell.

Abstract: An electronic fast switch for operation at room temperature utilizing uniform silicon nanoparticles (˜1 nm with about 1 part per thousand exceeding 1 nm) between two conducting electrodes. The silicon nanoparticles, when on an n-type silicon substrate exhibit, at zero bias, a large differential conductance, approaching near full transparency. The conductance is observed after one of the electrode is first biased at a voltage in the range 3 to 5 eV (switching voltage), otherwise the device does not conduct (closed). A practical MOSFET switch of the invention includes the silicon nanoparticles in a body of the MOSFET, with the gate and substrate forming the two conducting electrodes. Electrodes may be realized by metal in other switches of the invention.

Abstract: A memory device includes a plurality of cells, each having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away from the first location on the semiconductor material and a plurality of islands of semiconductor material. The islands have a maximum dimension of three to five nanometers and are surrounded by an insulator having a thickness of between five and twenty nanometers. The islands and the surrounding insulator are formed in pores extending into the semiconductor material between the first and second electrodes. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.

Abstract: A semiconducting yttrium-barium-copper-oxygen(YBCO) device which locally converts a semiconducting YBCO film to a nonconducting YBCO film by a conductive atomic force microscope (AFM), a superconducting YBCO device which locally converts a superconducting YBCO film to nonsuperconducting YBCO by an AFM, and manufacturing methods thereof are provided. According to a method of manufacturing a semiconducting YBCO device or a superconducting YBCO device locally converted by an AFM tip, a voltage is applied to the local region of a semiconducting YBCO channel or a superconducting YBCO channel by an AFM tip. This can produce a nonconducting YBCO region or nonsuperconducting YBCO region to thereby manufacture a tunnel junction easily without any patterning process by microfabrication including photolithography and dry/wet etching.

Abstract: The invention is a process for reducing roughness of a surface of a superconductor material (23) having an undesirable surface roughness (30 and 32) and a trilayer superconductor integrated circuit (100). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer (40) to fill the undesirable surface roughness and to produce an exposed oxide surface (42) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface (44) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.

Abstract: In a multilayer logic device or processor device with a plurality of individually matrix-addressable stacked thin layers of an active material, the active material in each layer is provided between a first electrode set and a second electrode set wherein the electrodes in the first set realize the columns and the electrodes in the second set the rows in an orthogonal array. The intersections between the electrodes in the array define logic cells in the layer of active material, and the stacked layers of active material are provided on a common supporting substrate. A separation layer with determined electrical or thermal properties is provided between each layer of active material.

Abstract: A semiconductor light emitting device is disclosed. The device has a tunnel junction disposed between a p-type layer and an n-type layer. The tunnel junction includes a tunnel barrier that is a non-continuous layer. The device also includes means for causing lateral electron flow into the tunnel junction.

Abstract: A superconductive tunnel junction device in which quasiparticles in a superconductive region (S1), relax into a normal metal trap (N1) releasing their potential energy in electron-electron interactions to increase the number of excited charge carriers in the trap. The excited charge carriers tunnel through an insulating tunnel junction barrier (I2) into a second superconductive region (S2). The quasiparticles in the first superconductive region are formed either by absorption or energetic particles/radiation or by injection by charge carriers tunneling in from a base region which can be of normal metal (N0) or superconductor (or both) of semiconductor. The current from the trap to the second superconductor is higher than that out of the base region thus providing current amplification. The device can thus form a three terminal transistor-like device. It can be used as or in particle/radiation detectors, as an analogue signal amplifier, microrefrigerator or digital switch.

Abstract: The present invention relates on an interferometer arrangement comprising a source electrode and a drain electrode, a base electrode to which the source electrode and the drain electrode are connected through tunnel barriers, the base electrode thus forming a double barrier quantum well, and first and second superconducting gate electrodes to control the source-drain current. The base electrode comprises a ferromagnetic material enabling resonant tunneling of source-drain electrons when there are bound states within the quantum well structure matching the energy of said source-drain electrons. The invention also relates to a logical element comprising such an interferometer arrangement and to a method of controlling the conductance of an interferometer.

Abstract: A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The device of the present invention can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The present invention enables construction of molecular electronic devices on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The device is either partially or completely chemically assembled, and the key to the scaling is that the location of the devices on the substrate are defined once the devices have been assembled, not prior to assembly.

Abstract: A single-electron memory device using the electron-hole Coulomb blockade is provided. A single-electron memory device in accordance with an embodiment of the present invention includes a plurality of quantum dot tunnel-junction arrays, a gate electrode, and source and drain electrodes. The plurality of quantum dot tunnel-junction arrays include at least two tunnel-junctions, are parallelly coupled to each other, and are well separated from each other to prevent single-electron tunneling between them. One of the plurality of quantum dot tunnel-junction arrays includes the gate electrode, and the voltage applied to the gate electrode can vary the number of electron-hole pairs.

Abstract: A new switching element and a circuit device and the like using the same element are provided, which comprises semiconductor in which a channel region is formed at an interface with an insulating film, first and second terminals S, D, which are located in corresponding manner to both ends of the channel region, and through which a tunnel current is let to flow into the channel region, and a third terminal G giving a high frequency vibration to a potential barrier of the channel region through the insulating film, wherein the tunnel current flowing into the channel region is increased as a value of an exponential function is increased with a predetermined threshold vibration frequency as a boundary value.

Abstract: There is provided a single electron device. The device has weak links with bottle-neck figure in place of the tunnel junction of the prior device. The weak links are easily formed on the same substrate by simple processes and thus the integration of the single electron device can be easily achieved.

Abstract: The present invention relates to a tunnel barrier and to uses thereof, particularly in conjunction with devices and integrated circuits fabricated with silicon substrates, and including the preparation of tunnel diodes, dielectric structures, transistors, memory cells and the products embodying one or more of the same. The tunnel barrier of the invention is designed to confer effective and reliable charge transfer performance, and is particularly well suited for the fabrication of nonvolatile memory cells. In an embodiment of the invention, with the barrier incorporated in a diode, the present evacuee facilitates over 109 bi-directional charge transfers across the barrier without destroying it. The multiple layer nature of the barrier, coupled with the use of direct tunnel oxides, provides desirable functionality, stability, and resistance to dielectric degradation, thus improving operating, storage and retention characteristics over conventional nonvolatile devices.

Abstract: An MIM nonlinear device having a large nonlinearity coefficient that represents the sharpness of the voltage-current characteristic, a liquid crystal display panel with high image-quality that uses this device, and a manufacturing method of said MIM nonlinear device are provided. The MIM nonlinear device contains a first conductive film 22, an insulating film 24, and a second conductive film 26 laminated on a substrate 30. The insulating film 24 may contain water, and in the insulating film, in a thermal desorption spectrum, a peak derived from water in the insulating film is 225-300° C. Further, in said thermal desorption spectrum, the number of molecules calculated from the area of the peak derived from the water is preferably 5×1014/cm2 or more.

Abstract: Disclosed is a photodetector adapted to be used with a voltage source for replacing the conventional CCD. The photodetector includes a substrate electrically connected with an electrode of the voltage source for generating electron-hole pairs in response to a light, a conducting layer electrically connected with the other electrode of the voltage source, and an ultra thin (˜nm) insulating layer formed between the conducting layer and the substrate, wherein one of electrons and holes, excited by the light, in the substrate will move to the conducting layer through the insulating layer so as to form a photo current when the voltage source provides a bias voltage.

Abstract: A cathode-anode apparatus is constructed whereby the wafer under test, connected to a conducting wire, forms the cathode terminal and a copper plate, also connected to a conducting wire, forms the anode terminal. The wafer under test and the copper plate are immersed in a CuSO4—H2O solution. A positive dc voltage is applied to the copper plate; the dc current ionizes the CuSO4 solution and forms Cu2+ ions. These Cu2+ ions will diffuse to the wafer surface. Most of the Cu2+ ions will accumulate in and around defective contacts or vias in the semiconductor surface making these defective contacts or vias readily identifiable.

Abstract: An ultra high speed and high sensitivity photo detecting element is fabricated by laminating thin film layers of superconducting material and ferromagnetic material on a substrate. A photo detecting element composed of a photo detecting portion formed on a substrate by laminating alternately at least a thin film layer of ferromagnetic material and at least a thin film layer of high temperature superconducting material between which a thin film layer of insulating material is sandwiched and electrodes connected to the photo detecting portion.

Abstract: An improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: A magnetic material is used for the gate of a MOSFET, and tunnel junctions are formed between a magnetic electrode and the gate electrode, and between a nonmagnetic electrode and the gate electrode. The magnetic gate electrode is biased through the two tunnel junctions, and the drain current of the MOSFET changes with a change in an external magnetic field, according to the tunneling magnetoresistance effect. Thus, the MOSFET can be used as a magnetic sensor, as the reading element in a read/write head, or in a magnetic memory cell of a magnetic random access memory.

Abstract: A transistor operated by changing the electrostatic potential of an island disposed between two tunnel junctions. The transistor has an island of material which has a band gap (e.g. semiconductor material). Source and drain contacts are provided. The transistor has a first tunnel junction barrier disposed between island and source, and a second tunnel junction barrier disposed between island and drain. The island is Ohmically isolated from other parts of the transistor as well as a substrate. A gate electrode is capacitively coupled to the island so that a voltage applied to the gate can change the potential of the island. The transistor has n- and p-type embodiments. In operation, applying a gate voltage lowers (e.g., for positive gate bias) or raises (e.g., for negative gate bias) the conduction band and valence band of the island. When the conduction band or valence band aligns with the Fermi energy of the source and drain, tunneling current can pass between the source, island and drain.

Abstract: Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum conductive layers are preferably used in trench capacitors to act as recrystallization barriers.

Abstract: This invention is characterized in that a load resistor is constituted of a tunneling junction element(12), and a single-electron tunneling junction element(10) and the tunneling junction element(12) for load resistor are laminated to design a phase-locked circuit compact. Further, the load resistor(12) is comprised of a plurality of laminated tunneling junctions for load resistor so that the load resistor can have the proper resistance. A DC bias voltage is applied to the electrode(37) of the tunneling junction element for load resistor, and an AC pump voltage to one electrode(20) of the single-electron tunneling junction element. In the case of a plurality of phase-locked circuit gates, one electrodes of the single-electron tunneling junction elements are designed into a common electrode to which the AC pump voltage is applied, and the other electrodes are formed apart from one another two-dimensionally.

Abstract: A high-temperature (10 K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area.

Abstract: A photoelectric conversion apparatus of this invention has a high sensitivity and low noise, and can be formed to have a large area at a relatively low temperature since it has a light absorption layer (310), formed of a non-monocrystalline material, for absorbing light and generating photocarriers, and a multiplication layer (301, 303, 305, 307, 309) for multiplying the photocarriers generated by the light absorption layer.

Abstract: A first electrode 1 comprises an anode oxide electrode 5, a lower electrode 2 and signal electrodes, wherein the signal (electrodes are connected to each other by the anode oxide electrode when the anodic oxidation treatment is performed, while a second electrode comprises an upper electrode on a nonlinear resistor layer, a display electrode connected to the upper electrode, and a connecting electrode covering a part of the anode oxide electrode, wherein the lower electrode, the nonlinear resistor layer and the upper electrode constitute the nonlinear resistor, and wherein a part of the anode oxide electrode is separated at the side thereof which is also a side of the connecting electrode comprising the second electrode, thereby forming independent signal electrodes.

Abstract: The present invention proposes a structure of nonvolatile memory cell with a textured tunnel oxide and a high capacitive-coupling ratio. A non-tunnel oxide is formed on the semiconductor substrate. The tunnel oxides with textured surfaces are formed on the semiconductor substrate and are separated by the non-tunnel oxide. The source and drain are formed aligned to the tunnel oxides in the semiconductor substrate. The floating gate, the interpoly dielectric and the control gate, are formed in turn over the tunnel and non-tunnel oxides. Due to the textured structure of the tunnel oxide, the high-density and high-speed nonvolatile memory can be achieved.

Abstract: Thin-film switching elements (20,21) of a display device or the like include a first electrode (22,23) on a substrate (11) and a layer of switching material (24,25) on the first electrode. These switching elements may be semiconductor PIN or Schottky diodes, or MIMs, or TFTs. The switching material is typically .alpha.-Si:H in the case of the semiconductor diodes and TFTs, and tantalum oxide or silicon nitride in the case of the MIMs. An auxiliary layer (28,29) of insulating material is provided between the first electrode (22,23) and the layer of switching material (24,25), leaving an edge (30,31) of the first electrode uncovered, so that the layer of switching material is connected to this edge only. The switching elements with this construction can be patterned using an inexpensive proximity printer, and have a low capacitance value, so counter-acting kickback and crosstalk which can occur in a switching matrix, e.g in the display of television pictures.

Abstract: An electromagnetic-wave detector having an electromagnetic-wave detection unit having the structure that M (M.gtoreq.1) contiguous pairs of a metallic layer and an insulating layer are provided at the side of incidence of an electromagnetic-wave, such as X-rays.

Abstract: The semiconductor device comprises a first insulating layer formed on the semiconductor substrate, at least one double-deck semiconductor nanocrystal formed on the first insulating layer, the at least one double-deck semiconductor nanocrystal comprising a first semiconductor nanocrystal and a second semiconductor nanocrystal stacked one upon the other via a second insulating layer, and a third insulating layer selectively formed on the first insulating layer so as to cover the at least one double-deck semiconductor nanocrystal.

Abstract: The tunnel-effect device comprises an input electrode 3, an output electrode 4, and N control electrodes 5 separated with tunneling barriers, the latter barriers and the interbarrier space therein appear as an ordered structure of molecules and clusters establishing tunneling junctions; each control electrode 5 is located in the region of the ordered structure of molecules and clusters 2. The dimensions and properties of the molecules and clusters provide for single-electron correlated electron tunneling at a relatively high (room) temperature. The tunnel-effect device functions on the base of controlled correlated electron tunneling. Possibility of controlling the tunneling current opens the way to constructing various electronic gate circuits on the base of single-electron tunneling junctions and hence to preparing single-electron analog and digital devices, in particular, high-sensitivity sensors.

Abstract: In an MIM or MIS electron source that is formed by a first conductive layer 101, an insulating layer 103 that is formed onto said first conductive layer 101, and a second conductive layer 104 that is formed onto said insulating layer 103, wherein a voltage is applied between said first and second conductive layers 101,104, so as to cause a tunneling current to occur in said insulating layer 103, the film thickness of said insulating layer 103 and the film thickness of said second conductive layer 104 are formed so as to be uniform.

Abstract: A semiconductor device includes spaced apart source and drain regions formed in a semiconductor substrate and a gate electrode insulatively spaced from a channel region between the source region and the drain region by a gate insulating film. Insulating layers are respectively formed between the source region and the channel region and between the drain region and the channel region.

Abstract: An electron emission device exhibits a high electron emission efficiency. The device includes an electron supply layer of metal or semiconductor, an insulator layer formed on the electron supply layer, and a thin-film metal electrode formed on the insulator layer. The insulator layer is made of an amorphous dielectric substance and has a film thickness of 50 nm or greater and has an amorphous phase with an average grain size of 5 to 100 nm as a major component and a polycrystal phase as a minor component. When an electric field is applied between the electron supply layer and the thin-film metal electrode, the electron emission device emits electrons.

Abstract: The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.

Abstract: A semiconductor nonvolatile memory device capable of lowering an operation voltage such as an erase voltage and capable of lowering costs and a method of production of the same, wherein a thin film transistor acting as the memory transistor is formed with a semiconductor layer 31b having a channel formation region formed on an insulating substrate 10 made of glass or plastic, a charge storing layer 32a formed on the semiconductor layer, a control gate 33a formed above the charge storing layer, and source and drain regions formed connected to the channel formation region.

Abstract: A magnetic sensor comprises a SQUID made of a superconducting thin film. The superconducting thin film has a washer pattern and a terminal portion. The washer pattern has a non-square one hole pattern and a pair of slit patterns. The hole pattern has rectangle shape and includes the center of the washer pattern. The slit patterns having a straight shape growing parallel to the long side of the hole pattern, from the outside edge of the washer pattern toward the inside of the washer pattern. This outside edge of the washer pattern is the nearest to the hole pattern. There is an artificial grain boundary in the domain that spacing between the hole pattern and the slit pattern is narrowest. There is no artificial grain boundary in the other domain at all.

Abstract: A semiconductor device comprises mutually separated first and third barrier layers interposed between the first and second patterned terminals. The device operates by the resonant tunneling of carriers from the second terminal to the first terminal. The first terminal is patterned into a section and a plurality of layers comprising the mutually separated first and second barrier layers are formed on top of the first terminal. A second terminal is then formed on top of the plurality of semiconductor layers. The second terminal is then patterned so that it only overlies the first terminal in confined region. A front-gate is then formed on top of the patterned second terminal.

Abstract: A high-temperature (10 K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area.

Abstract: The invention relates to a superconductive tunnel element comprising superconductors, barriers and insulators, which tunnel element has the following layer structure: superconductor (S1), insulator (I), superconductor (S2), barrier (B), superconductor (S3), insulator (I) and superconductor (S4).

Abstract: A wavelength-domain-multiplication memory comprises a first semiconductor layer including a first conductivity type impurity, a carrier barrier semiconductor layer formed on the first semiconductor layer, and quantum dots formed in the carrier barrier semiconductor layer.

Abstract: The liquid crystal display apparatus of this invention includes a pair of substrates facing each other and a liquid crystal layer interposed between the pair of substrates. At least one of the pair of substrates having on a surface thereof: pixel electrodes arranged in rows and columns; a plurality of signal lines; and a plurality of nonlinear switching elements for connecting each of the plurality of signal lines to a corresponding column of pixel electrodes. Each switching element has a lower electrode, an insulating film formed on the lower electrode, and an upper electrode formed on the insulating electrode, the lower electrode being a branch of the corresponding signal line, wherein the lower electrode has a first portion with a width larger than a width of a second portion overlapping the insulating film and the upper electrode, the first portion being located farther from the corresponding signal line than the second portion.

Abstract: A high-temperature (10K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area.

Abstract: A superconductor device comprises a Schottky barrier region S.sub.B for selectively passing injected carriers and a collector barrier region L.sub.B for selectively blocking leakage carriers. The Schottky barrier region is formed in a low permittivity region .epsilon..sub.L between the first operating region (B) made of superconductor material and the second operating region (C) made of either semiconductor material or metallic material. A resonance region R is formed in the low permittivity region .epsilon..sub.L.

Abstract: A single-electron controlling magnetoresistance element which comprises, a couple of first ferromagnetic bodies each magnetized in a first direction, a second ferromagnetic body magnetized in a second direction in an initial direction and sandwiched between the couple of first ferromagnetic bodies with a tunnel junction interposed therebetween respectively, and means for directing the magnetization direction of the second ferromagnetic body to a direction different from the second direction, wherein a charging energy E.sub.c of a single electron in at least one of the tunnel junctions interposed between the first ferromagnetic body and the second ferromagnetic body meets the following conditions:E.sub.c >>k.sub.B T (2)E.sub.c >>h/R.sub.t C (3)wherein k.sub.B T is a thermal energy at an operation temperature, h is a Planck's constant, R.sub.t is a junction tunnel resistance, and C is a junction capacity.

Abstract: Disclosed are single electron digital devices, in which the screening lengths of individual device islands are between 0.5 and 1.0 islands. This range permits island occupancy to be bias independent, permitting the devices to hold or process digital information independent of device biases. This range of screening lengths can be effected by choice of device parameters which are sufficiently modest to permit practical fabrication of these devices.