Abstract: The invention relates to an interconnection network and an integrated circuit and a method for manufacturing the same. Furthermore, the invention relates to a method for signal transfer between semiconductor structures. The invention is characterized in that a signal of a first semiconductor structure is supplied to a transmitter, which generates from the signal a plasmon wave, and couples the latter into a waveguide. The plasmons fed through the waveguide are received by a receiver, converted to an electric signal and forwarded to a second semiconductor structure.

Abstract: According to an embodiment, a semiconductor memory device capable of stably operating even when an element is shrunk is provided. The semiconductor memory device of the embodiment includes: first and second diodes serially connected between power sources of two different potentials, formed by nanowires, and exhibiting negative differential resistances; and a select transistor connected between the first diode and the second diode. The nanowires are preferably silicon nanowires. The thickness of the silicon nanowires is preferably 8 nm or less.

Abstract: A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped regions defined by a first set of a plurality of active regions, (b) providing a mask for disposing a plurality of polysilicon gates defined by a second set of a plurality of exposed regions, wherein an offset between a first member of the plurality of the exposed region of the first set differs in offset from a second member of the plurality of the exposed region of the second set, and (c) fabricating the parallel redundant array of single-electron devices as a function of the offset.

Abstract: A structure and method for transferring electronic charge or heat or light between substrates. The structure includes first and second substrates separated from one another and a plurality of localized spacers connecting the first and second substrates together. At least one of the localized spacers having a lateral dimension less than 350 nm. A sub-micron separation distance between the first and second substrates is configured to provide carrier tunneling or to provide heat transfer or light transfer between the first and second substrates. The method provides charge carriers or heat or light to a first substrate. The first substrate is separated from a second substrate by at least one localized spacer having a lateral dimension less than 350 nm and tunnels the charge carriers or couples the heat or couples light from the first substrate to the second substrate across a sub-micron gap between the first and second substrates formed by the at least one localized spacer.

Abstract: A quantum computing device and method employs qubit arrays of entangled states using negative refractive index lenses. A qubit includes a pair of neutral atoms separated by or disposed on opposite sides of a negative refractive index lens. The neutral atoms and negative refractive index lens are selectively energized and/or activated to cause entanglement of states of the atoms. The quantum computing device enjoys a novel architecture that is workable and scalable in terms of size and wavelength.

Abstract: The present invention discloses a light-emitting semiconductor device, includes: a first electrode that is made of a high reflective metal; a second electrode; a tunnel junction layer coupling to the first electrode through a first ohmic contact and generating a tunnel current by applying a reverse bias voltage between the first electrode and the second electrode; a light-emitting layer provided between the tunnel junction layer and the second electrode.

Abstract: A rewritable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.

Abstract: Methods of forming planar carbon nanotube (“CNT”) resistivity-switching materials for use in memory cells are provided, that include depositing first dielectric material, patterning the first dielectric material, etching the first dielectric material to form a feature within the first dielectric material, depositing CNT resistivity-switching material over the first dielectric material to fill the feature at least partially with the CNT resistivity-switching material, depositing second dielectric material over the CNT resistivity-switching material, and planarizing the second dielectric material and the CNT resistivity-switching material so as to expose at least a portion of the CNT resistivity-switching material within the feature. Other aspects are also provided.

Abstract: A multilayer structure with zirconium-oxide tunnel barriers. In one embodiment, the multilayer structure includes a first niobium (Nb) layer, a second niobium (Nb) layer, and a plurality of zirconium-oxide tunnel barriers sandwiched between the first niobium (Nb) layer and the second niobium (Nb) layer, wherein the plurality of zirconium-oxide tunnel barriers is formed with N layers of zirconium-oxide, N being an integer greater than 1, and M layers of zirconium, M being an integer no less than N, such that between any two neighboring layers of zirconium-oxide, a layer of zirconium is sandwiched therebetween.

Abstract: A thin film transistor, e.g., for use in an organic light emitting display, may include: a gate insulating layer disposed on a gate electrode located on a substrate; a semiconductor layer, disposed on the gate insulating layer; and a planarization layer disposed on the gate insulating layer, the source and drain electrodes, and the channel area, and having openings exposing parts of the first source and drain areas and the source and drain electrodes, respectively. The semiconductor layer may include: a channel area corresponding to the gate electrode; first source and drain areas doped with an impurity outside the channel area; second source and drain areas, including a metal, outside the first source and drain areas; and source and drain electrodes disposed on the second source and drain areas and exposing the first source and drain areas. A pixel electrode may be disposed in one of the openings.

Abstract: A magnetic random access memory includes a bit line running in a first direction, a first word line running in a second direction different from the first direction, and a memory element having a magnetoresistive effect element including a fixed layer having a fixed magnetization direction, a recording layer having a reversible magnetization direction, and a nonmagnetic layer formed between the fixed layer and the recording layer, the magnetization directions in the fixed layer and the recording layer being perpendicular to a film surface, and a heater layer in contact with the magnetoresistive effect element, the memory element being connected to the bit line, and formed to oppose a side surface of the first word line such that the memory element is insulated from the first word line.

Abstract: A method for determining whether a quantum system comprising a superconducting qubit is occupying a first basis state or a second basis state once a measurement is performed is provided. The method, comprising: applying a signal having a frequency through a transmission line coupled to the superconducting qubit characterized by two distinct, separate, and stable states of differing resonance frequencies each corresponding to the occupation of the first or second basis state prior to measurement; and measuring at least one of an output power or phase at an output port of the transmission line, wherein the measured output power or phase is indicative of whether the superconducting qubit is occupying the first basis state or the second basis state.

Abstract: A system is provided. The system includes a device that includes top and bottom thermally conductive substrates positioned opposite to one another, wherein a top surface of the bottom thermally conductive substrate is substantially atomically flat and a thermal blocking layer disposed between the top and bottom thermally conductive substrates. The device also includes top and bottom electrodes separated from one another between the top and bottom thermally conductive substrates to define a tunneling path, wherein the top electrode is disposed on the thermal blocking layer and the bottom electrode is disposed on the bottom thermally conductive substrate.

Abstract: A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract: In a photoelectric conversion device, in a contact between a p-type semiconductor 3a and an electrode 2, an n-type semiconductor 6 of a conductivity type opposite to that of the p-type semiconductor is provided between the p-type semiconductor 3a and the electrode 2. The existence of the n-type semiconductor 6 allows a recombination rate of photo-generated carriers excited by incident light to be effectively reduced, and allows a dark current component to be effectively prevented from being produced. Therefore, it is possible to improve photoelectric conversion efficiency as well as to stabilize characteristics. Further, a tunnel junction is realized by increasing the concentration of a doping element in at least one or preferably both of the p-type semiconductor 3a and the n-type semiconductor 6 in a region where they are in contact with each other, thereby keeping ohmic characteristics between the semiconductor and the electrode good.

Abstract: A qubit implementation based on exciton condensation in capacitively coupled Josephson junction chains is disclosed. The qubit may be protected in the sense that unwanted terms in its effective Hamiltonian may be exponentially suppressed as the chain length increases. Also disclosed is an implementation of a universal set of quantum gates, most of which offer exponential error suppression.

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract: A logic circuit that can reconfigure its functions in a nonvolatile manner and a single-electron transistor to be used in the logic circuits are provided. The logic circuit has a single-electron spin transistor that includes: a source; a drain; an island that is provided between the source and the drain, and has tunnel junctions between the island and the source and drain; and a gate that is capacitively coupled to the island. In this logic circuit, at least one of the source, the drain, and the island includes a ferromagnetic material having a variable magnetization direction.

Abstract: The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility.

Abstract: An implementation of a single qubit phase gate for use in a quantum information processing scheme based on the ?=5/2 fractional quantum Hall (FQH) state is disclosed. Using sack geometry, a qubit consisting of two ?-quasiparticles. which may be isolated on respective antidots, may be separated by a constriction from the bulk of a two-dimensional electron gas in the ?=5/2 FQH state. An edge quasiparticle may induce a phase gate on the qubit. The number of quasiparticles that are allowed to traverse the edge path defines which gate is induced. For example, if a certain number of quasiparticles are allowed to traverse the path, then a ?/8 gate may be effected.

Abstract: Coulomb blockade in metal nanoparticles isolated by a tunneling barrier is considered to be a potential solution to low power, robust, high-speed electronic switching device operating at single-electron transport. However, the switching voltage equal to the threshold voltage to overcome coulomb blockade for these devices is typically in the 10 mV range and/or operating at currents well below 1 nA, which inhibits their application as a practical device. Theoretically, a one dimensional nanoparticle necklace is predicted to be an ideal structure to achieve higher switching voltages. The present invention provides a single-electron device composed of a necklace of about 5000 nanoparticles. The linear necklace is self-assembled by interfacial phenomena along a triple-phase line of fiber, a substrate and electrolyte containing nanoparticles. The I-V measurements on the system show both coulomb blockade and staircase, with high currents and high threshold voltage of 1-3 V.

Abstract: An array substrate for a liquid crystal display device includes a substrate having a display area and a driving circuit area, a first semiconductor layer formed on the substrate in the display area, the first semiconductor layer having an active region and source and drain regions at opposing sides of the active region, a gate insulating layer formed on the first semiconductor layer, a gate electrode formed on the gate insulating layer and over the active region, the gate electrode being wider than the gate insulating layer, and an interlayer insulating layer formed over the substrate including the gate electrode, wherein the interlayer insulating layer, the gate electrode, the gate insulating layer, and the active region define a first cavity.

Abstract: A semiconductor photodetector for photon detection without the use of avalanche multiplication, and capable of operating at low bias voltage and without excess noise. In one embodiment, the photodetector comprises a plurality of InP/AlInGaAs/AlGaAsSb layers, capable of spatially separating the electron and the hole of an photo-generated electron-hole pair in one layer, transporting one of the electron and the hole of the photo-generated electron-hole pair into another layer, focalizing it into a desired volume and trapping it therein, the desired volume having a dimension in a scale of nanometers to reduce its capacitance and increase the change of potential for a trapped carrier, and a nano-injector, capable of injecting carriers into the plurality of InP/AlInGaAs/AlGaAsSb layers, where the carrier transit time in the nano-injector is much shorter than the carrier recombination time therein, thereby causing a very large carrier recycling effect.

Abstract: A resistance-change memory device is provided and includes a stack constituting a tunnel magnetoresistance effect element that has a magnetic layer in which a direction of magnetization is switchable and that is formed on a conductive layer, and the stack is included in a resistance-change memory cell performing data writing utilizing a spin transfer effect caused by current injection. The stack is formed such that a line connecting centers of respective layers of the stack is tilted with respect to a direction perpendicular to a surface of the conductive layer having the stack formed thereon.

Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select device may comprise, for example, a metal-insulator-insulator-metal (MIIM) device. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.

Abstract: A voltage supply is connected to provide a variable bias voltage to a plurality of optical quantum tunneling photodetectors to thereby vary the spectral response of the photodetectors and thus detect radiation.

Abstract: A thermo-electric semiconductor device is provided. The thermo-electric semiconductor device includes: a first electrode layer; a spacer layer formed on the first electrode layer and having a plurality of pillars with a uniform height, the plurality of pillars thermally grown and protruded on a surface of the spacer layer; and a second electrode layer formed over the spacer layer in such a manner as to contact tops of the protruded pillars.

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract: A device in one embodiment includes a plurality of tunnel junction resistors coupled in series; a first lead coupled to one end of the plurality of tunnel junction resistors coupled in series; and a second lead coupled to another end of the plurality of tunnel junction resistors coupled in series. A device in another embodiment includes a magnetoresistive sensor; a plurality of tunnel junction resistors coupled in series; a first lead coupling one end of the magnetoresistive sensor to one end of the plurality of tunnel junction resistors coupled in series; and a second lead coupling another end of the magnetoresistive sensor to another end of the plurality of tunnel junction resistors coupled in series.

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

Abstract: A structure comprising (i) a first information device, (ii) a second information device, (iii) a first coupling element and (iv) a second coupling element is provided. The first information device has at least a first lobe and a second lobe that are in electrical communication with each other. The second information device and has at least a first lobe and a second lobe that are in electrical communication with each other. The first coupling element inductively couples the first lobe of the first information device to the first lobe of the second information device. The second coupling element inductively couples the first lobe of the first information device to the second lobe of the second information device.

Abstract: An electron tunneling device includes a first non-insulating strip and a second non-insulating strip spaced apart from one another such that first and second end portions, respectively, of the first and second non-insulating strips cooperate to form an antenna having an antenna impedance. The first and second non-insulating strips include a transition region that extends from the antenna to a tunneling region in which the first and second non-insulating strips are in a confronting relationship. An arrangement cooperates with a portion of each of the first and second non-insulating strips in the tunneling region to form an electron tunneling structure exhibiting a tunneling region impedance. The transition region is configured to match the antenna impedance to the tunneling region impedance. The transition region can provide for changing an electromagnetic field orientation between the antenna and the tunneling region.

Abstract: A detector includes a voltage source for providing a bias voltage and first and second non-insulating layers, which are spaced apart such that the bias voltage can be applied therebetween and form an antenna for receiving electromagnetic radiation and directing it to a specific location within the detector. The detector also includes an arrangement serving as a transport of electrons, including tunneling, between and to the first and second non-insulating layers when electromagnetic radiation is received at the antenna. The arrangement includes a first insulating layer and a second layer configured such that using only the first insulating in the arrangement would result in a given value of nonlinearity in the transport of electrons while the inclusion of the second layer increases the nonlinearity above the given value. A portion of the electromagnetic radiation incident on the antenna is converted to an electrical signal at an output.

Abstract: The nanostructure-based electronic device comprises a solid support, an organic template layer, a nanostructure and electrodes. The organic template layer is on the surface of the solid support, and has a surface comprising a pair of spaced, electrically-charged regions arranged in tandem in an electrically-neutral background. The nanostructure is elongate, is electrically-conducting, and extends between the charged regions. The electrodes are located the surface of the template layer and are at least co-extensive with the charged regions.

Abstract: A photoelectric conversion device including a photoelectric conversion part including a pair of electrodes and a photoelectric conversion layer provided between the pair of electrodes, wherein the photoelectric conversion part further includes a first charge blocking layer for reducing an injection of a charge into the photoelectric conversion layer from one of the pair of electrodes when a voltage is applied between the pair of electrodes, the first charge blocking layer being provided between the one of the pair of electrodes and the photoelectric conversion layer; and the first charge blocking layer has a relative dielectric constant larger than a relative dielectric constant of the photoelectric conversion layer.

Abstract: In a photoelectric conversion device, in a contact between a p-type semiconductor 3a and an electrode 2, an n-type semiconductor 6 of a conductivity type opposite to that of the p-type semiconductor is provided between the p-type semiconductor 3a and the electrode 2. The existence of the n-type semiconductor 6 allows a recombination rate of photo-generated carriers excited by incident light to be effectively reduced, and allows a dark current component to be effectively prevented from being produced. Therefore, it is possible to improve photoelectric conversion efficiency as well as to stabilize characteristics. Further, a tunnel junction is realized by increasing the concentration of a doping element in at least one or preferably both of the p-type semiconductor 3a and the n-type semiconductor 6 in a region where they are in contact with each other, thereby keeping ohmic characteristics between the semiconductor and the electrode good.

Abstract: A nonvolatile memory cell includes a gate controlled diode steering element and a resistivity switching element.

Abstract: Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode.

Abstract: A memory using a tunnel barrier is disclosed. A memory element includes a tunneling barrier and two conductive materials. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is irreversibly formed for one time programmable memory. The tunneling barrier can be formed by mobile ions combining with complementary ions. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity, multiple states can be created in the memory cell.

Abstract: A tunnel barrier in proximity with a layer of a rare earth element-transition metal (RE-TM) alloy forms a device that passes negatively spin-polarized current. The rare earth element includes at least one element selected from the group consisting of Gd, Tb, Dy, Ho, Er, Tm, and Yb. The RE and TM have respective sub-network moments such that the absolute magnitude of the RE sub-network moment is greater than the absolute magnitude of the TM sub-network moment. An additional layer of magnetic material may be used in combination with the tunnel barrier and the RE-TM alloy layer to form a magnetic tunnel junction. Still other layers of tunnel barrier and magnetic material may be used in combination with the foregoing to form a flux-closed double tunnel junction device.

Abstract: More sensitive (especially due to reduced interference of flux noise) than a conventional SQUID, an inventive SQUID's major component is a hollow cylindric structure comprising one or more annular Josephson junctions. Each annular Josephson junction is defined by two superconductive annuli and an interposed non-superconductive annulus. Inventive practice is variable, e.g., in terms of number and/or spacing of Josephson junctions, and/or as having one or more shunts connecting two or more Josephson junctions, and/or as having one or more vortices each threaded through a Josephson junction. The inventive cylindric structure is positioned proximate a magnetic field of interest so that the latter is aligned with the longitudinal axis of the former.

Abstract: A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyimide passivation and planarization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substrate 100 that serves as a foundation for bottom contact layers 102 and a polyimide 700 coating. An ohmic metal contact 300 and emitter metal contact 400 protrude above the polyimide 700 coating exposing the ohmic metal contact 300 and emitter metal contact 400. The contacts are capped with an etch-resistant coating 710 thus allowing for the polyimide etch, and other etching processes without adversely affecting the contacts.

Abstract: This invention concerns quantum computers in which the qubits are closed systems, in that the particle or particles are confined within the structure. A “site” can be produced by any method of confining an electron or other quantum particle, such as a dopant atom, a quantum dot, a cooper pair box, or any combination of these. In particular the invention concerns a closed three-site quantum particle system. The state in the third site is weakly coupled by coherent tunneling to the first and second states, so that the third state is able to map out the populations of the first and second states as its energy is scanned with respect to the first and second states. In second and third aspects it concerns a readout method for a closed three-state quantum particle system.

Abstract: A switching element comprising: an insulative substrate; a first electrode and a second electrode provided on one surface of the insulative substrate; and an interelectrode gap which is provided between the first electrode and the second electrode, and which has a gap on the order of nanometers in which switching phenomenon of resistance occurs by applying predetermined voltage between the first electrode and the second electrode, wherein the one surface of the insulative substrate contains nitrogen.

Abstract: An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 ?-?m2 or even less than or equal to 1 ?-?m2 for the electrical device.

Abstract: A transistor has an emitter, a spin-selective base, a collector, a first barrier interposed between the spin-selective base and the emitter, a second barrier interposed between the spin-selective base and the collector, and a transfer ratio of more than 10?3.

Abstract: A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line electrode in contact with the upper electrode element; and a dielectric fill layer surrounding the phase change element and the upper electrode element, spaced from the same and sealed by the bit line electrode to define a vacuum jacket around the phase change element and upper electrode element.

Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.

Abstract: Methods of forming ferromagnetic floating gate structures are described. The methods include atomic layer deposition of multiple precursor films, followed by alloying the metals in the precursor films, to form a ferromagnetic floating gate. Devices that include ferromagnetic floating gates formed with these methods are also described.