Abstract: The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: A magnetic memory cell includes first and second magneto-resistive devices connected in series. The first and second magneto-resistive devices have sense layers with different coercivities. Magnetic Random Access Memory (MRAM) devices may include arrays of these memory cells.

Abstract: The present invention provides a single-electron transistor device (100). The device (100) comprises a source (105) and drain (100) located over a substrate (115) and a quantum island (120) situated between the source and drain (105, 110), to form tunnel junctions (125, 130) between the source and drain (105, 110). The device (100) further includes a movable electrode (135) located adjacent the quantum island (120) and a displaceable dielectric (140) located between the moveable electrode (135) and the quantum island (120). The present invention also includes a method of fabricating a single-electron device (200), and a transistor circuit (300) that include a single-electron device (310).

Abstract: The present invention discloses an array substrate for an active-matrix LCD device and a method of fabricating the same. The array substrate reduces the number of masks used in the fabrication process so that reliability is enhanced and the cost is reduced over the conventional device and method.

Abstract: A logic apparatus comprises a first single-electron device formed of a first conductive island, two first tunnel barriers with the first conductive island interposed, first and second electrodes, and a first charge storage region, and a second single-electron device formed of a second conductive island, second tunnel barriers with the second island interposed, third and fourth electrodes, and a second charge storage region, the first electrode of the first single-electron device being connected to the third electrode of the second single-electron device being connected to each other.

Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 &OHgr;-&mgr;m2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface.

Abstract: This invention relates to a Coulomb blockade transistor comprising the following on a substrate:

Abstract: A non-volatile memory cell incorporated in an integrated circuit is disclosed. The non-volatile memory cell comprises an access transistor; a floating gate transistor coupled to the access transistor; a tunneling capacitor formed between the source of the access transistor and the gate of the second transistor; and a coupling capacitor having a first plate associated with a gate of the floating gate transistor, the first plate being formed to minimize the gate to source capacitance of the floating gate transistor. A window is also created to reduce the capacitance of the tunneling capacitor and the gate to source capacitance of the floating gate transistor. A method of manufacturing this non-volatile memory cell is also disclosed.

Abstract: The present invention relates to a configuration of a display element and forms switching circuits or peripheral circuits for driving pixels by transferring/disposing a semiconductor circuit formed on another substrate and disposes high performance transistors on the display substrate. The present invention also relates to a process of forming a circuit having switching elements for driving pixels and peripheral circuits for sending drive signals thereto on the substrate of the display element. A separation layer is formed on a second substrate and a semiconductor film is formed thereon. This semiconductor film having predetermined semiconductor circuits formed therein is bonded to the substrate of the display element and then electrical connection with a wire on the substrate is effected.

Abstract: A gated nanoscale switch operates as a resonant tunneling device. A conductive channel is formed of a pair of conductive molecular wires and a conductive nanoparticle. Each molecular wire is bound, at one end, to the conductive nanoparticle and, at the opposed end, to one of a pair of electrodes. The structure is located upon a dielectric layer that overlies a conductive substrate. The device may be arranged to operate as a switch with the conductive substrate acting as a gate electrode. Alternatively, the device may be employed to measure the electrical (current versus voltage) characteristics of the molecular wires.

Abstract: The invention involves tunneling tips to their conducting surface, and specifically the deposition of a monolayer of fullerene C60 onto the conducting plate surface to protect the tunneling tip from contact. The Fullerene C60 molecule is approximately spherical, and a monolayer of fullerene has a thickness of one nanometer, such that a monolayer thereby establishing the theoretical distance desired between the MEMS' tunneling tip and the conducting plate. Exploiting the electrical conductivity of C60, the tip can be accurately positioned by simply monitoring conductivity between the fullerene and the tunneling tip. By monitoring the conductivity between the tip and the fullerene layer as the tip is brought in proximity, the surfaces can be brought together without risk of contacting the underlying conducting surface.

Abstract: A logic apparatus having first and second single-electron devices connected serially or in parallel. Each of the single-electron devices includes a conductive island insulatively disposed between two tunnel barriers, which separate the conductive island from respective source/drain electrodes. A first charge storage region is insulatively disposed over and under the conductive island and a gate electrode, respectively. When charges are accumulated in the charge storage region, a Coulomb oscillation of the respective device is shifted by a half-period from the Coulomb oscillation that results when no charge has accumulated therein.

Abstract: A method for forming a uniform layered structure comprising an ultra-thin layer of amorphous silicon and its thermal oxide is disclosed. In one aspect, a method for forming a nanolaminate of silicon oxide on a substrate is disclosed. In another aspect, a method for forming a patterned hard mask on a substrate is disclosed. The patterned hard mask includes a nanolaminate of silicon and silicon oxide. The methods are characterized by the oxidation of an amorphous silicon layer using atomic oxygen.

Abstract: The quantum circuit device comprises: an asymmetrical coupled quantum dot of a main quantum dot 3a and an operational quantum dot 3b of a smaller size than the main quantum dot 3c; an asymmetrical coupled quantum dot of a main quantum dot 3c arranged at a distance which does not permit to substantially tunnel from the main quantum dot 3a, and an operation quantum dot 3d having a smaller size than the main quantum dot 3c and arranged at a distance which permits tunneling from the operational quantum dot 3b; and a laser device for applying to the asymmetrical coupled quantum dots a laser beam of a wavelength which resonates an inter-level energy the asymmetrical coupled quantum dots. In the sleep state, electron is present at the ground state of the main quantum dot, where no exchange interaction takes place, and in an operation, the electron is transited to an excited state of the operational quantum dot, whereby the operation is made by the exchange interactions between the adjacent operational quantum dots.

Abstract: A metal-oxide-silicon (MOS) device that at least includes a silicon-based substrate, a nanometer scaled oxide layer formed on the silicon-based substrate and a metal layer formed on the oxide layer, is disclosed. The present invention basically uses a nanometer scaled oxide structure that result in a non-uniform tunneling current to enhance light-emitting efficiency. The manufacturing steps of the MOS device according to the present invention are quite similar to those of conventional MOS device, so the MOS device according to the present invention can be integrated with the current silicon-based integrated circuit chip. Further the application fields of the silicon-based chip and material can be extended. The cost of MOS device can be reduced and its practicality can be increased.

Abstract: A self-organized nanometer interface structure is disclosed. During the reactive sputtering process, the chemical dynamics difference among reactants induces self-organization to form a special nanometer interface structure. The nanometer interface structure naturally form an interface potential difference so that it has a rectifying effect in a particular range of potential variation range. Therefore, it functions like a diode. Such a self-organized nanometer interface structure can be used in the manufacturing of diodes, transistors, light-emitting devices, and sonic devices. The invention has the advantages of a wide variety of material selections, highly compatible processes, easy operations, and low-cost fabrications.

Abstract: A single electron tunnelling device is formed by positioning between first and second electrodes a particle formed of a material having a first conductivity characteristic having a surface layer of a material of a second conductivity characteristic, the thickness of said layer being sufficiently small to support quantum mechanical tunnelling therethrough.

Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.

Abstract: The present invention provides a quantum structure product comprising a substrate having quantum ridges and quantum tips on at least one surface thereof. In some embodiments of the invention quantum ridges may support quantum wires and the quantum tips may support quantum dots. Grooves which separate the quantum ridges and quantum tips from each other may be shallow or deep, and may contain organic molecules, fullerene tubes, and fullerene balls.

Abstract: A wavelength-tunable light emitting device includes a substrate having an atomic-scale structure formed on a surface thereof, a needle member for locally applying a voltage through a vacuum space or a transparent insulating member to the substrate to cause a tunnel current to flow through the atomic-scale structure, and a variable-voltage power supply capable of varying voltage applied across the gap between the substrate and the needle member. The gap between the first member and the second member is as close as a few nm in length. A tunnel current flows from the tip of the needle member to the atomic-scale structure when a predetermined voltage is applied across the gap between the substrate and the needle member; and light is emitted from a tunneling region in which the tunnel current flows, because of an optical transition between respective localized states of the substrate and the needle.

Abstract: An electronic device has a plurality of electrically conductive first nanowires, a layer system applied on the first nanowires, and also second nanowires applied on the layer system. The first and second nanowires are arranged skew with respect to one another. The layer system is set up in such a way that charge carriers generated by the nanowires can be stored in the layer system.

Abstract: Provided are a Schottky barrier tunnel transistor (SBTT) and a method of fabricating the same. The SBTT includes a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove. In the SBTT, the SOI layer is formed to an ultra-thin thickness to minimize the occurrence of a leakage current, and a channel in the SOI layer below the gate is completely wrapped by the gate and the conductive layer, thereby improving the operational characteristics of the SBTT.

Abstract: An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 &OHgr;-&mgr;m2 or even less than or equal to 1 &OHgr;-&mgr;m2 for the electrical device.

Abstract: The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: Provided are a Schottky barrier tunnel transistor (SBTT) and a method of fabricating the same. The SBTT includes a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove. In the SBTT, the SOI layer is formed to an ultra-thin thickness to minimize the occurrence of a leakage current, and a channel in the SOI layer below the gate is completely wrapped by the gate and the conductive layer, thereby improving the operational characteristics of the SBTT.

Abstract: An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped region forming a channel of different conductivity type than the first region is positioned over the first region. A fourth doped region of a different conductivity and forming a channel is positioned over the second region. The process of creating the gate structure for each of the two transistors allows for the formation of oxide layers of different thickness between the two transistors. The transistors are therefore capable of operating at different operating voltages (including different threshold voltages). Each transistor further includes fifth and sixth layers positioned respectively over the third and fourth regions and having an opposite conductivity type with respect to the third and fourth regions.

Abstract: A negative differential resistance device is provided that includes a first barrier, a second barrier and a third barrier. A first quantum well is formed between the first and second barriers. A second quantum well is formed between the second and third barriers.

Abstract: The present invention provides a quantum structure product comprising a substrate having quantum ridges and quantum tips on at least one surface thereof. In some embodiments of the invention quantum ridges may support quantum wires and the quantum tips may support quantum dots. Grooves which separate the quantum ridges and quantum tips from each other may be shallow or deep, and may contain organic molecules, fullerene tubes, and fullerene balls.

Abstract: A micro electron gun that is capable of extracting electrons from a semiconductor utilizing a quantum size effect and that can be mounted individually for each of pixels is disclosed, as well as a picture display apparatus using such electron guns which is high in quantum efficiency, of high brightness and thin, as well as methods of manufacture thereof. Conduction electrons from a n-type semiconductor substrate (2) are accelerated under an electric field through a layer or layers (4) of quantum size effect micro particles (3) formed on surfaces of the n-type semiconductor substrate (2) and passed therethrough without undergoing phonon scattering, so that they when arriving at an electrode (5) may possess an amount of energy not less than the work function of the electrode (5) and are thus allowed to spring out into a vacuum.

Abstract: A single-electron transistor includes a projecting feature, such as a pyramid, that projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode. At least one nanoparticle is provided on the projecting feature between the first and second electrodes. Accordingly, the geometric configuration of the projecting feature can define the spacing between the first and second electrodes.

Abstract: A quantum device is constituted from a two-dimensional array of quantum dots formed from metal atom aggregates contained in a metalloprotein complex. The metalloprotein is arranged on the surface of a substrate having an insulation layer with a pitch of the size of the metalloprotein complex. The diameter of the metal atom aggregates used in the quantum device is 7 nm or smaller, and the pitch of the metalloprotein complex is preferably from 11 to 14 nm.

Abstract: A switch device includes a source, a drain, and a gate electrode which are conductive, one or more semiconductor island layer(s) formed between the source and drain, an insulating film between the source and island layer, an insulating film between the drain and island layer, an insulating layer between island layers if a plurality of island layers are provided, and a gate capacitor formed by the gate electrode, at least one island layer, and a gate insulating film provided between the gate electrode and the island layer. The electric field applied to the gate capacitor is set to be substantially parallel with a channel current flowing via the island between the source and the drain.

Abstract: This invention pertains to a device and a method for injecting spin polarized monochromatic electrons with a particular magnetic moment at room temperature and in absence of an external magnetic field into a nonmagnetic electrode. The device comprises a ferromagnetic electrode, a nonmagnetic electrode spaced from the ferromagnetic electrode, a nanocrystal doped with a single active paramagnetic ion disposed in the space between the electrodes, and an electrical connection between the electrodes for applying voltage to move the electrons from the ferromagnetic electrode, through the doped nanocrstal and into the nonmagnetic electrode.

Abstract: A superconductor integrated circuit (10) includes a silicon substrate (12) a niobium ground layer (14), an anodized niobium first ground insulator layer (16), a second ground insulator layer (22), a molybdenum nitrogen (MoNx) resistor (18) provided between the first and second ground insulator layers (16, 22), a Josephson junction (23) provided above the first and second ground insulator layers (16, 22), first and second oxide insulators (27, 30), and a niobium interconnect (28) for providing electrical communication with the Josephson junction. The MoNx first resistor (18) provides a sheet resistance of between 3-5 ohms/sq at 4° K with a thickness of approximately 95 nm and enables the superconductor integrated circuit (10) to have a critical current density between 6-8 kA/cm2.

Abstract: A metal-oxide-silicon (MOS) device that at least includes a silicon-based substrate, a nanometer scaled oxide layer formed on the silicon-based substrate and a metal layer formed on the oxide layer, is disclosed. The present invention basically uses a nanometer scaled oxide structure that result in a non-uniform tunneling current to enhance light-emitting efficiency. The manufacturing steps of the MOS device according to the present invention are quite similar to those of conventional MOS device, so the MOS device according to the present invention can be integrated with the current silicon-based integrated circuit chip. Further the application fields of the silicon-based chip and material can be extended. The cost of MOS device can be reduced and its practicality can be increased.

Abstract: A superconducting qubit is presented. The qubit is a shaped long Josephson junction with a magnetic fluxon such that, in the presence of an externally applied magnetic field, a fluxon potential energy function indicating a plurality of pinning sites in the qubit is produced. In one embodiment, a heart-shaped Josephson junction is formed where a trapped fluxon has a double-welled potential energy function, indicating two pinning sites, when the junction is placed in an externally applied magnetic field. The qubit is manipulated by preparing an initial state, creating a superposition of the two states by decreasing the magnetic field, evolving of the quantum state with time, freezing in a final state by increasing the magnetic field, and reading out the final state. In other embodiments, qubit exhibiting potential energy functions having any number of pinning sites can be realized.

Abstract: The first phonon-pumped semiconductor laser. The active region is an unbiased boron-doped Si0.94Ge0.06/Si superlattice with Si0.97Ge0.03 buffer layers embedded in a surface-plasmon strip waveguide. Warm and cool heat sinks create a temperature gradient across the waveguide. A heat buffer layer adjacent to the cool sink reflects optical phonons and transmits acoustic phonons. Within the resonator, the difference in effective temperatures of optical and acoustic phonons provides hole pumping for the lasing transition between the heavy-hole 2 (HH2) and heavy-hole 1(HH1) minibands. A gain of 280/cm at the 5THz emission frequency is predicted for 6×1017/cm3 doping at temperatures of 300K and 77K for optical and acoustic phonons, respectively.

Abstract: A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode.

Abstract: An organic electroluminescent device having a luminescent layer interposed between an anode and a cathode, on a substrate, wherein a layer containing an electron-accepting compound containing a boron atom represented by the following formula (I): wherein each of Ar1 to Ar3 which are independent of one another, is an aromatic hydrocarbocyclic group or aromatic heterocyclic group which may have a substituent, and a hole transport compound, is formed between the luminescent layer and the anode.

Abstract: A liquid crystal display apparatus is provided which is capable of realizing a uniform display even at a high definition and offering a widened operating temperature. A signal line is formed on a signal line through an intervening insulating layer in an active-matrix type liquid crystal display apparatus of MIM drive type. MIM devices as two-terminal nonlinear devices are formed between each pixel electrode and the signal lines. The MIM devices are formed to operate in different operating temperature ranges. By selecting one of the signal lines to be supplied with a driving signal to achieve switching between the MIM devices, the pixel electrode associated therewith can operate within a wider operating temperature range. The respective resistances of the signal lines and/or MIM devices associated with each pixel electrode are adjusted so as to be equalized throughout all the pixel electrodes, thereby lessening a non-uniform display to ensure a uniform display.

Abstract: A single electron device. Fabricated from nanoparticle derivatives, particularly from Au and fullerene nanoparticle derivatives, the device reduces thermal fluctuation in the nanoparticle array and has 15 nm of spacing between two electrodes.

Abstract: In accordance with embodiments of the present invention, a junction of an unconventional superconductor, an intermediate material, and a conventional superconducting material is presented. In some embodiments, the resulting junction is in the c-axis direction of the orthorhombic unconventional superconductor. Alternatively, the junction is in the a-b plane direction. Interface junctions according to embodiments of the present invention may be used in super low inductance qubits (SLIQs) and in permanent readout superconducting qubits (PRSQs), can form the basis of quantum registers, and can allow for parity keys or other devices made from conventional superconducting material to be attached to qubits made from unconventional superconducting material or vice versa. Coherent tunnel junctions according to embodiments of the present invention may be used to form parity keys or coherently couple two regions of a superconducting material.

Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.

Abstract: A tunneling junction transistor (TJT) device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The TJT device includes a gate defining a channel interposed between a source and a drain formed within one of the active regions of the SOI substrate. At least one thin nitride layer is interposed between a portion of the channel and at least one of the source and the drain.

Abstract: Both a non-volatile memory (NVM) and a dynamic nanocrystal memory (DNM) are integrated on a semiconductor substrate. Control gates and control dielectrics with embedded nanocrystals or discrete storage elements are formed over differing thicknesses of tunnel dielectrics to form the two memories. Source and drain regions are formed within the semiconductor substrate adjacent to the tunnel dielectrics. Various methods can be used to form a thin tunnel oxide and a thick tunnel oxide by adding minimum processing steps.

Abstract: A cryogenic, high-resolution X-ray detector with high count rate capability has been invented. The new X-ray detector is based on superconducting tunnel junctions (STJs), and operates without thermal stabilization at or below 500 mK. The X-ray detector exhibits good resolution (˜5-20 eV FWHM) for soft X-rays in the keV region, and is capable of counting at count rates of more than 20,000 counts per second (cps). Simple, FET-based charge amplifiers, current amplifiers, or conventional spectroscopy shaping amplifiers can provide the electronic readout of this X-ray detector.

Abstract: Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in between. At the time of “the reading of data”, an electric potential is applied to the first control electrode. During “the reading of data”, a change in an electric potential between the conduction region and the storage region is prevented, and therefore, unintentional writing or erasing of information is prevented, so that written information can be accurately read out.

Abstract: A method of forming diffusion barrier stacks on a dielectric for a dual damascene metal chip-level interconnect, and a diffusion barrier stack produced thereby. Alternating layers of a metal and an electrically resistive diffusion barrier are deposited on a dielectric substrate, with different layers having different thicknesses appropriate to their functions in the device. In an example of the present invention, alternating layers of tantalum and tantalum nitride are deposited on a dielectric substrate.

Abstract: A method of manufacturing a semiconductor device is provided in which a tunnel dielectric layer and a gate layer are formed on a semiconductor wafer and a trench forming technique is used to define a floating gate structure. An insulator is deposited in the trench whereby the gate layer and the tunnel dielectric layer form a gate which is self-aligned to a tunnel dielectric.

Abstract: An MOS-type semiconductor device comprises two semiconductors separated by an insulator. The two semiconductors comprise monocrystal semiconductors, each having a crystallographic orientation with respect to the insulator (or other crystallographic/semiconductor property) different to the crystallographic orientation (or other respective property) of the other semiconductor. This arrangement of crystallographic orientations (and other crystallographic/semiconductor properties) can yield reduced unintended electron tunneling or current leakage through the insulator vis a vis a semiconductor device in which such an arrangement is not used. Methods for forming the MOS-type semiconductor devices of the invention are also provided.