For Protecting Against Gate Insulator Breakdown Patents (Class 257/356)
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Patent number: 7449751Abstract: A high voltage operating electrostatic discharge protection device is provided. The high voltage operating electrostatic discharge protection device includes: a first gate structure and a second gate structure disposed on a substrate of a first conductive type with a predetermined distance; a well of the first conductive type formed in a first region of the substrate such that the well contacts one bottom portion of the first gate structure; a source region of a second conductive type formed within in the well; a counter pocket source region of the first conductive type formed within the well encompassing the source region; and a drift region of the second conductive type contacting a bottom surface of the second gate structure and formed in a second region of the substrate such that the drift region contacts the other bottom portion of the first gate structure.Type: GrantFiled: September 7, 2005Date of Patent: November 11, 2008Assignee: Magnachip Semiconductor, Ltd.Inventor: Kil-Ho Kim
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Publication number: 20080258224Abstract: A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Inventor: Fwu-Iuan Hshieh
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Patent number: 7439590Abstract: A semiconductor device features connecting gate patterns of all transistors to a N+ or +P junction by the first connected wiring layer to prevent degradation of characteristics of the semiconductor device which results from plasma damages during a process. In order to connect a junction to a gate layer weak to plasma damages, the gate layer is connected to the N+ or P+ junction when a first wiring layer after a transistor is formed. As a result, when the gate layer is charged up by plasma damages, the gate layer is discharged by the junction or provided to receive (?) ions or electrons so that a gate oxide is not affected by plasma damages.Type: GrantFiled: July 3, 2006Date of Patent: October 21, 2008Assignee: Hynix Semiconductor Inc.Inventor: Dong Hoon Kim
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Patent number: 7439591Abstract: Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a temperature compensated logic circuit and other on-chip temperature sensor applications.Type: GrantFiled: October 5, 2004Date of Patent: October 21, 2008Assignee: Infineon Technologies AGInventor: Woo-Tag Kang
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Patent number: 7436041Abstract: An ESD protection circuit using a double-triggered silicon controller rectifier (SCR). The double-triggered silicon controller rectifier (SCR) includes N+ diffusion areas, P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.Type: GrantFiled: December 20, 2005Date of Patent: October 14, 2008Assignee: National Chiao Tung UniversityInventors: Ming-Dou Ker, Kuo-Chun Hsu
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Patent number: 7432556Abstract: At least a laminate of a gate insulating film 6 and a gate electrode 7 and an active region 13 are formed on a silicon substrate 1, and an underlying interlayer insulating film 10 is further formed. Then, a conductor 11a connected to the gate electrode 7, and a conductor 11b that is a dummy conductor and is connected to the active region 13 are formed simultaneously on the underlying interlayer insulating film 10. Thereafter, an interlayer insulating film 12 is formed on the underlying interlayer insulating film 10 by a plasma process. At this time, charging current from a plasma 14 is emitted through the conductor 11b, which is a dummy conductor.Type: GrantFiled: January 8, 2007Date of Patent: October 7, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Eriguchi, Susumu Matsumoto
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Patent number: 7429774Abstract: An NMOS device having protection against electrostatic discharge. The NMOS device includes a P-substrate, a P-epitaxial layer overlying the P-substrate, a P-well in the P-epitaxial layer, an N-well in the P-epitaxial layer and encompassing the P-well, an N-Buried Layer (NBL) underneath the P-well and bordering the N-well. The P-well is fully isolated by the N-well and the NBL. The NMOS device further includes a first isolation structure consisting of a gate-insulating layer connected with a field oxide layer, which is formed on the P-epitaxial layer. A gate overlies the first isolation structure. A second isolation structure laterally spaced apart from the first isolation structure is approximately situated on the N-well. An N+ source doping region, which functions as a source of the NMOS device, is disposed in the P-well. An N+ drain doping region, which functions as a drain of the NMOS device, is disposed in the N-well.Type: GrantFiled: February 22, 2005Date of Patent: September 30, 2008Assignee: United Microelectronics Corp.Inventors: Chih-Nan Cheng, Yii-Chian Lu, Fang-Mei Chao
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Patent number: 7420251Abstract: An exemplary ESD protection circuit includes first and second sets of transistors and an ESD discharge transistor. Each of the transistors includes a source electrode, a drain electrode, and a gate electrode. The drain electrodes and gate electrodes of each of the transistors are connected to each other, and the source electrodes of the transistors are respectively connected to the drain electrodes of the next adjacent transistors in both sets of the transistors. The gate electrode of the ESD transistor, the source electrodes of last transistors of the first and second sets of the transistors are connected to each other, the source electrode of the ESD transistor is connected to the drain electrode of a first transistor of the first set of the transistors, and the drain electrode of the ESD transistor is connected to the drain electrode of a first transistor of the second set of the transistors.Type: GrantFiled: September 29, 2006Date of Patent: September 2, 2008Assignee: Innolux Display Corp.Inventors: Chi-Ming Chen, Hung-Yu Chen
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Patent number: 7420252Abstract: A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.Type: GrantFiled: January 20, 2006Date of Patent: September 2, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Ming Wu, Jian-Hsing Lee, Yi-Chun Lin, Chi-Chih Chen
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Publication number: 20080203480Abstract: In an embodiment, an apparatus includes a source region, a gate region and a drain region supported by a substrate, and a drift region including a plurality of vertically extending n-wells and p-wells to couple the gate region and the drain region of a transistor, wherein the plurality of n-wells and p-wells are formed in alternating longitudinal rows to form a superjunction drift region longitudinally extending between the gate region and the drain region of the transistor.Type: ApplicationFiled: February 23, 2007Publication date: August 28, 2008Applicant: INFINEON TECHNOLOGIES AGInventors: Martin Stiftinger, Snezana Jenei, Wolfgang Werner, Uwe Hodel
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Patent number: 7417287Abstract: An electrostatic discharge (ESD) device has a parasitic SCR structure and a controllable trigger voltage. The controllable trigger voltage of the ESD device is achieved by modulating a distance between an edge of a lightly doped well and an edge of a heavily doped region located at two ends of the lightly doped well. Since the distance and the trigger voltage are linearly proportional, the trigger voltage can be set to a specific value from a minimum value to a maximum value.Type: GrantFiled: July 1, 2005Date of Patent: August 26, 2008Assignee: System General Corp.Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu G. Lin, Tuo-Hsin Chien
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Patent number: 7417303Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.Type: GrantFiled: September 15, 2006Date of Patent: August 26, 2008Assignee: Broadcom CorporationInventors: Agnes N. Woo, Kenneth R. Kindsfater, Fang Lu
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Patent number: 7402868Abstract: A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device.Type: GrantFiled: November 1, 2004Date of Patent: July 22, 2008Assignee: Spansion L.L.C.Inventors: Ihsan Jahed Djomehri, Mark Randolph, Yi He, Wei Zheng
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Patent number: 7402846Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.Type: GrantFiled: October 20, 2005Date of Patent: July 22, 2008Assignee: Atmel CorporationInventors: Stefan Schwantes, Michael Graf, Volker Dudek, Gayle W. Miller, Jr., Irwin Rathbun, Peter Grombach, Manfred Klaussner
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Publication number: 20080164527Abstract: The semiconductor comprises a channel layer including GaN, a barrier layer formed by laminating a first layer including AlXGa1-XN (0.05?X?0.25) and a second layer including AlYGa1-YN (0.20?Y?0.28, X<Y), source and drain electrodes provided spaced apart from each other on the barrier layer, and a gate electrode provided on the bottom of a ditch extending between the source and drain electrodes and formed with a depth starting from the top surface of the barrier layer reaching the first layer adjacent to the channel layer.Type: ApplicationFiled: December 13, 2007Publication date: July 10, 2008Inventors: Takashi Kataoka, Atsuko Yamashita, Yoshiharu Kouji
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Publication number: 20080157203Abstract: A semiconductor device having an EDMOS transistor and a method for forming the same are provided. The semiconductor device includes source and drain regions formed separately in a semiconductor substrate, a first gate insulating layer filling a trench formed in the substrate between the source and drain regions, the first gate insulating layer being adjacent to the drain region and separated from the source region, a second gate insulating layer formed over the substrate between the first gate insulating layer and the source region, the second gate insulating layer being thinner than the first gate insulating layer, a gate electrode formed over the first and second gate insulating layers, and a doped drift region formed in the substrate under the first gate insulating layer, the doped drift region being in contact with the drain region. This reduces the planar area of the EDMOS transistor, thereby achieving highly integrated semiconductor devices.Type: ApplicationFiled: December 12, 2007Publication date: July 3, 2008Inventor: Hyun-Soo Shin
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Patent number: 7391069Abstract: In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the present invention, for example, a MOS transistor, a P type diffusion layer 5 as the back gate region, and an N type diffusion layer 8 as a drain region, are formed in an N type epitaxial layer 4. In the P type diffusion layer 5, an N type diffusion layer 7 as a source region and a P type diffusion layer 6 are formed. The P type diffusion layer 6 is formed by performing ion implantation twice so as to correspond to a shape of a contact hole 15. Moreover, impurity concentrations in surface and deep portions of the P type diffusion layer 6 are controlled. By use of this structure, a device size is reduced, and an operation of a parasitic NPN transistor is suppressed.Type: GrantFiled: August 14, 2006Date of Patent: June 24, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Seiji Otake, Ryo Kanda, Shuichi Kikuchi
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Patent number: 7385253Abstract: Disclosed herein are a device for electrostatic protection and circuit thereof.Type: GrantFiled: February 4, 2005Date of Patent: June 10, 2008Assignee: Magnachip Semiconductor, Ltd.Inventor: Kil Ho Kim
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Publication number: 20080121995Abstract: A bi-directional power switch is formed as a monolithic semiconductor device. The power switch has two MOSFETs formed with separate source contacts to the external package and a common drain. The MOSFETs have first and second channel regions formed over a well region above a substrate. A first source is formed in the first channel. A first metal makes electrical contact to the first source. A first gate region is formed over the first channel. A second source region is formed in the second channel. A second metal makes electrical contact to the second source. A second gate region is formed over the second channel. A common drain region is disposed between the first and second gate regions. A local oxidation on silicon region and field implant are formed over the common drain region. The metal contacts are formed in the same plane as a single metal layer.Type: ApplicationFiled: July 3, 2007Publication date: May 29, 2008Applicant: GREAT WALL SEMICONDUCTOR CORPORATIONInventors: Samuel J. Anderson, David N. Okada
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Publication number: 20080111192Abstract: There is provided a high-voltage-withstanding semiconductor device a fabrication method thereof capable of suppressing Vt fluctuation induced by plasma damage in a via hole forming step. In the high-voltage-withstanding semiconductor device, a gate electrode of a transistor having a gate insulating film formed on a semiconductor substrate and having a thickness of 350 ? or more and a diode composed of a first conductive well region formed in a surface layer region of the semiconductor substrate and a second conductive diffusion layer formed in the surface layer region of the semiconductor substrate and on the well region are electrically connected by a wire directly connected to contacts formed respectively on the gate electrode and the diode, via the contacts.Type: ApplicationFiled: October 19, 2007Publication date: May 15, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Osamu Koike
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Patent number: 7361957Abstract: The present invention relates to a device for electrostatic discharge protection (ESD).Type: GrantFiled: June 23, 2006Date of Patent: April 22, 2008Assignee: Magnachip Semiconductor, Ltd.Inventors: Kil Ho Kim, Yong Icc Jung
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Publication number: 20080087962Abstract: Methods and devices are provided for protecting semiconductor devices against electrostatic discharge events. An electrostatic discharge protection device comprises a silicon substrate, a P+-type anode region disposed within the silicon substrate, and an N-well device region disposed within the silicon substrate in series with the P+-type anode region. A first P-well device region is disposed within the silicon substrate in series with the first N-well device region and an N+-type cathode region is disposed within the silicon substrate. A gate electrode is disposed at least substantially overlying the first N-well and P-well device regions of the silicon substrate.Type: ApplicationFiled: October 16, 2006Publication date: April 17, 2008Inventors: Akram Salman, Stephen Beebe
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Patent number: 7355250Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.Type: GrantFiled: September 8, 2005Date of Patent: April 8, 2008Assignee: System General Corp.Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu G. Lin, Tuo-Hsin Chien
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Patent number: 7352031Abstract: A compact electrostatic-breakdown-preventive and protective circuit for a semiconductor-device capable of performing high-speed operations includes first and second protective transistors. The distance from a contact hole for connecting an impurity diffusion layer serving as a source and a drain of each of the first and second protective transistors with a metallic wiring, to gates of the protective transistors, is made shorter than a corresponding distance in an output transistor or a protective transistor provided for an input terminal.Type: GrantFiled: April 7, 2003Date of Patent: April 1, 2008Assignee: Oki Electric Industry, Co., Ltd.Inventor: Katsuhiro Kato
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Patent number: 7342282Abstract: A semiconductor device and method for electrostatic discharge protection. The semiconductor device includes a first semiconductor controlled rectifier and a second semiconductor controlled rectifier. The first semiconductor controlled rectifier includes a first semiconductor region and a second semiconductor region, and the second semiconductor controlled rectifier includes the first semiconductor region and the second semiconductor region. The first semiconductor region is associated with a first doping type, and the second semiconductor region is associated with a second doping type different from the first doping type. The second semiconductor region is located directly on an insulating layer.Type: GrantFiled: September 10, 2004Date of Patent: March 11, 2008Assignee: Altera CorporationInventors: Hugh Sungki O, Chih-Ching Shih, Cheng-Hsiung Huang, Yow-Juang Liu
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Patent number: 7335954Abstract: An electrostatic discharge (ESD) protection device includes a first-type substrate, a second-type well formed in the substrate and a first-type well formed in the substrate. The second-type well includes a second-type+ region formed between first and second first-type+ regions. The first-type well is formed in the substrate adjacent a first side of the second-type well. The first-type well includes first and second first-type regions with a first-type+ region and a second-type+ region formed between the first and second first-type regions. The second-type+ region of the first-type well is formed between the first-type+ region of the first-type well and the second-type well.Type: GrantFiled: April 20, 2005Date of Patent: February 26, 2008Assignee: Delphi Technolgoies, Inc.Inventors: Jack L. Glenn, Pedro E. Castillo-Borelly
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Patent number: 7323753Abstract: To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is connected to the output of the NMOS, to shift the output of the NMOS for boosting. Then, a back gate of the NMOS is connected, via a PMOS in an on state, to the power source. With this structure, the PMOS provides a resistor component when the output terminal short-circuits.Type: GrantFiled: August 24, 2004Date of Patent: January 29, 2008Assignee: Sanyo Electric Co. Ltd.Inventors: Kazuo Henmi, Nobuyuki Otaka
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Patent number: 7317633Abstract: A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor and an NMOS transistor the PMOS transistors sharing a common deep N well and the NMOS transistors connected to a P well, wherein during negative charging, the NMOS transistors shunt leakage current to ground, and during positive charging, the PMOS transistors shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.Type: GrantFiled: July 5, 2005Date of Patent: January 8, 2008Assignee: Saifun Semiconductors LtdInventors: Eli Lusky, Ilan Bloom, Assaf Shappir, Boaz Eitan
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Patent number: 7298008Abstract: Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.Type: GrantFiled: January 20, 2006Date of Patent: November 20, 2007Assignee: International Business Machines CorporationInventors: Robert J. Gauthier, Jr., Junjun Li, Souvick Mitra, Mahmoud A. Mousa, Christopher Stephen Putnam
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Publication number: 20070262387Abstract: A power semiconductor module having an integral circuit board with a metal substrate electrode, an insulation substrate and a heat sink joined is disclosed. A SiC semiconductor power device is joined to a top of the metal substrate electrode of the circuit board. A difference in average coefficients of thermal expansion between constituent materials of the circuit board in a temperature range from room to joining time temperatures is 2.0 ppm/° C. or less, and a difference in expansion, produced by a difference between a lowest operating temperature and a joining temperature, of the circuit-board constituent materials is 2,000 ppm or less.Type: ApplicationFiled: May 10, 2007Publication date: November 15, 2007Inventors: Kenichi Nonaka, Takeshi Kato, Kenji Oogushi, Yoshihiko Higashidani, Yoshimitsu Saito, Kenji Okamoto
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Patent number: 7294892Abstract: A multi-transistor layout capable of saving area includes a substrate; a common drain comprising four sides formed over the substrate; four gates formed over the four sides of the common drain; and four sources formed over outer sides of the four gates corresponding to the common drain.Type: GrantFiled: May 27, 2005Date of Patent: November 13, 2007Assignee: Faraday Technology Corp.Inventor: Hsin-Hung Chen
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Patent number: 7291883Abstract: In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across a wider region on an upper surface of the N-type buried diffusion layer so that a PN junction region for overvoltage protection is formed. A P-type diffusion layer is formed so as to be connected to the P-type diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. With this structure, the concentration of the breakdown current is prevented so that the semiconductor device can be protected from the overvoltage.Type: GrantFiled: February 22, 2006Date of Patent: November 6, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Ryo Kanda, Shuichi Kikuchi, Seiji Otake
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Patent number: 7285837Abstract: A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.Type: GrantFiled: January 17, 2005Date of Patent: October 23, 2007Assignee: System General Corp.Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-yu G. Lin, Ta-yung Yang
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Patent number: 7282768Abstract: A high-reliable depletion-type MOS field-effect transistor as a process monitor is provided. A diode formed in polycrystalline silicon and a diode formed in a semiconductor substrate form a bi-directional diode. The bi-directional diode connects a gate electrode with the semiconductor substrate in the depletion-type MOS field-effect transistor through metal wirings.Type: GrantFiled: July 1, 2005Date of Patent: October 16, 2007Assignee: Seiko Instruments Inc.Inventor: Hirofumi Harada
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Publication number: 20070221994Abstract: A driver circuit that lowers the dependence of the loss in the wide gap semiconductor device upon the temperature is provided. A gate driver circuit for voltage driven power semiconductor switching device includes a power semiconductor switching device, a driver circuit for supplying a drive signal to a gate terminal of the switching device with reference to an emitter control terminal or a source control terminal of the switching device, and a unit for detecting a temperature of the switching device. The temperature of the power semiconductor switching device is detected, and a gate drive voltage or a gate drive resistance value is changed based on the detected temperature.Type: ApplicationFiled: January 25, 2007Publication date: September 27, 2007Inventors: Katsumi Ishikawa, Sunao Funakoshi, Kozo Sakamoto, Hidekatsu Onose
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Patent number: 7274071Abstract: This invention provides an electrostatic damage protection device which can protects a device to be protected enough from an electrostatic damage and prevents damages of protection transistors themselves. A N-channel type first MOS transistor and a N-channel type second MOS transistor serving as protection transistors are connected in series between an output terminal and a ground potential. On the other hand, a P-channel type third MOS transistor and a P-channel type fourth MOS transistor serving as protection transistors are connected in series between a high power supply potential and the output terminal. These first, second, third, and fourth MOS transistors are formed of low withstand voltage MOS transistors.Type: GrantFiled: November 3, 2004Date of Patent: September 25, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Ryoichi Ando, Akira Uemoto, Toshio Kakiuchi
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Patent number: 7268398Abstract: In an NMOS device, the turn-on voltage or the triggering voltage is reduced by adding an NBL connected to an n-sinker and contacted through an n+ region, which is connected to a bias voltage. The bias voltage may be provided by the drain contact or by a separate bias voltage.Type: GrantFiled: August 14, 2006Date of Patent: September 11, 2007Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper
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Patent number: 7265422Abstract: Techniques for ESD protection are provided. An ESD protection device includes a first well region and a second well region disposed in a semiconductor substrate, with an isolation region therebetween. N+ implant regions are disposed in the second well region and are coupled in common at a first node. NLDD regions are disposed between the N+ implant regions, and pocket implants underlie each of the NLDD regions. Current discharge paths are defined by corresponding NLDD regions and pocket implants when a voltage of the first node exceeds a breakdown voltage. In a specific embodiment, the breakdown voltage is less than a breakdown voltage for a logic gate oxide.Type: GrantFiled: August 29, 2005Date of Patent: September 4, 2007Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Talee Yu, Chi Kang Liu
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Patent number: 7262468Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.Type: GrantFiled: December 28, 2001Date of Patent: August 28, 2007Assignee: Texas Instruments IncorporatedInventors: James D. Gallia, Srikanth Krishnan, Anand T. Krishnan
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Patent number: 7259429Abstract: It is an object of the present invention to provide a semiconductor display device using a protective circuit in which dielectric breakdown is prevented more effectively. In the invention, in the cases that a first interlayer insulating film is formed covering a TFT used for a protective circuit and a second interlayer insulating film, which is an insulating coating film, is formed covering a wiring formed over the first interlayer insulating film, a wiring for connecting the TFT to other semiconductor elements is formed so as to be in contact with the surface of the second interlayer insulating film so as to secure a path discharging charge accumulated in the surface of the second interlayer insulating film. Note that the TFT used for the protective diode is a so-called diode-connected TFT in which either of the first terminal or the second terminal is connected to a gate electrode.Type: GrantFiled: October 14, 2004Date of Patent: August 21, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 7253453Abstract: An integrated circuit for providing electrostatic discharge protection that includes a contact pad, a CMOS device including a transistor having a substrate, and a CDM clamp for providing electrostatic discharge protection coupled between the contact pad and the CMOS device, the CDM clamp including at least one active device, wherein the CDM clamp conducts electrostatic charges accumulated in the substrate of the transistor to the contact pad and wherein the CMOS device is coupled between a high voltage line and a low voltage line.Type: GrantFiled: May 21, 2003Date of Patent: August 7, 2007Assignee: Industrial Technology Research InstituteInventors: Ming-Dou Ker, Tang-Kui Tseng, Hsin-Chin Jiang
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Patent number: 7250660Abstract: Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.Type: GrantFiled: July 14, 2004Date of Patent: July 31, 2007Assignee: Altera CorporationInventors: Cheng-Hsiung Huang, Chih-Ching Shih, Jeffrey Tyhach, Guu Lin, Chiakang Sung, Stephanie T. Tran
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Patent number: 7242061Abstract: The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur.Type: GrantFiled: January 14, 2003Date of Patent: July 10, 2007Assignee: Seiko Epson CorporationInventors: Kazuhiko Okawa, Takayuki Saiki
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Patent number: 7238991Abstract: A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.Type: GrantFiled: September 23, 2004Date of Patent: July 3, 2007Assignee: Oki Electric Industry Co., Ltd.Inventors: Toshikazu Kuroda, Katsuhito Sasaki
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Patent number: 7235846Abstract: The present invention provides an ESD protection device or structure that exploits the high conductivity of a heavily doped heterojunction base of a standard SiGe bipolar junction transistor (BJT) cell. This improved ESD protection scheme further uses the combination of trench isolation and buried subcollector layer of the SiGe BJT to confine ESD current, minimizing parasitic substrate leakage and achieving large forward voltages while imposing minimal parasitic capacitive loads on a protected active device. Since the ESD protection structure is formed from conventional SiGe BJT transistor cells through modification of the contact metallization, it can be fabricated in an available SiGe BiCMOS fabrication process without additional processing steps, and characterization data already available for the SiGe BJTs can be used to model the performance of the ESD protection devices.Type: GrantFiled: April 27, 2005Date of Patent: June 26, 2007Assignee: WJ Communications, Inc.Inventor: Greg Fung
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Patent number: 7233475Abstract: MOS Transistors and bipolar junction transistors are connected to input pads and output pads for implementing electrostatic discharge protection. By conducting a power clamp circuit and applying a substrate-trigger technology, electrostatic discharge protection is further enhanced. For instance, positive ESD stress protection can be enhanced between signal pads (input pads and output pads) and VSS by using NMOS transistors and field oxide devices. Negative ESD stress protection can be enhanced between signal pads and VDD by using PMOS transistors.Type: GrantFiled: April 13, 2006Date of Patent: June 19, 2007Assignee: Novatek Microelectronics Corp.Inventor: Shiao-Shien Chen
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Patent number: 7227239Abstract: A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.Type: GrantFiled: September 23, 2004Date of Patent: June 5, 2007Assignee: International Business Machines CorporationInventors: Wagdi William Abadeer, John Atkinson Fifield, Robert J. Gauthier, Jr., William Robert Tonti
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Patent number: 7217984Abstract: A divided drain implant structure for transistors used for electrostatic discharge protection is disclosed. At least two transistors are formed close to each other on a substrate with their gates and sources coupled together and with the drains placed next to each other and separated as a divided drain implant structure. The divided drain implant structure further comprises at least two drain implant regions separated by a lightly doped drain region and a halo implant region formed underneath. At least one of the drain implant regions is coupled to an input/output pad of a circuit.Type: GrantFiled: June 17, 2005Date of Patent: May 15, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Chang Huang, Yu-Hung Chu
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Patent number: 7217980Abstract: An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. in one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivity type. A well region formed with a second conductivity type in the semiconductor substrate. A first region formed in the well region. A second region formed having a portion in the weil region and another portion outside the well region, but still within the semiconductor substrate. Moreover, a third region formed within the well region and in between the first; region and the second region. A fourth region formed within the semiconductor substrate and outside the well region. A fifth region formed within the semiconductor substrate and in between the second region and the fourth region.Type: GrantFiled: September 30, 2004Date of Patent: May 15, 2007Assignee: United Microelectronics Corp.Inventors: Shiao-Shien Chen, Tien-Hao Tang, Mu-Chun Wang
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Patent number: 7211868Abstract: A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.Type: GrantFiled: March 16, 2001Date of Patent: May 1, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Hirokazu Fukuda, Hiroki Etou, Kouji Takahashi