Abstract: A bi-directional silicon controlled rectifier structure provides electrostatic discharge (ESD) protection against both positive and negative voltage spikes. The structure utilizes a pair of wells, n+ and p+ regions formed in both wells, a first ring formed around the junction between the first well and the semiconductor material, and a second ring formed around the junction between the second well and the semiconductor material.

Abstract: A charging sensor is provided to detect charging signal during the manufacturing process of integrated circuits and various semiconductor devices. In one embodiment, the charging sensor includes a charging-sensitive insulator layer and complementary elements designed to effectively provide an indicative potential drop across the charging sensitive insulator.

Abstract: A device for adjusting an integrated circuit before encapsulation includes a first MOS transistor having a gate and a source connected together, and a body connected to a voltage reference. A first resistor is connected in parallel with the first MOS transistor. A second MOS transistor is connected in series with the first MOS transistor. The second MOS transistor has a gate and a source connected together, and a body connected to the voltage reference. A second resistor is connected in parallel with the second MOS transistor. A first terminal is connected to the source of the first MOS transistor, and a second terminal is connected to the source of the second MOS transistor. The first terminal is accessible externally after the integrated circuit has been encapsulated.

Abstract: A semiconductor device includes a substrate, a well region formed in the substrate, a field effect transistor formed in the well region, and a diffused region, formed across the well region and the substrate for applying back gate potential to the well region, and forming a PN junction together with its periphery. The field effect transistor and the PN junction are connected between terminals for absorbing excess current so that an internal circuit connected to the terminals is protected.

Abstract: The invention describes structures and a process for providing ESD protection between multiple power supply lines or buses on an integrated circuit chip. Special diode strings are used for the protection devices whereby the diodes are constructed across the boundary of an N-well and P substrate or P-well. The unique design provides very low leakage characteristics during normal circuit operation, as well as improved trigger voltage control achieved by stacking 2 or more diodes in a series string between the power buses.

Abstract: A semiconductor integrated circuit is provided, which has an improved withstanding voltage for electrostatic breakdown at the time of electrostatic discharge by the charged device model, in the case of protecting a MOS capacitor provided at the input side of the internal circuit.

Abstract: A cascaded diode structure with a deep N-well for effectively reducing the leakage current of the P-type substrate by floating the base of a parasitic transistor in the cascaded diode structure. The cascaded diode structure includes a P-type substrate, a deep N-well formed on the P-type substrate, a plurality of elemental diodes formed on the deep N-well, and a plurality of connecting parts for cascading the elemental diodes. Each elemental diode includes a P-well formed on the deep N-well, a heavily doped P-type region formed on the P-well, and a heavily doped N-type region formed on the P-well.

Abstract: The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).

Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, a first and a second doped region formed in the substrate. The first and second doped regions are separated from each other by only the substrate region. The ESD protection device includes no gate above the first and second doped regions. Furthermore, the distance separating the first and second doped regions is defined by a length of a resist during a process of forming the ESD protection device.

Abstract: A semiconductor integrated circuit including a digital circuit and an analog circuit which are integrated on a single semiconductor chip comprises a first electrostatic destruction protection circuit, connected to a digital circuit, for protecting the digital circuit from destruction caused by ESD therein by an influence of an input digital signal and a second electrostatic destruction protection circuit, connected to an analog circuit, for protecting the analog circuit from destruction caused by ESD therein by an influence of an input analog signal. A first grounding conductor connected to the first electrostatic destruction protection circuit and a second grounding conductor connected to the second electrostatic destruction protection circuit are connected to each other outside the semiconductor integrated circuit.

Abstract: The present invention is a method and apparatus whereby two NMOS or PMOS devices connected in a stacked gate configuration formed on SOI exhibit improved ESD response characteristics. The shared source-drain region between the two devices is formed to have a dopant depth in the shared region that does not extend through the silicon layer to the BOX layer. This provides a common body for the two devices, and thus a single parasitic bipolar transistor is formed between the drain of one NMOS or PMOS device and the source of the second NMOS or PMOS device. Simultaneous snapback occurs for the two devices through the common body. A further embodiment includes a method of forming two or more stacked gate NMOS or PMOS devices on SOI. The method includes protecting the shared source-drain region between two NMOS or PMOS devices during a final doping step and silicide processing.

Abstract: The isolated high-voltage LDMOS transistor according to the present invention includes a split N-well and P-well in the extended drain region. The P-well is split in the extended drain region of the N-well to form a split junction-field in the N-well. The split N-well and P-well deplete the drift region, which shifts the electric field maximum into the bulk of the N-well. This achieves a higher breakdown voltage and allows the N-well to have a higher doping density. Furthermore, the LDMOS transistor according to the present invention includes a N-well embedded beneath the source diffusion region. This creates a low-impedance path for the source region, which restricts the transistor current flow between the drain region and the source region.

Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.

Abstract: A protection structure against electrostatic discharges for a semiconductor electronic device that is integrated inside a well is disclosed, wherein the well is formed on a SOI substrate and isolated dielectrically by a buried oxide layer and an isolation structure, which isolation structure includes in turn at least a dielectric trench filled with a filler material. Advantageously, the protection structure is formed at the isolation structure.

Abstract: The semiconductor device includes a plurality of transistors, wherein one of the transistors that has the thinnest gate dielectric layer is selected to serve as a power source protection element, among a plurality of transistors, each having a gate dielectric layer of an independently set film thickness, disposed on a same substrate to be operated by a voltage from a same power source. Also, a threshold voltage of the transistor selected as the power source protection element is set higher than other transistor that also has the thinnest gate dielectric layer.

Abstract: An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.

Abstract: A protection circuit for MOS components. In the protection circuit, a bypass PMOS transistor has a gate, a source and a substrate, all coupled to a first voltage node and a drain coupled to a gate of a MOS component. A bypass NMOS transistor has a gate, a source and a substrate, all coupled to a second voltage node and a drain coupled to the gate of the MOS component. When positive charges are accumulated on the gate of the MOS component due to an antenna effect, the bypass PMOS transistor dissipates the positive charges to the first voltage node. On the contrary, when negative charges are accumulated on the gate of the MOS component due to antenna effect, the bypass NMOS transistor dissipates the negative charges to the second voltage node.

Abstract: An NMOS device having protection against electrostatic discharge. The NMOS device includes a P-substrate, a P-epitaxial layer overlying the P-substrate, a P-well in the P-epitaxial layer, an N-well in the P-epitaxial layer and encompassing the P-well, an N-Buried Layer (NBL) underneath the P-well and bordering the N-well. The P-well is fully isolated by the N-well and the NBL. The NMOS device further includes a first isolation structure consisting of a gate-insulating layer connected with a field oxide layer, which is formed on the P-epitaxial layer. A gate overlies the first isolation structure. A second isolation structure laterally spaced apart from the first isolation structure is approximately situated on the N-well. An N+ source doping region, which functions as a source of the NMOS device, is disposed in the P-well. An N+ drain doping region, which functions as a drain of the NMOS device, is disposed in the N-well.

Abstract: An ESD protection circuit with high substrate-triggering efficiency. The circuit comprises a multi-finger-type device having a plurality of finger gates below which a parasitic BJT is formed, a plurality of finger sources, each of which is an emitter of one parasitic BJT, and at least one finger drain coupled to a pad, a plurality of voltage drop elements, each of which is coupled between one of the finger sources and a power line to detect a transient current flowing through one of the finger gates, and a plurality of feedback circuits, each of which is coupled between a base and an emitter respectively of a first and second parasitic BJT, and activates the first BJT to bypass ESD current during an ESD event.

Abstract: ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: An ESD NMOS structure with an odd number of N-type structures built into a P-type well. Buried N-type structures are positioned between the N-type structures. The center N-type structure and each alternate N-type structure are electrically connected to each other, to the buried N-type structures, and to the output contact; while the other N-type structures are electrically connected to each other and the P-well and to ground. When a positive ESD event occurs, a depletion zone is created in the P-well between the N-type buried structures and the N-type structures thereby increasing the resistivity of the structure. Moreover, when a positive ESD event occurs, the lateral NPN transistors on either side of the center N-type structure break down and snap back. The resulting current travels through the area of increased resistivity and thereby creates a larger voltage along the P-well from the center N-type structure out toward the distal N-type structures.

Abstract: An electrostatic discharge (ESD) protection device with enhanced ESD robustness. The ESD protection device comprises a pad, a finger-type MOS, a well stripe and a doped segment. The pad is on a semiconductor substrate of a first-conductive type. The finger-type MOS is on the semiconductor substrate and comprises drain regions, source regions and channel regions. Each drain region is of a second-conductive type and is coupled to the pad. Each source region is of the second-conductive type and coupled to a power rail. Channel regions are formed on the semiconductor, substantially parallel to each other. Each channel region is located between one source region and one drain region. The well stripe is of the second-conductive type and formed on the semiconductor, in an angle to the channel regions. The doped segment is of the first-conductive type and in the well stripe. Furthermore, the doped segment is coupled to the pad.

Abstract: This invention provides a semiconductor device that does not cause a defect at an intersection of wirings even when a surge voltage enters from a signal input terminal, an electro-optic device provided with the semiconductor device as a TFT array substrate, and an electronic instrument. In a TFT array substrate of a liquid crystal device, a signal input terminal, and terminals are arranged along a substrate side, and a signal input line extends from the signal input terminal to a substrate side. Of constant potential lines that supply constant potential to an electrostatic protection circuit for the signal input line, a low potential line does not at all intersect the signal input line, and a high potential line, though intersecting the signal input line, does not intersect a wiring portion from the signal input terminal to the electrostatic protection circuit.

Abstract: A sophisticated and highly reliable high-frequency Si-MOS semiconductor device having high electrostatic discharge (ESD) resistance. Lateral polysilicon diodes are connected between high-frequency I/O signal lines and the external supply voltage, VDD, and between the ground, GND, and the high-frequency I/O signal lines, respectively. The forward direction of the diodes is the direction from the high-frequency I/O signal line to the supply voltage, VDD, and the direction from the ground, GND, to the high-frequency I/O signal line, respectively.

Abstract: An electrostatic discharge protection circuit coupled between an I/O pad and an internal circuit of an IC. The electrostatic discharge protection circuit includes a first diode having a positive end coupled to the I/O pad, and a negative end coupled to a first supply voltage; a second diode having a positive end coupled to a second supply voltage, and a negative end coupled to the I/O pad; and a third diode having a positive end coupled to the second supply voltage, and a negative end coupled to the first-supply voltage. The breakdown voltage of the third diode is substantially smaller than the breakdown voltage of the first diode or the breakdown voltage of the second diode.

Abstract: A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

Abstract: An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.

Abstract: An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid unit surrounding a rectangular semiconductor island (102). Each island contains three parallel regions of the opposite conductivity type: the center region (104) is operable as the transistor drain and the two other regions (103 and 105), abutting the isolations, are operable as transistor sources. Transistor gates (106 and 107) are between the parallel regions, completing the formation of two transistors having one common drain. Electrical contacts (108) are placed on both source regions and the drain region. The source contacts are placed so that the spacing (120) between each contact and its respective isolation is at least twice as large as the spacing (121) between each contact and the gate.

Abstract: A pMOS transistor (601) is located in an n-well (602) and has at least one gate (603). Transistor (601) is connected between power pad Vdd or I/O pad (604) and ground potential Vss (605). Gate (603) is connected to power pad (604). The n-well (602) is capacitively (620) coupled to ground (605), decoupled from the transistor source (606) and floating under normal operating conditions. Under an ESD event, the diode formed by the source (606) and the n-well (602) is forward biased (n-well negatively biased) to turn on the lateral pnp transistor to discharge the ESD current. The well voltage keeps increasing up to the value that triggers the lateral bipolar pnp transistor. The ESD protection is scalable with the width of gate (603), improving with shrinking gate width.

Abstract: The invention concerns an anode voltage sensor of a vertical power component selected from the group consisting of components called thyristor, MOS, IGBT, PMCT, EST, BRT transistor, MOS thyristor, turn-off MOS thyristor, formed by a lightly doped N-type substrate (1) whereof the rear surface (2) having a metallizing coat corresponds to the component anode. Said sensor comprises, on the front surface side, a substrate zone (12) surrounded at least partly by a P-type region with low potential in front of an anode potential, said zone (12) being coated with a metallizing coat (M) in ohmic contact with it, whereon is provided an image of the anode voltage.

Abstract: A semiconductor device including an electrostatic protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer. A plurality of salicide N-type MOS transistors isolated by a first diffusion region are formed on a semiconductor substrate of this semiconductor device. An NPN lateral bipolar transistor and a Zener diode are formed as an electrostatic protection circuit for these MOS transistors. The NPN lateral bipolar transistor includes a P-type well and a second diffusion region which is formed in a region isolated by two second isolation regions. The Zener diode is formed by the PN junction between the first diffusion region of the MOS transistor and a third diffusion region. The breakdown start voltage of the Zener diode is set to be lower than the breakdown start voltage of the MOS transistor.

Abstract: An ESD protection device with thicker polysilicon film, an electronic apparatus having the same, and a method for manufacturing the same are provided. The ESD protection device can be a diode or a MOS transistor with a thicker polysilicon film employed in an ESD protection circuit to protect an electronic apparatus. The electronic apparatus includes a substrate having a device area and an ESD protection circuit area. A first polysilicon film of a first thickness is formed on the device area of the substrate, so as to form an electronic device. A second polysilicon film of a second thickness is formed on the ESD protection circuit area, so as to form an ESD protection device. The second thickness, which is preferably about in the range of 100 to 500 nanometers, is thicker than the first thickness.

Abstract: A semiconductor device for use in includes a base and emitter shorted by means of a surface electrode. The surface electrode of a vertical-type bipolar transistor in which a P-type epitaxial growth layer and a P-type semiconductor substrate form the collector is electrically connected to the drain electrode of a lateral MOSFET by means of a metal electrode wiring. Upon application of a high ESD voltage and high surge voltage, the energy of the ESD and surge is absorbed by operation of the vertical-type bipolar transistor and is limited to a voltage equal to or less than the breakdown voltage of the lateral MOSFET that was to be destroyed.

Abstract: A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions.

Abstract: A complementary metal-oxide semiconductor (CMOS) structure for a battery protection circuit and a battery protection circuit therewith. A tri-well technique or a buried layer technique is used for such CMOS structure to allow the battery protection circuit therewith to operate at different low voltage levels. Thereby, low voltage process can be realized to effectively reduce the cost of the chip and simplify the design.

Abstract: An electrostatic discharge device may provide better protection of an integrated circuit by more uniform breakdown of a plurality of finger regions. The plurality of finger regions may extend through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. An electrostatic discharge device may include a collector region having a middle region that may be highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the electrostatic discharge device.

Abstract: A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer and a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

Abstract: The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the present invention uses a novel I/O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and/or varying channel lengths in the layout structure.

Abstract: A structure of a semiconductor device facilitating electrostatic discharge protection at least includes a source terminal, a drain terminal, and a gate terminal, wherein a portion of the source terminal and a portion of the drain terminal are overlapped above the gate terminal to increase the coupling capacitance so that the electrostatic discharge protection device can be turned on quickly. Accordingly the response of the electrostatic discharge protection device to an electrostatic discharge can be effectively promoted.

Abstract: A surge protection device includes a gate electrode embedded in an insulator, a source electrode and a drain electrode on the insulator. The source and drain electrodes respectively form first and second capacitances with the gate electrode. A semiconductor island is provided on the insulator to form a channel between the source and drain electrodes and a third capacitance with the gate electrode. The third capacitance is smaller than either of the first and second capacitances. The source and drain electrodes are adapted for connection to external circuitry for establishing a low-impedance path when the external circuitry is subjected to a surge potential.

Abstract: A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first vias, a first conductive line, a plurality of second conductive lines and a plurality of second vias. The conductive layers are parallel layers each at a different height level between the bonding pad and a substrate. The first vias connect the bonding pad electrically with a neighboring conductive layer as well as each neighboring conductive layer. The first conductive line connects electrically with the conductive layer nearest the substrate and the drain terminal of an ESD protection circuit. The second conductive lines are parallel lines each at a different height level between the first conductive line and the bonding pad. Each second conductive line connects electrically with the conductive layer at a corresponding height level.

Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.

Abstract: An ESD protection device (20) comprises an N-type epitaxial collector (21), a first, lightly doped, deep base region (221) and second, highly doped, shallow base region (222) that extends a predetermined lateral dimension. The device responds to an ESD event by effecting vertical breakdown between the base regions and the N-type epitaxial collector. The ESD response is controlled by the predetermined lateral dimension, S, which, in one embodiment, may be is determined by a single masking step. Consequently, operation of the ESD protection device is rendered relatively insensitive to the tolerances of a fabrication process, and to variations between processes.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of suppressing stresses concentrated at bottom corners of a gate electrode as simultaneously as preventing an oxidation of a metal included in a gate electrode. The inventive method includes the steps of: forming a gate oxide layer on a substrate; forming a gate electrode including at least one metal layer on the gate oxide layer; forming an oxide layer on the substrate including the gate electrode at a temperature lower than oxidation temperature of the metal layer; and etching selectively the densified oxide layer so as to form an oxide spacer on the lateral sides of the gate electrode.

Abstract: The invention provides an ESD protection circuit compatible with the high voltage device manufacturing processes by using parasitic bipolar junction transistor punch characteristics. The design of the present invention takes advantage of bipolar punch characteristics of the parasitic NPN or PNP bipolar structure to bypass the ESD current, thus significantly increasing the ESD level. In addition, the ESD protection circuit of the present invention can greatly reduce the ESD cell areas by eliminating certain prior art diode structure.

Abstract: A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.

Abstract: A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.

Abstract: An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid unit surrounding a rectangular semiconductor island (102). Each island contains three parallel regions of the opposite conductivity type: the center region (104) is operable as the transistor drain and the two other regions (103 and 105), abutting the isolations, are operable as transistor sources. Transistor gates (106 and 107) are between the parallel regions, completing the formation of two transistors having one common drain. Electrical contacts (108) are placed on both source regions and the drain region. The source contacts are placed so that the spacing (120) between each contact and its respective isolation is at least twice as large as the spacing (121) between each contact and the gate.

Abstract: Disclosed is an improved hard macro design for use in an ASIC, which avoids undesirable buildup of electrostatic charge on a gate of an I/O transistor of the hard macro. The hard macro includes a port level metallic conductor of an I/O port positioned at a low level metalization layer and an electrical connection between the port level metallic conductor and a gate conductor of the I/O transistor. The electrical connection includes a first conducting section extending from the gate conductor to a top level metallic conductor at a highest level metalization layer and a second conducting section extending from the top level metallic conductor layer to the port level conductor. Antenna rule violations at the I/O port of the hard macro are eliminated due to the electrical connection between the top level metallic conductor and a diffusion region.

Abstract: A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and a fourth polycrystalline silicon film, wherein the first polycrystalline silicon film and the third polycrystalline silicon film have substantially the same thickness; the first polycrystalline silicon film and the third polycrystalline silicon film have different impurity concentrations controlled independently of each other; the second polycrystalline silicon film and the fourth polycrystalline silicon film have substantially the same thickness, and the second polycrystalline silicon film, the fourth polycrystalline silicon film, and the third polycrystalline silicon film have substantially the same impurity concentration.