With Window Means Patents (Class 257/434)
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Patent number: 8513757Abstract: An image sensor assembly includes an image sensor die attached adjacent to a cavity and a lower surface in a preformed package having substantially vertical surfaces extending from the lower surface to an upper surface of the package. The image sensor die provides the light receiving surface for capturing the image. A light absorbing layer is applied to a cover such that the light absorbing layer prevents light from falling on the substantially vertical surfaces of the preformed package without preventing the passage of light that falls on the light receiving surface of the image sensor die. The light absorbing layer includes openings that provide a line-of-sight view of two opposing corners of at least one of the light receiving surface and the image sensor die to facilitate placing the cover over the upper surface of the package in registry with the image sensor die.Type: GrantFiled: July 18, 2012Date of Patent: August 20, 2013Assignee: Apple Inc.Inventors: Terence N. Tam, Jeffrey N. Gleason
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Patent number: 8507309Abstract: A photosensor comprises a photoelectric conversion device region and a connection pad on the lower surface of a semiconductor substrate, and also comprises a wiring line connected to the connection pad via insulating film under the semiconductor substrate, and a columnar electrode as an external connection electrode connected to the wiring line. As a result, as compared with the case where the photoelectric conversion device region and the connection pad connected to the photoelectric conversion device region are formed on the upper surface of the semiconductor substrate, a piercing electrode for connecting the connection pad and the wiring line does not have to be formed in the semiconductor substrate. Thus, the number of steps can be smaller, and a fabrication process can be less restricted.Type: GrantFiled: May 25, 2011Date of Patent: August 13, 2013Assignee: Teramikros, Inc.Inventors: Ichiro Mihara, Takeshi Wakabayashi
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Patent number: 8502334Abstract: Disclosed is an image sensor including a photo-sensing device, a color filter positioned on the photo-sensing device, a microlens positioned on the color filter, and an insulation layer positioned between the photo-sensing device and the color filter, and including a trench exposing the photo-sensing device and a filler filled in the trench. The filler has light transmittance of about 85% or more at a visible ray region, and a higher refractive index than the insulation layer. A method of manufacturing the image sensor is also provided.Type: GrantFiled: September 20, 2011Date of Patent: August 6, 2013Assignee: Cheil Industries Inc.Inventors: Kil-Sung Lee, Jae-Hyun Kim, Chang-Min Lee, Eui-June Jeong, Min-Soo Kim, Hwan-Sung Cheon, Tu-Won Chang
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Publication number: 20130175650Abstract: An image sensor assembly includes an image sensor die attached adjacent to a cavity and a lower surface in a preformed package having substantially vertical surfaces extending from the lower surface to an upper surface of the package. The image sensor die may include a charge-coupled device or an active pixel sensor imager that provides the light receiving surface for capturing the image. A cover is placed over the upper surface of the package. The cover may be a glass cover or an infrared cut filter. A light absorbing layer is applied to the cover in registry with the image sensor die such that the light absorbing layer prevents light from falling on the substantially vertical surfaces of the preformed package without preventing the passage of light that falls on the light receiving surface of the image sensor die.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: Apple IncInventor: Jeffrey N. Gleason
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Patent number: 8482012Abstract: A chip module package structure applied to an optical input device includes a cover body, a first chip module, and a second chip module. The first chip module and the second chip module are respectively combined with the cover body, the first chip module has an optical source, and the second chip module has an optical sensor. Further, the optical source and the optical sensor form a preset relative spatial position relation, such that a part of light emitted by the optical source is received by the optical sensor after at least one reflection.Type: GrantFiled: July 12, 2010Date of Patent: July 9, 2013Assignee: Pixart Imaging Inc.Inventors: Kuo-Hsiung Li, Hung-Ching Lai
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Patent number: 8476726Abstract: Provided is a semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device has a semiconductor element having a plurality of wires bonded to the semiconductor element with sufficient bonding reliability and has a good heat dissipation property. A semiconductor device in which a first wire is ball bonded on an electrode, and a second wire is further bonded on the ball-bonded first wire, and the first wire or an end of the second wire defines a space between itself and the ball portion of the first wire.Type: GrantFiled: April 29, 2010Date of Patent: July 2, 2013Assignee: Nichia CorporationInventor: Satoshi Shirahama
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Patent number: 8466527Abstract: A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.Type: GrantFiled: October 29, 2010Date of Patent: June 18, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Sun Jang, Woon-Seong Kwon, Tae-Je Cho, Un-Byoung Kang, Jung-Hwan Kim
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Patent number: 8455902Abstract: An optical device is equipped with a light receiving region 16a and a peripheral circuit region 22 located around the light receiving region 16a on a major surface of an light receiving element 11a; electrodes for external connection 15 electrically connected to the peripheral circuit region 22 formed on a back surface opposite to the major surface of the light receiving element 11a; a transparent member 12 covering the light receiving region 16a adhered on the major surface of the light receiving element 11a with a light-transmitting adhesive 13; and a molding resin 14 for coating side surfaces of the transparent member 12 and the major surface of the light receiving element 11a excluding the region covered with the transparent member 12.Type: GrantFiled: July 28, 2011Date of Patent: June 4, 2013Assignee: Panasonic CorporationInventors: Kiyokazu Itoi, Toshiyuki Fukuda, Yoshiki Takayama, Tetsushi Nishio, Tetsumasa Maruo
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Patent number: 8450770Abstract: A light emitting diode (LED) package structure comprising a carrier, an LED chip, a first encapsulant, at least one bonding wire, a plurality of phosphor particles and a second encapsulant is provided. The LED chip is disposed on the carrier. The LED chip has at least one electrode. The first encapsulant is disposed on the carrier and covering the LED chip. The first encapsulant is provided with at least one preformed opening exposing at least a portion of the at least one electrode. The at least one bonding wire is electrically connected between the at least one electrode and the carrier via the at least one preformed opening. The phosphor particles are distributed within the first encapsulant. The second encapsulant is disposed on the carrier and encapsulates the LED chip, the first encapsulant and the at least one bonding wire.Type: GrantFiled: May 11, 2010Date of Patent: May 28, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hyunsoo Jeong, Seongoo Lee, Ryungshik Park, Hyunil Lee
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Patent number: 8450822Abstract: Disclosed herein an image sensor chip, including a substrate having at least one via extending through at least one inter layer dielectric (ILD); a first conductive layer over the ILD, wherein the first conductive layer has a first thickness; a second conductive layer over the first conductive layer, wherein the second conductive layer has a second thickness of less than the first thickness; a polymer layer over the second conductive layer, the polymer layer including a cavity; a plurality of cavity components in the cavity; and an optically transparent layer contacting the polymer layer and covering the cavity.Type: GrantFiled: September 23, 2009Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Robert K. Leidy, Richard J. Rassel
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Patent number: 8450847Abstract: A method for producing an optoelectronic device includes providing a carrier, applying at least one first metal layer on the carrier, providing at least one optical component, applying at least one second metal layer on the at least one optical component, and mechanically connecting the carrier to the at least one optical component by the at least one first and the at least one second metal layer, wherein the connecting includes friction welding or is friction welding.Type: GrantFiled: November 2, 2009Date of Patent: May 28, 2013Assignee: OSRAM Opto Semiconductors GmbHInventors: Patrick Ninz, Herbert Brunner
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Patent number: 8445984Abstract: According to one embodiment, a micro-optical device includes an electro-optical circuit and an annular frame disposed on a surface of a substrate. The electro-optical circuit has an active region that is encapsulated by a window and an interconnect region adjacent at least one edge of the electro-optical circuit. The annular frame extends around an outer periphery of the window and is separated from the window by a gap, the annular frame and the electro-optical circuit form a cavity for placement of a plurality of bonding wires the interconnect that electro-optical circuit to the substrate.Type: GrantFiled: May 3, 2011Date of Patent: May 21, 2013Assignees: Texas Instruments Incorporated, Amkor Technology, Inc.Inventors: Bradley Morgan Haskett, John Patrick O'Connor, Mark Myron Miller, Sean Timothy Crowley, Jeffrey Alan Miks, Mark Phillip Popovich
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Patent number: 8440491Abstract: An imager device is disclosed including a first substrate having an array of photosensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure formed above the first substrate, a second conductive layer formed above the standoff structure, the second conductive layer being conductively coupled to the first conductive layer, and an electrically powered device positioned above the standoff structure, the electrically powered device being electrically coupled to the second conductive layer.Type: GrantFiled: July 2, 2010Date of Patent: May 14, 2013Assignee: Micron Technology, Inc.Inventor: Warren Farnworth
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Patent number: 8426954Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.Type: GrantFiled: August 18, 2011Date of Patent: April 23, 2013Assignee: Round Rock Research, LLCInventors: Todd O. Bolken, Chad A. Cobbley
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Patent number: 8421175Abstract: A wafer level packaged integrated circuit includes an array of contacts, a silicon layer and a glass layer. The silicon and glass layers are bonded together to form a bonding material layer therebetween. The bonding material layer includes gaps between the silicon layer and the glass layer at areas where no bonding material is present. An array of contacts is adjacent the semiconductor layer on a side thereof opposite the bonding layer. The wafer level packaged integrated circuit is provided with additional bonding material layer portions within the gaps and aligned with at least some of the contacts. When the wafer level packaged integrated circuit is configured as an image sensor or display having a pixel array, the additional bonding material layer portions are not used in an area of the pixel array.Type: GrantFiled: September 10, 2009Date of Patent: April 16, 2013Assignee: STMicroelectronics ( Research & Development) LimitedInventor: Robert Nicol
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Patent number: 8421207Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface at an opposite side thereof. The first surface has an active layer with a light-receiving part. The semiconductor device also includes an adhesive layer provided to surround the light-receiving part on the first surface of the semiconductor substrate; a light-transmissive protective member disposed above the light-receiving part of the semiconductor substrate with a predetermined gap and adhered via the adhesive layer; and plural external connection terminals arranged in a predetermined array on the second surface of the semiconductor substrate are included. Each center point of the external connection terminals forming two facing edges is positioned inside of an area of the adhesive layer projected on the second surface among the outermost external connection terminals.Type: GrantFiled: September 14, 2010Date of Patent: April 16, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Hideko Mukaida
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Patent number: 8410568Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.Type: GrantFiled: August 25, 2009Date of Patent: April 2, 2013Assignee: Tau-Metrix, Inc.Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nader Pakdaman
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Patent number: 8410569Abstract: A solid-state imaging device includes a first substrate including a light-sensing portion configured to perform photoelectric conversion of incident light and a wiring portion provided on a light-incident side; an optically transparent second substrate provided on a wiring portion side of the first substrate at a certain distance; a through-hole provided in the first substrate; a through-via provided in the through-hole; a front-surface-side electrode connected to the through-via and provided on a front surface of the first substrate; a back-surface-side electrode connected to the through-via and provided on a back surface of the first substrate; and a stopper electrode provided on the front-surface-side electrode and filling a space between the front-surface-side electrode and the second substrate.Type: GrantFiled: July 23, 2010Date of Patent: April 2, 2013Assignee: Sony CorporationInventors: Ikuo Yoshihara, Masaya Nagata, Naoto Sasaki, Taku Umebayashi, Hiroshi Takahashi, Yoichi Otsuka, Isaya Kitamura, Tokihisa Kaneguchi, Keishi Inoue, Toshihiko Hayashi, Hiroyasu Matsugai, Mayoshi Aonuma, Hiroshi Yoshioka
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Patent number: 8410511Abstract: High temperature semiconducting materials in a freestanding epitaxial chip enables the use of high temperature interconnect and bonding materials. Process materials can be used which cure, fire, braze, or melt at temperatures greater than 400 degrees C. These include, but are not limited to, brazing alloys, laser welding, high-temperature ceramics and glasses. High temperature interconnect and bonding materials can additionally exhibit an index of refraction intermediate to that of the freestanding epitaxial chip and its surrounding matrix. High index, low melting point glasses provide a hermetic seal of the semiconductor device and also index match the freestanding epitaxial chip thereby increasing extraction efficiency. In this manner, a variety of organic free semiconducting devices, such as solid-sate lighting sources, can be created which exhibit superior life, efficiency, and environmental stability.Type: GrantFiled: October 16, 2009Date of Patent: April 2, 2013Assignee: Goldeneye, Inc.Inventors: Scott M. Zimmerman, Karl W. Beeson, William R. Livesay
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Patent number: 8404513Abstract: A method for generating electric power including the steps of: (a) preparing a solar cell having a condensing lens and a solar cell element, wherein the solar cell element includes an n-type GaAs layer, a p-type GaAs layer, a quantum tunneling layer, an n-type InGaP layer, a p-type InGaP layer, a p-type window layer, an n-side electrode, and a p-side electrode, and satisfies the following equation (I): d2<d1, d3<d1, nanometer?d2?4 nanometers, 1 nanometer?d3?4 nanometers, d5<d4, d6<d4, 1 nanometer?d5?5 nanometers, 1 nanometer?d6?5 nanometers, 100 nanometers?w2, 100 nanometers?w3, 100 nanometers?w4, and 100 nanometers?w5. . . (I); and (b) irradiating a region S which is included in the surface of the p-type window layer through the condensing lens with light to satisfy the following equation (II) in order to generate a potential difference between the n-side electrode and the p-side electrode: w6?w1. . . (II).Type: GrantFiled: June 1, 2012Date of Patent: March 26, 2013Assignee: Panasonic CorporationInventors: Akio Matsushita, Akihiro Itoh, Tohru Nakagawa, Hidetoshi Ishida
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Patent number: 8399945Abstract: A semiconductor light detecting element includes: a semiconductor substrate; and a distributed Bragg reflector layer of a first conductivity type, an optical absorption layer, and a semiconductor layer of a second conductivity type, sequentially laminated on the semiconductor substrate. The distributed Bragg reflector layer includes first and second alternately laminated semiconductor layers with different band-gap wavelengths, sandwiching the wavelength of detected incident light. The sum of thicknesses a first and a second semiconductor layer is approximately one-half the wavelength of the incident light detected.Type: GrantFiled: May 20, 2010Date of Patent: March 19, 2013Assignee: Mitsubishi Electric CorporationInventors: Masaharu Nakaji, Ryota Takemura
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Publication number: 20130062720Abstract: An integrated circuit chip includes a window cover over etchant holes in a dielectric layer and over a cavity in the substrate of said integrated circuit chip. The window cover extends at least 400 microns beyond the edge of the cavity. An integrated sensor chip with a sensor cover which extends at least 400 microns beyond the edges of a cavity. A method of forming an integrated sensor chip with a sensor cover which extends at least 400 microns beyond the edge of a cavity.Type: ApplicationFiled: March 5, 2012Publication date: March 14, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Rick L. Wise, Kalin Valeriev Lazarov, Karen Hildegard Ralston Kirmse, Kandis Meinel
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Patent number: 8390087Abstract: The present invention discloses an image sensor package structure with a large air cavity. The image sensor package structure includes a substrate, a chip, a cover and a package material. The chip is combined with the substrate. A plastic sheet of the cover is adhered to the chip and a transparent lid of the cover is combined with the plastic sheet to provide a covering over a sensitization area of the chip so as to form an air cavity. The package material is arranged on the substrate and encapsulated around the chip and the cover. The plastic sheet having a predetermined thickness can increase the distance between the transparent lid and the chip to enlarge the air cavity. Thus, the image-sensing effect of the image sensor package structure can be improved and the ghost image problem resulting from multi-refraction and multi-reflection of light can be minimized.Type: GrantFiled: January 7, 2010Date of Patent: March 5, 2013Assignee: Kingpak Technology Inc.Inventors: Hsiu-Wen Tu, Ren-Long Kuo, Young-Houng Shiao, Tsao-Pin Chen, Mon-Nam Ho, Chih-Cheng Hsu, Chin-Fu Lin, Chung-Hsien Hsin
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Patent number: 8390003Abstract: An electronic element wafer module according to the present invention is provided, in which a translucent support substrate for covering and protecting a plurality of electronic elements is attached on an electronic element wafer having the plurality of electronic elements formed thereon, and an optical filter is formed corresponding to the electronic elements on at least one surface of the translucent support substrate, where the optical filter is removed to lessen warping along a part or all of dicing lines for individually dividing the electronic element wafer module into a plurality of electronic element modules.Type: GrantFiled: May 29, 2009Date of Patent: March 5, 2013Assignee: Sharp Kabushiki KaishaInventors: Tohru Ida, Eiichi Hirata
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Patent number: 8390047Abstract: An implantable, miniaturized platform and a method for fabricating the platform is provided, where the e platform includes a top cover plate and a bottom substrate, top cover plate including an epitaxial, Si-encased substrate and is configured to include monolithically grown devices and device contact pads, the Si-encased substrate cover plate including a gold perimeter fence deposited on its Si covered outer rim and wherein the bottom substrate is constructed of Si and includes a plurality of partial-Si-vias (PSVs), electronic integrated circuits, device pads, pad interconnects and a gold perimeter fence, wherein the device pads are aligned with a respective device contact pad on the top cover plate and includes gold bumps having a predetermined height, the top cover plate and the bottom substrate being flip-chip bonded to provide a perimeter seal and to ensure electrical connectivity between the plurality of internal devices and at least one external component.Type: GrantFiled: November 16, 2009Date of Patent: March 5, 2013Inventors: Faquir Chand Jain, Fotios Papadimitrakopoulos
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Patent number: 8384699Abstract: The present invention intends to realize a narrow frame of a system on panel. In addition to this, a system mounted on a panel is intended to make higher and more versatile in the functionality. In the invention, on a panel on which a pixel portion (including a liquid crystal element, a light-emitting element) and a driving circuit are formed, integrated circuits that have so far constituted an external circuit are laminated and formed. Specifically, of the pixel portion and the driving circuit on the panel, on a position that overlaps with the driving circuit, any one kind or a plurality of kinds of the integrated circuits is formed by laminating according to a transcription technique.Type: GrantFiled: October 19, 2011Date of Patent: February 26, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yuugo Goto, Yumiko Ohno, Yasuyuki Arai, Noriko Shibata
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Patent number: 8368096Abstract: There are provided image pickup devices capable of significantly increasing production yield and ensuring long-term reliability and a method for manufacturing the image pickup devices.Type: GrantFiled: December 27, 2005Date of Patent: February 5, 2013Assignee: AAC Technologies Japan R&D Center Co., Ltd.Inventors: Osamu Asano, Hitoo Iwasa, Sumio Terakawa, Masami Shouji
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Patent number: 8368110Abstract: A side view light emitting diode (LED) package structure includes a package housing, a side view LED chip and a thermal conductive member. The side view LED chip is enclosed by the package housing and an emitting direction of the side view LED chip is perpendicular to a thickness direction of a substrate. The thermal conductive member connected with the side view LED chip is disposed inside the package housing and a portion of which extends out of a dissipation opening of the package housing to be exposed so that heat of the side view LED chip is dissipated.Type: GrantFiled: September 19, 2007Date of Patent: February 5, 2013Assignee: Everlight Electronics Co., Ltd.Inventors: Yi-Tsuo Wu, Chung-Chuan Hsieh, Chia-Hsien Chang
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Publication number: 20130020491Abstract: The photodetector device includes a semiconductor body having a front surface, and an active-area region that extends in the semiconductor body facing the front surface and is configured for receiving a light radiation and generating, in response to the light radiation received, electric charge carriers. A polydimethylsiloxane cover layer extends on the front surface in the active-area region so that the light radiation is received by the active-area region through the cover layer.Type: ApplicationFiled: April 10, 2012Publication date: January 24, 2013Applicant: STMicroelectronics S.r.l.Inventor: Massimo Cataldo MAZZILLO
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Patent number: 8354294Abstract: A method, apparatus and material produced thereby in an amorphous or crystalline form having multiple elements with a uniform molecular distribution of elements at the molecular level.Type: GrantFiled: July 26, 2010Date of Patent: January 15, 2013Inventors: L. Pierre de Rochemont, Alexander J. Kovacs
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Patent number: 8344431Abstract: An image sensor includes a light receiving device, a field effect transistor, a stress layer pattern, and a surface passivation material. The light receiving device is formed in a first region of a substrate. The field effect transistor is formed in a second region of the substrate. The stress layer pattern is formed over the field effect transistor for creating stress therein to improve transistor performance. The surface passivation material is formed on the first region of the substrate for passivating dangling bonds at the surface of the light receiving device.Type: GrantFiled: April 27, 2011Date of Patent: January 1, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyoun-Min Beak, Tae-Seok Oh, Jong-Won Choi, Su-Young Oh
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Publication number: 20120313203Abstract: A semiconductor package includes a wiring board, an electronic component mounted on the wiring board, and an enclosing frame arranged on an upper surface of the electronic component. The enclosing frame includes a basal portion, which has the form of a closed frame and extends along the upper surface of the electronic component, and an adhesion portion, which is wider than the basal portion and is arranged on the upper surface of the basal portion. A cap is adhered to an upper surface of the adhesion portion. A molding resin contacts a lower surface of the adhesion portion and seals the electronic component and the wiring board that are exposed from the enclosing frame.Type: ApplicationFiled: June 1, 2012Publication date: December 13, 2012Applicant: Shinko Electric Industries Co., Ltd.Inventors: Masayuki FUSE, Satoshi MATSUZAWA
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Publication number: 20120306038Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: STATS CHIPPAC, LTD.Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing
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Publication number: 20120299141Abstract: An avalanche photodiode including a semiconductor substrate of a first conductivity type, an avalanche multiplication layer, an electric field control layer, a light absorption layer, and a window layer wherein the layers are laid one on another in this order on a major surface of the semiconductor substrate, an impurity region of a second conductivity type in a portion of the window layer, and a straight electrode on the impurity region and connected to the impurity region, the straight electrode being straight as viewed in a plan view facing the major surface of the semiconductor substrate.Type: ApplicationFiled: December 15, 2011Publication date: November 29, 2012Applicant: Mitsubishi Electric CorporationInventors: Yoshifumi Sasahata, Masaharu Nakaji
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Patent number: 8314469Abstract: An image sensor structure and a method for making the image sensor structure, for avoiding or mitigating lens shading effect. The image sensor structure includes a substrate, a sensor array disposed at the surface of the substrate, a dielectric layer covering the sensor array, wherein the dielectric layer includes a top surface having a dishing structure, an under layer filled into the dishing structure and having a refraction index greater than that of the dielectric layer, a filter array disposed on the under layer corresponding to the sensor array, and a microlens array disposed above the filter array. A top layer may be additionally disposed to cover the filter array and the microlens array is disposed on the top layer.Type: GrantFiled: September 4, 2009Date of Patent: November 20, 2012Assignee: United Microelectronics Corp.Inventor: Cheng-Hung Yu
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Publication number: 20120273908Abstract: Disclosed herein is a stacked chip package including an image sensor including a recess formed on a surface thereof, and a digital signal processor chip that is positioned within the recess. Also disclosed herein is a method of fabricating a stacked chip package including the steps of forming a recess on a surface of an image sensor and positioning a digital signal processor in the recess of the image sensor.Type: ApplicationFiled: January 18, 2012Publication date: November 1, 2012Applicant: APTINA IMAGING CORPORATIONInventors: LARRY KINSMAN, YU TE HSIEH
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Patent number: 8294177Abstract: A light emitting device (1) includes a LED chip (10) as well as a mounting substrate (20) on which the LED chip (10) is mounted. Further, the light emitting device (1) includes a cover member (60) and a color conversion layer (70). The cover member (60) is formed to have a dome shape and is made of a translucency inorganic material. The color conversion layer (70) is formed to have a dome shape and is made of a translucency material (such as, a silicone resin) including a fluorescent material excited by light emitted from the LED chip (10) and emitting light longer in wavelength than the light emitted from the LED chip (10). The cover member (60) is attached to the mounting substrate (20) such that there is an air layer (80) between the cover member (60) and the mounting substrate (20). The color conversion layer (70) is superposed on a light-incoming surface or a light-outgoing surface of the cover member (60).Type: GrantFiled: December 5, 2008Date of Patent: October 23, 2012Assignee: Panasonic CorporationInventors: Keiichi Yamazaki, Naoko Takei, Tomoyuki Nakajima
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Patent number: 8288770Abstract: A solid-state imaging device is disclosed. In the solid-state imaging device, plural unit areas, each having a photoelectric conversion region converting incident light into electric signals are provided adjacently, in which each photoelectric conversion region is provided being deviated from the central position of each unit area to a boundary position between the plural unit areas, a high refractive index material layer is arranged over the deviated photoelectric conversion region, and a low refractive index material layer is provided over the photoelectric conversion regions at the inverse side of the deviated direction being adjacent to the high refractive index material layer, and optical paths of the incident light are changed by the high refractive index material layer and the low refractive index material layer, and the incident light enters the photoelectric conversion region.Type: GrantFiled: December 24, 2009Date of Patent: October 16, 2012Assignee: Sony CorporationInventors: Hideo Kido, Hiroaki Ishiwata
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Patent number: 8283555Abstract: A solar power generation system includes a plurality of individual modules, each formed from a photovoltaic cell, a solar concentrator, a sealed evaporative cooling system and a heat sink. The solar concentrator focuses sunlight onto a front side the cell to generate electricity. The cooling system circulates a coolant in a liquid state to an evaporative cooling chamber having a wall defined at least partially by a back side of the cell to remove heat from the cell by direct contact between the coolant and the cell, and emits coolant in a vapor state to a condenser where the vapor coolant is condensed to a liquid state. The heat sink may be any suitable body of water, such that the condenser may be at least partially submerged therein. The modules are combined to form a platform that is rotated on the body of water by a drive device to provide tracking of the sun.Type: GrantFiled: June 23, 2009Date of Patent: October 9, 2012Assignee: Solaris Synergy Ltd.Inventors: Yuri Kokotov, Michael A. Reyz, Joseph Fisher
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Patent number: 8274034Abstract: The invention relates to optical arrangements which can be provided, preferably also in miniaturized form, for the most varied applications. They can be used in many sectors of life and also commercially, and indeed whenever information should be presented visually and/or optical information should be recognized and taken into account. It is the object of the invention to provide optical arrangements with which different optical information can be utilized in more complex form together in one arrangement. The optical arrangement in accordance with the invention is configured such that elements both emitting and detecting electromagnetic radiation are arranged on a common substrate or are configured thereat. A plurality of these elements are preferably present together in each case. It can, however, also be sufficient for specific applications to provide in each case an emitting or a detecting element with a plurality of the respective other elements.Type: GrantFiled: June 14, 2007Date of Patent: September 25, 2012Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.Inventors: Uwe Vogel, Jorg Amelung, Daniel Kreye
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Patent number: 8269300Abstract: A packaged image sensor assembly utilizes a spacer paste to control the height of a transparent window above an image sensor die to provide safe wire bond clearance. A dam structure is used to control the height of the transparent window. The dam may be formed either entirely from spacer paste or by depositing the spacer paste on an underlying patterned mesa. An additional encapsulant is provided outside of the dam to encapsulate wirebonds and provide additional protection from moisture permeation.Type: GrantFiled: April 29, 2008Date of Patent: September 18, 2012Assignee: OmniVision Technologies, Inc.Inventors: Yeh-An Chien, Wei-Feng Lin
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Patent number: 8269301Abstract: Submounts for mounting optical devices which have an excellent heat radiating property and can be formed in a wafer state in batch are provided. A metallized electrode including optical device mounting parts and wiring parts is formed on a surface of a first substrate containing an insulating material as a main component, a through hole is formed in a glass substrate serving as a second substrate, the optical device mounting parts of the first substrate are aligned to be located inside the through hole of the second substrate, and the first substrate and the second substrate are joined together by use of a method such as anodic bonding.Type: GrantFiled: April 4, 2007Date of Patent: September 18, 2012Assignee: Hitachi Kyowa Engineering Co., Ltd.Inventors: Shohei Hata, Eiji Sakamoto, Naoki Matsushima, Hideaki Takemori, Masatoshi Seki
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Patent number: 8265432Abstract: An optical module. The optical module includes an opto-chip. The opto-chip includes an integrated circuit with optical windows and a plurality of optoelectronic devices positioned in alignment with the optical windows. The plurality of optoelectronic devices are flip chip attached to the integrated circuit.Type: GrantFiled: March 10, 2008Date of Patent: September 11, 2012Assignee: International Business Machines CorporationInventors: Fuad Elias Doany, Clint Lee Schow
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Patent number: 8253154Abstract: A lens for a light emitting diode package and a light emitting diode package having the same have simple structures and increase light extraction efficiency by preventing light emitted from a light emitting diode chip from being internally reflected by a lens surface through a structural change in the lens surface.Type: GrantFiled: October 28, 2009Date of Patent: August 28, 2012Assignee: Samsung Led Co., Ltd.Inventors: Soo Jin Jung, Joong Kon Son, Gwan Su Lee
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Publication number: 20120212637Abstract: A solid-state imaging apparatus, comprising: a semiconductor chip having a principal face including a pixel region; a protruding portion disposed on the principal face to surround the pixel region; a cover member disposed over the pixel region; and an adhesive material surrounding the pixel region and bonding the cover member and the protruding portion, is provided. The protruding portion has top and first side faces facing the space, a first edge line being formed by this two faces. The adhesive material bonds the top face of the protruding portion and the cover member. The adhesive material has a first face facing the interior space, and the first face extends from the first edge line toward the cover member. Perimeters of the interior space, in planes parallel to the principal face become shorter in a direction from the top face of the protruding portion toward the cover member.Type: ApplicationFiled: January 27, 2012Publication date: August 23, 2012Applicant: CANON KABUSHIKI KAISHAInventors: Koji Tsuduki, Takanori Suzuki, Hisatane Komori, Satoru Hamasaki
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Patent number: 8243443Abstract: A filter 101 of the present application has flexibility. The filter 101 includes a left protruding portion 102, a right protruding portion 103, a lower protruding portion 104a, a lower protruding portion 104b, and an upper protruding portion 105. The electronic equipment of the present application includes a main portion 2 and a display portion 3. The display portion 3 includes a left groove 11a, a right groove 11b, a lower groove 12a, and a lower groove 12b. The left protruding portion 102 can be inserted in the left groove 11a. The right protruding portion 103 can be inserted in the right groove 11b. The lower protruding portion 104a can be inserted in the lower groove 12a. The lower protruding portion 104b can be inserted in the lower groove 12b. When the filter 101 is mounted on the display portion 3, the upper protruding portion 105 is positioned on the display frame 9.Type: GrantFiled: August 31, 2010Date of Patent: August 14, 2012Assignee: Panasonic CorporationInventors: Shintaro Tanaka, Akira Iwamoto
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Publication number: 20120181648Abstract: Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.Type: ApplicationFiled: March 26, 2012Publication date: July 19, 2012Inventors: PAUL S. ANDRY, John M. Cotte, John U. Knickerbocker, Cornelia K. Tsang
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Publication number: 20120175721Abstract: Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.Type: ApplicationFiled: January 18, 2012Publication date: July 12, 2012Applicant: PROMERUS LLCInventors: Chris Apanius, Robert A. Shick, Hendra Ng, Andrew Bell, Wei Zhang, Phil Neal
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Publication number: 20120161271Abstract: A semiconductor device having a substrate including a photodiode; a resin layer formed on an upper surface of the substrate, the resin layer not covering a light receiving region of the photodiode, the resin layer including at least one groove surrounding the light receiving region; and a molding resin portion formed by mold-sealing the photodiode with the resin layer thereon so as not to cover the light receiving region.Type: ApplicationFiled: February 29, 2012Publication date: June 28, 2012Applicant: SONY CORPORATIONInventors: Shuji Yoneda, Masato Oishi, Tamotsu Shinohara, Shinji Watanabe, Koji Miyata, Seiji Fukae, Kenji Yamauchi, Yoichi Goto, Masakazu Baba
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Patent number: 8198120Abstract: An optical article and method of making the same are provided. The optical article has optical multi-aperture operation. The optical article has one or more electrically conductive and selectively passivated patterns.Type: GrantFiled: January 28, 2009Date of Patent: June 12, 2012Assignee: Rohm and Haas Electronic Materials LLCInventors: Jitendra S. Goela, Michael A. Pickering, Neil D. Brown, Angelo Chirafisi, Mark Lefebvre, Jamie L. Triba