With Particular Electrode Configuration Patents (Class 257/448)
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Patent number: 7265381Abstract: A memory cell for opto-electronic applications includes a substrate, a first electrode and a second electrode, and an active layer arranged between the first and the second electrodes, wherein the active layer includes a metalloporphyrin derivative, and wherein the second electrode is transparent and includes ZnO, which is doped with B, Al, Ga, or Mg.Type: GrantFiled: December 30, 2004Date of Patent: September 4, 2007Assignee: Infineon Technologies, AGInventor: Klaus Ufert
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Publication number: 20070200192Abstract: A photovoltaic apparatus includes a first photoelectric conversion portion so formed on an insulating surface of a substrate as to cover a first substrate electrode and a second substrate electrode isolated from each other by a first groove, a second photoelectric conversion portion formed on the surface of the first photoelectric conversion portion through a conductive intermediate layer, a first back electrode and a second back electrode formed on the surface of said second photoelectric conversion portion and a connecting passage portion for electrically connecting the first substrate electrode and the second back electrode, provided at a prescribed interval from the side surface of said intermediate layer.Type: ApplicationFiled: February 20, 2007Publication date: August 30, 2007Applicant: Sanyo Electric Co., Ltd.Inventor: Mataru Shinohara
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Patent number: 7224009Abstract: An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output transistor. The doped polysilicon contact line in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a doped polysilicon contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.Type: GrantFiled: May 13, 2005Date of Patent: May 29, 2007Assignee: Micron Technology, Inc.Inventor: Howard E. Rhodes
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Patent number: 7220986Abstract: A NTCDA single crystal is used as a photoelectric current multiplier layer, and Au thin films are formed as electrodes on the opposite surfaces of the multiplier layer by a vapor deposition method to form a sandwich type cell. When a voltage is applied to the NTCDA single crystal by the electrodes from a dc power source and a monochromatic light is applied, a multiplied photoelectric current flows between the electrodes. A rise of this element at light-on is considerably faster than when a vapor-deposited layer is used as a photoelectric current multiplier layer to permit a faster response.Type: GrantFiled: July 31, 2002Date of Patent: May 22, 2007Assignee: Japan Science & Technology AgencyInventors: Masahiro Hiramoto, Masaaki Yokoyama
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Patent number: 7214999Abstract: An exemplary system and method for providing an integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS host wafer (460) bonded with a monocrystalline, optically active donor wafer (300); a photosensing element (390) integrated in said optically active donor wafer (300) having an interconnect via (505, 495, 485) substantially decoupled from the photosensing element (390), wherein the host (460) and donor (300) wafers are bonded through the optically active material in a region disposed near a metalization surface (450, 455, 445) of the CMOS layer (460) in order to allow fabrication of the interconnect (505, 495, 485). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics.Type: GrantFiled: August 26, 2004Date of Patent: May 8, 2007Assignee: Motorola, Inc.Inventors: Paige Holm, Jon J. Candelaria
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Patent number: 7187052Abstract: A primary object of the present invention is to provide a photoelectric conversion apparatus with less leak current in a floating diffusion region. In order to obtain the above object, a photoelectric conversion apparatus according to the present invention includes a photodiode for converting light into a signal charge, a first semiconductor region having a first conductivity type, a floating diffusion region formed from a second semiconductor region having a second conductivity type for converting the signal charge generated by the photodiode into a signal voltage, the second semiconductor region being formed in the first semiconductor region, and an electrode formed above the first semiconductor region through an insulating film and having an effect of increasing a concentration of majority carriers in the first semiconductor region, in which the electrode is not formed above a depletion region formed from the second semiconductor region.Type: GrantFiled: October 25, 2004Date of Patent: March 6, 2007Assignee: Canon Kabushiki KaishaInventors: Akira Okita, Katsuhito Sakurai, Hiroki Hiyama, Hideaki Takada
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Patent number: 7184193Abstract: A micro-electro mechanical system includes a flexure, wherein the flexure is made of an amorphous material. Similarly, a method for forming a micro-electro mechanical system includes forming a substrate, and forming an amorphous flexure, the amorphous flexure being coupled to the substrate.Type: GrantFiled: October 5, 2004Date of Patent: February 27, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: James McKinnell, Arthur R. Piehl, James R. Przybyla
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Patent number: 7180064Abstract: An optical sensor package with a substrate that supports a membrane carrying an optical sensor and through which radiation passes to impinge the sensor. The substrate has a first surface in which a cavity is defined, a second surface opposite the first surface, and a wall between the cavity and the second surface. The optical sensor is supported on the membrane, which is bonded to the substrate and spans the cavity in the substrate. A window is defined at the second surface of the substrate for enabling infrared radiation to pass through the wall of the substrate to the optical sensor.Type: GrantFiled: June 29, 2004Date of Patent: February 20, 2007Assignee: Delphi Technologies, Inc.Inventors: Han-Sheng Lee, Dan W. Chilcott, James H. Logsdon
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Patent number: 7176532Abstract: An active pixel sensor which provides reduced dark current, improved sensitivity, and improved modulation transfer function. An N well, surrounded by a P well is formed in a P type epitaxial substrate. A P+ region is formed extending from within the P well into the substrate leaving a gap between the P+ region and the N well. A gate dielectric is formed covering at least the gap, part of the P+ region, and part of the N well. A gate electrode is formed on the gate dielectric over the gap, part of the P+ region, and part of the N well. The gate electrode is biased so that the region of the substrate under the gate electrode is accumulated with holes and the region of the N well under the gate electrode is depleted of electrons. This will reduce the dark current and improve the sensitivity of the active pixel sensor.Type: GrantFiled: January 14, 2005Date of Patent: February 13, 2007Assignee: Dialog Semiconductor GmbHInventor: Taner Dosluoglu
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Patent number: 7173295Abstract: An improved photoconductive semiconductor switch comprises multiple-line optical triggering of multiple, high-current parallel filaments between the switch electrodes. The switch can also have a multi-gap, interdigitated electrode for the generation of additional parallel filaments. Multi-line triggering can increase the switch lifetime at high currents by increasing the number of current filaments and reducing the current density at the contact electrodes in a controlled manner. Furthermore, the improved switch can mitigate the degradation of switching conditions with increased number of firings of the switch.Type: GrantFiled: June 16, 2003Date of Patent: February 6, 2007Assignee: Sandia CorporationInventors: Alan Mar, Fred J. Zutavern, Guillermo Loubriel
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Patent number: 7157742Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.Type: GrantFiled: March 11, 2003Date of Patent: January 2, 2007Assignee: Tessera Technologies Hungary Kft.Inventor: Avner Badehi
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Patent number: 7148551Abstract: A semiconductor energy detector includes a semiconductor substrate comprised of a semiconductor of a first conductivity type, into which an energy ray of a predetermined wavelength range is incident from an incident surface thereof. A semiconductor energy detector includes a plurality of diffusion regions of a second conductivity type comprised of a semiconductor of a second conductivity type and a diffusion region of the first conductivity type comprised of a semiconductor of the first conductivity type higher in impurity concentration than the semiconductor substrate. The diffusion regions of a second conductivity type and the diffusion region of the first conductivity type are provided on a surface opposite to the incident surface of said semiconductor substrate. Each first conductivity type semiconductor substrate side of pn junctions, formed at the area of interface between the semiconductor substrate and each of the diffusion regions of the second conductivity type, is commonly connected.Type: GrantFiled: October 3, 2002Date of Patent: December 12, 2006Assignee: Hamamatsu Photonics K.K.Inventors: Yasuhito Yoneta, Hiroshi Akahori, Masaharu Muramatsu
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Patent number: 7135750Abstract: A photodiode array includes a first photodiode and at least a second photodiode. The first photodiode includes a first active area, a first anti-reflective coating area, and a first residual polysilicon ring. The first anti-reflective coating area and the first residual polysilicon ring are formed asymmetrically over the first active area. The second photodiode includes a second active area, a second anti-reflective coating area, and a second residual polysilicon ring. The second anti-reflective coating area and the second residual polysilicon ring are formed asymmetrically over the second active area. The first anti-reflective coating area is formed over a region of the first active region adjacent to the second photodiode, and the second anti-reflective coating area is formed over a region of the second active region adjacent to the first photodiode.Type: GrantFiled: June 2, 2004Date of Patent: November 14, 2006Assignee: Polar Semiconductor, Inc.Inventors: John C. Beckman, Noel P. Hoilien
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Patent number: 7132308Abstract: An organic electroluminescent display device includes first and second substrates facing and spaced apart from each other, the first and second substrates having a plurality of sub-pixel regions, a thin film transistor provided at each of the plurality of sub-pixel regions on an inner surface of the first substrate, a first electrode on an inner surface of the second substrate, an organic electroluminescent layer on the first electrode, a second electrode on the organic electroluminescent layer at each of the plurality of sub-pixel regions, and a connection pattern contacting the thin film transistor and the second electrode, wherein a melting temperature of the connection pattern is lower than a melting temperature of the second electrode.Type: GrantFiled: May 3, 2005Date of Patent: November 7, 2006Assignee: LG.Philips LCD Co., Ltd.Inventors: Jae-Yong Park, Choong-Keun Yoo, Ock-Hee Kim, Nam-Yang Lee, Kwan-Soo Kim
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Patent number: 7129458Abstract: An image pickup device has a plurality of photoelectric converter substrates carrying respective input/output terminals connected to the photoelectric converters. The device comprises leads connected to the input/output terminals and extending to the side opposite to the light receiving surfaces of the photoelectric converter substrates thorough the gaps separating the substrates.Type: GrantFiled: August 24, 2004Date of Patent: October 31, 2006Assignee: Canon Kabushiki KaishaInventors: Osamu Hamamoto, Yoshinori Shimamura, Noriyuki Kaifu, Kazuaki Tashiro, Tetsunobu Kochi, Osamu Yuki, Kenji Kajiwara
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Patent number: 7098520Abstract: A semiconductor memory device includes a first transistor area doped by a first-type dopant for having a plurality of second-type transistors; a second transistor area doped by a second-type dopant for having a plurality of first-type transistors; a first guardring area doped by the first-type dopant between the first and second transistor areas; and a second guardring area doped by the second-type dopant between the first and second transistor areas, wherein the second guardring area runs parallel with the first guardring area in the direction from the first transistor area to the second transistor area.Type: GrantFiled: June 23, 2004Date of Patent: August 29, 2006Assignee: Hynix Semiconductor, Inc.Inventors: Byung-Kwon Park, Kyung-Wook Park
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Patent number: 7038288Abstract: This invention relates to a novel optoelectronic chip with one or more optoelectronic devices, such as photodiodes, fabricated on a front side of a semiconductor wafer and contacts on a backside of the semiconductor wafer. The backside contacts can be contact bumps, which allow the optoelectronic chip to achieve the benefits of flip chip packaging without flipping the optoelectronic chip upside down with respect to a chip carrier. In an optical communication system, a photodiode chip can be backside bumped to a chip carrier or an electronic chip, allowing front side illumination of the photodiode chip. Front side illumination offers many benefits, including improved fiber alignment, reduced manufacturing time, and overall cost reduction.Type: GrantFiled: September 23, 2003Date of Patent: May 2, 2006Assignee: Microsemi CorporationInventors: Jay Jie Lai, Truc Q. Vu, Gary B. Warren
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Patent number: 7034274Abstract: A light receiving device using a new method of controlling sensitivity and a spatial information detecting apparatus using the same technical concept are provided. This light receiving device comprises a photoelectric converter for receiving a light at a light receiving surface and generating amounts of electric charges corresponding to an intensity of received light; electrodes formed on the photoelectric converter; a charge collection area induced in the photoelectric converter by applying a control voltage to the electrodes to collect at least part of the electric charges generated in the photoelectric converter; a charge ejector for outputting the electric charges from the charge collection area; and a sensitivity controller for controlling the number of the electrodes, to which the control voltage is applied, to change size of the charge collection area in the light receiving surface of the photoelectric converter.Type: GrantFiled: June 6, 2003Date of Patent: April 25, 2006Assignee: Matsushita Electric Works, Ltd.Inventors: Yusuke Hashimoto, Yuji Takada, Fumikazu Kurihara
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Patent number: 7026702Abstract: Systems and methodologies for fabrication of a memory cell or array are disclosed. The memory cell employs a functional zone with passive and active layers. Such passive and active layers facilitate electron migration, and allow a plurality of states for the memory cell. A memory device formed in accordance with the disclosed methodology can include a top-electrode formed over the functional layer, which in turn over lays a lower conductive layer.Type: GrantFiled: February 11, 2004Date of Patent: April 11, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Juri Heinrich Krieger, Nikolay Fedorovich Yudanov
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Patent number: 7012314Abstract: A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (D planarizing the top of the device to remove allType: GrantFiled: June 3, 2003Date of Patent: March 14, 2006Assignee: Agere Systems Inc.Inventors: Jeffrey Devin Bude, Malcolm Carroll, Clifford Alan King
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Patent number: 6995445Abstract: The present invention is directed to organic photosensitive optoelectronic devices and methods of use for determining the position of a light source. Provided is an organic position sensitive detector (OPSD) comprising: a first electrode, which is resistive and may be either an anode or a cathode; a first contact in electrical contact with the first electrode; a second contact in electrical contact with the first electrode; a second electrode disposed near the first electrode; a donor semiconductive organic layer disposed between the first electrode and the second electrode; and an acceptor semiconductive organic layer disposed between the first electrode and the second electrode and adjacent to the donor semiconductive organic layer. A hetero-junction is located between the donor layer and the acceptor layer, and at least one of the donor layer and the acceptor layer is light absorbing.Type: GrantFiled: June 25, 2003Date of Patent: February 7, 2006Assignee: The Trustees of Princeton UniversityInventors: Stephen R. Forrest, Barry P. Rand, Michael J. Lange
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Patent number: 6965153Abstract: This invention relates to an electrooptic system array having a plurality of electron lenses. The electrooptic system array includes upper, middle, and lower electrodes arranged along the paths of a plurality of charged-particle beams, the upper, middle, and lower electrodes having pluralities of apertures on the paths of the plurality of charged-particle beams, an upper shield electrode which is interposed between the upper and middle electrodes and has a plurality of shields corresponding to the respective paths of the charged-particle beams, and a lower shield electrode which is interposed between the lower and middle electrodes and has a plurality of shields corresponding to the respective paths of the charged-particle beams.Type: GrantFiled: March 29, 2001Date of Patent: November 15, 2005Assignee: Canon Kabushiki KaishaInventors: Haruhito Ono, Masato Muraki
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Patent number: 6960786Abstract: A display device according to the present invention includes: a planarization layer for insulating between a gate electrode etc. and a data wiring, a drain electrode, or the like of the transistor; and a barrier layer that is formed on an upper surface or lower surface of the planarization layer and at the same time, adapted to suppress diffusion of moisture or degassing components from the planarization layer. The display device adopts a device structure effective in reducing the plasma damage on the planarization layer by devising a positional relationship between the planarization layer and the barrier layer. Also, in combination with a novel structure as a structure for a pixel electrode, effects such as an increase in luminance can be provided as well.Type: GrantFiled: May 1, 2003Date of Patent: November 1, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Murakami, Mitsuaki Osame
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Patent number: 6960817Abstract: A novel solid-state imaging device is provided which has a first color picture cell array containing picture cells having a photo-electric converting element for converting incident light to electric signals arranged two-dimensionally, and a second color picture cell array containing picture cells having a photo-electric converting element for converting incident light to electric signals arranged two-dimensionally, placed in juxtaposition, on a substrate. The solid-state imaging device is characterized in that a common well is provided to be common to the first color picture cell array and the second color picture cell array. A well-wiring and a well-contact may be provided as necessary between the first color picture cell array and the second color picture cell array.Type: GrantFiled: April 19, 2001Date of Patent: November 1, 2005Assignee: Canon Kabushiki KaishaInventors: Masanori Ogura, Hidekazu Takahashi
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Patent number: 6943388Abstract: In the air or in an inert gas atmosphere, powder raw materials are deposited on a flexible sheet for forming a film, an electrode, and a protective film under pressing a heating roller, and a device can be manufactured by continuous operations in which all the steps are integrated. There is provided a cheap device, by which the manhours for manufacturing a device is reduced, the throughput is improved in comparison with those of a previous device by which a film, an electrode, and a protective film have been manufactured on a crystal substrate in a vacuum.Type: GrantFiled: March 18, 2004Date of Patent: September 13, 2005Assignees: National Institute of Advanced Industrial Science and Technology, System Engineers Co., Ltd.Inventors: Yunosuke Makita, Yasuhiko Nakayama, Zhengxin Liu
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Patent number: 6943389Abstract: A solid-state imaging device comprises an image pickup unit having unit cells including opto-electrical converter elements, said unit cells being disposed in a two-dimensional array, a selection line made of polysilicon for selectively determining the unit cells in the same row within the image pickup unit, a read-out line made of polysilicon for reading out an electric charge accumulated in the opto-electrical converter elements of the unit cells in the same row within the image pickup unit, a signal line transmitting pixel signals produced from the unit cells in the same row within the image pickup unit, a reset line made of polysilicon for discharging the unit cells in the same row within the image pickup unit down to a desired voltage level, a driver circuit located on one side of the image pickup unit for supplying drive signals to the read-out line, the selection line, and the reset line, respectively, and a read-out auxiliary wiring disposed along at least the read-out line and electrically connected tType: GrantFiled: September 25, 2003Date of Patent: September 13, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Yamaguchi, Ryohei Miyagawa, Yoshitaka Egawa
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Patent number: 6940142Abstract: The signal-to-noise ratio of amorphous silicon (a-Si:H) image sensor arrays is limited by electronic noise, which is largely due to data line capacitance. To reduce data line capacitance, an air-gap (i.e., vacuum or gas-filled space) is produced at crossover points separating the data lines and gate lines. This air-gap crossover structure is formed by depositing a release material on the gate lines, forming the data lines on the release material, and then removing (etching) the release material such that the data lines form an arch extending over the gate lines. A dielectric material is then applied to strengthen the data line, and the sensor pixels are then formed.Type: GrantFiled: July 2, 2001Date of Patent: September 6, 2005Assignee: Xerox CorporationInventors: Robert A. Street, Ping Mei, Jeffrey T. Rahn
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Patent number: 6940552Abstract: To read stable image information by making small in a short time the amount of change in potential at the time the potential of signal wires or sensor bias wires drops a moment, the device is, in the refresh mode of photoelectric conversion pixels, so driven that the timing at which two drive wires are driven overlaps which are sequentially and at least consecutively driven by the control means among drive wires while keeping the signal wires at a reset potential.Type: GrantFiled: August 31, 2000Date of Patent: September 6, 2005Assignee: Canon Kabushiki KaishaInventors: Isao Kobayashi, Noriyuki Kaifu, Toshikazu Tamura, Tomoyuki Yagi
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Patent number: 6940094Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.Type: GrantFiled: May 23, 2002Date of Patent: September 6, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Teramoto
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Patent number: 6930299Abstract: Pixels are disposed on a semiconductor substrate in a matrix shape. Each pixel includes a photodiode, a reset transistor, a source follower transistor and a select transistor. An active region in which the photodiode and transistors are disposed includes a first area in which the photodiode is disposed and a second area having an are elongated in a first direction. Each of the gate electrodes of the reset transistor, source follower transistor and select transistor crosses the area, elongated in the first direction, of the second area. An intra-pixel wiring line interconnects the drain region of the reset transistor and the gate electrode of the source follower transistor.Type: GrantFiled: August 27, 2003Date of Patent: August 16, 2005Assignee: Fujitsu LimitedInventor: Narumi Ohkawa
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Patent number: 6909461Abstract: An image capture system generates an extended effective dynamic range from a signal provided by an image sensor by utilizing an image sensing device having standard photosites with a predetermined response to a light exposure and non-standard photosites with a slower response to the same light exposure. An optical section exposes the image sensing device to image light, thereby causing the image sensing device to generate an image signal and a processing section expands the response of the standard photosites to increased light exposures by utilizing the image signals from neighboring non-standard photosites. Furthermore, the processing section may expand the response of the non-standard photosites to decreased light exposures by utilizing the image signals from neighboring standard photosites.Type: GrantFiled: July 13, 2000Date of Patent: June 21, 2005Assignee: Eastman Kodak CompanyInventors: Andrew C. Gallagher, David N. Nichols
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Patent number: 6900475Abstract: A method for fabricating a surface-emission semiconductor laser on a p-type substrate includes the step of interposing an Au film between an AuGeNi film or AuGe film of an n-side electrode and a compound semiconductor layer of an n-type DBR, followed by annealing to form an Au alloy in the n-side electrode. The presence of the Au alloy film improves the adherence between the n-side electrode and the compound semiconductor layer to improve an injection current vs. applied voltage characteristic.Type: GrantFiled: September 19, 2002Date of Patent: May 31, 2005Assignee: The Furukawa Electric Co., Ltd.Inventors: Noriyuki Yokouchi, Norihiro Iwai
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Patent number: 6876019Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.Type: GrantFiled: November 29, 2002Date of Patent: April 5, 2005Assignee: Canon Kabushiki KaishaInventor: Mahito Shinohara
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Patent number: 6867469Abstract: There is provided a photoelectric converter comprising a photoelectric conversion element of a laminated structure comprising a first electrode layer, an insulation layer for blocking the passage of a first carrier and a second carrier, a photoelectric conversion semiconductor layer, an injection blocking layer for blocking the injection of the first carrier to the photoelectric conversion semiconductor layer, and a second electrode layer, wherein a switching means is provided for operating the converter by switching the following three operation modes a) through c) for applying an electric field to each layer of the photoelectric conversion element; a) an idling mode for emitting the second carrier from the photoelectric conversion element, b) a refreshment mode for refreshing the first carrier accumulated in the photoelectric conversion element, and c) a photoelectric conversion mode for generating pairs of the first carrier and the second carrier in accordance with an amount of incident light to accumulateType: GrantFiled: April 27, 2001Date of Patent: March 15, 2005Assignee: Canon Kabushiki KaishaInventors: Isao Kobayashi, Noriyuki Kaifu
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Patent number: 6849917Abstract: In a photovoltaic element obtained by forming an ITO film, that is a transparent conductive film, on a semiconductor layer composed of an n-type silicon wafer, an i-type amorphous silicon hydride layer and a p-type amorphous silicon hydride layer, the ITO film has an interface layer as an alkali diffusion prevention region on a side adjacent to the semiconductor layer, and a bulk layer layered on the interface layer. The crystallinity of the interface layer is made lower than that of the bulk layer by changing the water partial pressure when forming the interface layer and the bulk layer.Type: GrantFiled: March 17, 2003Date of Patent: February 1, 2005Assignee: Sanyo Electric Co., Ltd.Inventor: Eiji Maruyama
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Patent number: 6846695Abstract: A solid-state imaging device of the present invention includes a vertical charge transfer portion and a horizontal charge transfer portion that is connected to at least one end of the vertical charge transfer portion. The vertical charge transfer portion includes a vertical transfer channel region and a plurality of vertical transfer electrodes formed on the vertical transfer channel region. The horizontal charge transfer portion includes a horizontal transfer channel region, a plurality of first horizontal transfer electrodes formed on the horizontal transfer channel region, and a plurality of second horizontal transfer electrodes arranged between the plurality of first horizontal transfer electrodes. A potential below the first horizontal transfer electrode is higher than a potential below the second horizontal transfer electrode that is arranged adjacent to the first horizontal transfer electrode and backward along a transfer direction with respect to the first horizontal transfer electrode.Type: GrantFiled: February 27, 2003Date of Patent: January 25, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Tooru Yamada
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Patent number: 6838742Abstract: A multiple-trench photosensor for use in a CMOS imager having an improved charge capacity. The multi-trench photosensor may be either a photogate or photodiode structure. The multi-trench photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The multi-trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the multi-trench photosensor.Type: GrantFiled: February 27, 2004Date of Patent: January 4, 2005Assignee: Micron Technology, Inc.Inventor: Howard E. Rhodes
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Patent number: 6835991Abstract: A method and apparatus for creating objects on a semiconductor wafer includes a mask/reticle having a substantially uniform pattern of features. The wafer is illuminated through the mask/reticle to create a corresponding uniform pattern of objects on the wafer. Selected objects created by the uniform pattern of features are then utilized to provide desired electrical functions on the integrated circuit. In one embodiment of the invention, the objects are interconnect wires formed by a mask or reticle having a substantially uniform pattern of strips that extends over an area of the integrated circuit. Interconnect wires of different lengths are created by defining endpoints on the strips or by exposing areas on the wafer corresponding to the endpoints of the wires.Type: GrantFiled: November 7, 2002Date of Patent: December 28, 2004Inventor: Edwin A. Pell, III
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Patent number: 6822306Abstract: The reduction in size, noise and voltage is realized in a MOS solid-state imaging device. A gate electrode in a pixel part is formed in a two-level structure. An amplifier gate of an amplifier transistor is formed in the first level while a select gate of a select transistor is formed in the second level. The both are structurally partly overlapped. With the first-level amplifier gate as self-alignment, ions are implanted for a select gate in the second level. Although the gate electrode if formed in one level as in the conventional requires a space of nearly a design rule between the amplifier gate and the select gate, the structure of the invention can eliminate such a dead space. Meanwhile, because the diffusion layer does not exist between the amplifier gate and the select gate, the diffusion layer is eliminated of sheet resistance and voltage drop.Type: GrantFiled: September 16, 2002Date of Patent: November 23, 2004Assignee: Sony CorporationInventor: Keiji Mabuchi
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Patent number: 6822296Abstract: A complementary metal-oxide semiconductor (CMOS) structure for a battery protection circuit and a battery protection circuit therewith. A tri-well technique or a buried layer technique is used for such CMOS structure to allow the battery protection circuit therewith to operate at different low voltage levels. Thereby, low voltage process can be realized to effectively reduce the cost of the chip and simplify the design.Type: GrantFiled: April 24, 2003Date of Patent: November 23, 2004Assignee: TOPRO Technology, Inc.Inventor: Chi-Chang Wang
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Patent number: 6806454Abstract: Image sensors are provided that reduce conflicts between different sensor functions because sensor structures do not demand access to the same internal spaces. Accordingly, sensor structures can be independently arranged to enhance their respective functions. In particular, sensor embodiments include a substrate, semiconductor devices and an interconnect structure carried over the substrate, reference and sense electrodes and a photoconductive medium that are carried over the interconnect structure, and vias that couple the reference and sense electrodes to the interconnect structure and semiconductor devices. Different sensor elements do not demand access through the same internal VLSI spaces and may thus be arranged to enhance their respective sensor functions. In addition, sensors of the invention will respond to radiation rays that are orthogonal to the sensor's upper face and also to radiation rays that are tilted from this relationship.Type: GrantFiled: May 31, 2002Date of Patent: October 19, 2004Assignee: Analog Devices, Inc.Inventor: Kenneth Carl Zemlok
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Patent number: 6800836Abstract: An image pickup device has a plurality of photoelectric converter substrates carrying respective input/output terminals connected to the photoelectric converters. The device comprises leads connected to the input/output terminals and extending to the side opposite to the light receiving surfaces of the photoelectric converter substrates thorough the gaps separating the substrates.Type: GrantFiled: July 9, 2001Date of Patent: October 5, 2004Assignee: Canon Kabushiki KaishaInventors: Osamu Hamamoto, Yoshinori Shimamura, Noriyuki Kaifu, Kazuaki Tashiro, Tetsunobu Kochi, Osamu Yuki, Kenji Kajiwara
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Patent number: 6798030Abstract: In a two-dimensional image detecting device, an active-matrix substrate and an opposing substrate are bonded to each other via conductive connecting members and space keeping members, that are disposed respectively for pixels, such that pixel electrodes and electrical charge collecting electrodes oppose each other. The pixel electrodes are formed on the active-matrix substrate, and the electrical charge collecting electrodes are formed on the opposing substrate. Further, when a resin material of the space keeping members is soft, reinforcing members, which have electrical insulation and are hardly deformed in a thermocompression bonding, are dispersed into the resin material, so that the space keeping ability is fully exhibited. According to this arrangement, it is possible to improve the responsivity so as to respond to a moving image. Additionally, an even space can be achieved between the substrates, and it is possible to prevent a connecting defect and a defect caused by a leak between the substrates.Type: GrantFiled: December 13, 1999Date of Patent: September 28, 2004Assignee: Sharp Kabushiki KaishaInventors: Yoshihiro Izumi, Osamu Teranuma
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Photoconductor-on-active-pixel (POAP) sensor utilizing a multi-layered radiation absorbing structure
Patent number: 6798033Abstract: An active pixel sensor for producing images from electron-hole producing radiation includes a crystalline semiconductor substrate having an array of electrically conductive diffusion regions, an interlayer dielectric (ILD) layer formed over the crystalline semiconductor substrate and comprising an array of contact electrodes, and an interconnect structure formed over the ILD layer, wherein the interconnect structure includes at least one layer comprising an array of conductive vias. An array of patterned metal pads is formed over the interconnect structure and are electrically connected to an array of charge collecting pixel electrodes. A radiation absorbing structure includes a photoconductive N-I-B-P photodiode layer formed over the interconnect structure, and a surface electrode layer establishes an electrical field across the radiation absorbing structure and between the surface electrode layer and each of the array of charge collecting pixel electrodes.Type: GrantFiled: August 27, 2002Date of Patent: September 28, 2004Assignee: e-Phocus, Inc.Inventors: Calvin Chao, Tzu-Chiang Hsieh, Michael Engelmann, Milam Pender -
Patent number: 6798034Abstract: A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.Type: GrantFiled: August 7, 2002Date of Patent: September 28, 2004Assignee: Diglrad CorporationInventor: Lars S. Carlson
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Patent number: 6794725Abstract: A hybrid structure or device is provided wherein carried on a single substrate is at least one micro-spring interconnect having an elastic material that is initially fixed to a surface of the substrate, an anchor portion which is fixed to the substrate surface and a free portion. The spring contact is self-assembling in that as the free portion is released it moves out of the plane of the substrate. Also integrated on the substrate is a sensor having an active layer and contacts. The substrate and sensor may be formed of materials which are somewhat partially transparent to light at certain infrared wavelengths. The integrated sensor/spring contact configuration may be used in an imaging system to sense output from a light source which is used for image formation. The light source may be a laser array, LED array or other appropriate light source. The sensor is appropriately sized to sense all or some part of light from the light source.Type: GrantFiled: December 21, 1999Date of Patent: September 21, 2004Assignee: Xerox CorporationInventors: Francesco Lemmi, Christopher L. Chua, Ping Mei, JengPing Lu, David K. Fork, Harry J. McIntyre
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Patent number: 6781211Abstract: Disclosed is a photodiode with improved light-receiving efficiency and coupling effect with an optical fiber, whose capacitance may be decreased. The inventive photodiode includes a substrate; a buffer layer and a light-absorbing layer laminated in sequence on the substrate; an epitaxial layer formed on the upper surface of the light absorbing layer and having an active region with a surface in a convex lens shape so that it has greater surface area and more effective light-receiving area than an active region defined in a two-dimensional plane, the active region further having a convex surface can harvest light with its convex-lens characteristics; a dielectric layer formed on the upper surface of the epitaxial layer; a first metal electrode formed on an upper surface of the dielectric layer; and, a second metal electrode formed on an under surface of the substrate.Type: GrantFiled: January 17, 2003Date of Patent: August 24, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Hwa-Young Kang, Jung-Kee Lee
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Patent number: 6777769Abstract: A light-receiving element, comprises an absorption layer formed on a semiconductor substrate, a window layer formed on the absorption layer, a first electrode formed on the window layer, a second electrode formed on the window layer and electrically connected to the first electrode, and a diffusion region which is formed in the absorption layer and the window layer and is formed between the first electrode and the substrate and between the second electrode and the substrate.Type: GrantFiled: November 5, 2002Date of Patent: August 17, 2004Assignee: The Furukawa Electric Co., Ltd.Inventors: Takeshi Higuchi, Naoki Tsukiji
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Patent number: 6765281Abstract: A semiconductor apparatus includes a MOS transistor and a resistive element having insulative first polysilicon and conductive second polysilicon films, an insulating film for a resistive element, and a third polysilicon film. The second polysilicon film is formed in a region adjacent each side edge of the first polysilicon film, and has a contact hole formed therein. The third polysilicon film determines a resistance value of the resistive element, and is continuously formed on the second polysilicon film and the insulating film formed on the first polysilicon film. The MOS transistor is formed in an active region surrounded by the field insulating film, and includes a gate oxide film and a gate electrode including a polysilicon film formed as a lower layer with the second polysilicon film and a polysilicon film formed as an upper layer with the third polysilicon film. A method of making this semiconductor apparatus is also described.Type: GrantFiled: November 27, 2002Date of Patent: July 20, 2004Assignee: Ricoh Company, Ltd.Inventor: Junichi Konishi
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Patent number: RE38582Abstract: A multi-layer Auger suppressed diode having at least two exclusion interfaces and at least two extraction interfaces. A specific embodiment has two composite contacts, each consisting of a heavily doped layer (3, 4) and a buffer layer (8, 9) of lower doped, high bandgap material sandwiched between the heavily doped layer and the active region (2) of the device.Type: GrantFiled: June 26, 2002Date of Patent: September 14, 2004Assignee: QinetiQ LimitedInventor: Anthony M. White