With Particular Electrode Configuration Patents (Class 257/448)
  • Patent number: 6762473
    Abstract: Ultra thin back-illuminated photodiode array structures and fabrication methods. The photodiode arrays are back illuminated photodiode arrays having a substrate of a first conductivity type having first and second surfaces, the second surface having a layer of the first conductivity type having a greater conductivity than the substrate. The arrays also have a matrix of regions of a first conductivity type of a higher conductivity than the substrate extending from the first surface of the substrate to the layer of the first conductivity type having a greater conductivity than the substrate, a plurality of regions of the second conductivity type interspersed within the matrix of regions of the first conductivity type and not extending to the layer of the first conductivity type on the second surface of the substrate, and a plurality of contacts on the first surface for making electrical contact to the matrix of regions of the first conductivity type and the plurality of regions of the second conductivity type.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: July 13, 2004
    Assignee: Semicoa Semiconductors
    Inventors: Alexander O. Goushcha, Chris Hicks, Richard A. Metzler, Mark Kalatsky, Eddie Bartley, Dan Tulbure
  • Patent number: 6756651
    Abstract: A novel photodetector CMOS-compatible photodetector is disclosed in which photo-generation of carriers (electrons) is carried out in the metal of the electrodes, rather than as electron-hole pairs in the semiconductor on which the metal electrodes are deposited. The novel photo detector comprises a silicon or other semiconductor substrate material characterized by an electron energy bandgap, and a pair of metal electrodes disposed upon a surface of the silicon to define therebetween a border area of the surface. One of the two electrodes being exposed to the incident radiation and covering an area of said surface which is larger than the aforesaid border area, the aforesaid metal of the electrodes being characterized by a Fermi level which is within said electron energy bandgap.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: June 29, 2004
    Assignee: International Business Machines Corporation
    Inventors: Ferenc M. Bozso, Fenton Read McFeely, John Jacob Yurkas
  • Patent number: 6753915
    Abstract: A photoelectric conversion apparatus has a plurality of photoelectric conversion elements (photodiodes 4), a plurality of switching elements (TFTs 3) connected to the respective photoelectric conversion elements 4, a plurality of signal lines 5 for outputting electric signals resulting from photoelectric conversion in each of the photoelectric conversion elements 4, and a plurality of driving wires (bias lines 6) for driving the photoelectric conversion elements 4. In the photoelectric conversion apparatus, each of the driving wires 6 is arranged in parallel to the signal lines 5 and between the signal lines 5 and each of the driving wires 6 is located so that a center line thereof lies between a first position at a center between the signal lines 5 and a second position at a center of gravity of an area of the photoelectric conversion element 4, thereby enhancing photosensitivity.
    Type: Grant
    Filed: September 16, 1999
    Date of Patent: June 22, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Chiori Mochizuki
  • Publication number: 20040104446
    Abstract: One method of achieving the above subjects is by connecting a block member 14, which is connected to the side opposite to that of a semiconductor chip 11 having insulating substrates 12 and 13 connected to the top and bottom of the semiconductor chip 11, to a block member 15 across an laminated structure constituted by the semiconductor chip 11 and the insulating substrates 12 and 13.
    Type: Application
    Filed: July 2, 2003
    Publication date: June 3, 2004
    Inventors: Atsuhiro Yoshizaki, Keiichi Mashino, Hiromichi Anan, Yoshitaka Ochiai
  • Publication number: 20040099920
    Abstract: An imager temperature sensor and a current correction apparatus are provided which use dark pixel measurements from an imager chip during operation together with a fabrication process constant as well as a chip dependent constant to calculate chip temperature. The chip temperature may be used to generate a current correction signal. The correction signal is used to tune a current on the imager chip to correct for temperature variations.
    Type: Application
    Filed: November 8, 2002
    Publication date: May 27, 2004
    Inventors: Giuseppe Rossi, Gennadiy A. Agrarov
  • Patent number: 6740807
    Abstract: A differential response light-receiving device comprising: a semiconductor electrode comprising an electrically conductive layer and a photosensitive layer containing a semiconductor sensitized by a dye; an ion-conductive electrolyte layer; and a counter electrode, the differential response light-receiving device making time-differential response to quantity of light to output a photoelectric current. A composite light-receiving device comprising the differential response light-receiving device and a stationary response light-receiving device, and an image sensor using the differential response light-receiving device or the composite light-receiving device are also provided.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: May 25, 2004
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Michio Ono
  • Patent number: 6730208
    Abstract: Chips, and methods of manufacturing thereof, comprising a base having a surface, and a plurality of components integrated in the base. Each component is coupled to at least one individual electrode disposed on the surface and to a counter-electrode. Each component operates as an electric generator, when activated by a power supply external to the chip. The counter-electrode is disposed such that each activated component creates a polarization voltage and/or a polarization current between that at least one individual electrode and the counter-electrode, when a medium is brought into contact with the surface.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: May 4, 2004
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Michel Bruel
  • Patent number: 6724062
    Abstract: A semiconductor energy detector as disclosed herein is arranged so that an aluminum wiring pattern is formed on the front side of transfer electrodes of a CCD vertical shift register, which pattern includes meander-shaped auxiliary wirings for performing auxiliary application/supplement and additional wirings for performing auxiliary supplement of transfer voltages in a way independent of the auxiliary wirings with respective ones of such wirings being connected to corresponding transfer electrodes to thereby avoid a problem as to lead resistivities at those transfer electrodes made of polycrystalline silicon, thus achieving the intended charge transfer at high speeds with high efficiency.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: April 20, 2004
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hiroshi Akahori, Hisanori Suzuki, Kazuhisa Miyaguchi, Masaharu Muramatsu, Koei Yamamoto
  • Patent number: 6724064
    Abstract: A photoelectric conversion element comprising a substrate and a light sensor disposed on a surface of the substrate and receiving high speed optical pulse signals and converting them into high frequency waves in which the light sensor comprises at least carbon nano-tubes, as well as a photoelectric conversion device having the element, for directly converting high speed optical pulses signals in a communication band into signals of high frequency waves or electromagnetic waves.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: April 20, 2004
    Assignee: Fuji-Xerox Co., Ltd.
    Inventors: Hiroyuki Watanabe, Kazunori Anazawa, Chikara Manabe, Masaaki Shimizu
  • Patent number: 6713832
    Abstract: Device for photodetection with a vertical metal semiconductor microresonator and procedure for the manufacture of this device. According to the invention, in order to detect an incident light, at least one element is formed over an insulating layer (2) that does not absorb this light, including a semiconductor material (6) and at least two electrodes (4) holding the element, with the element and electrode unit being suitable for absorbing this light and designed to incease the light intensity with respect to the incident light, in particular by making a surface plasmon mode resonate between the unit interfaces with the layer and the propagation medium for the incident light, with the resonance of this mode taking place in teh interface between the element and atleast one of the electrodes, with this mode being excited by the component of the magnetic field of the light, parallel to the electrodes. Application for optical telecommunications.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: March 30, 2004
    Assignee: Centre National de la Recherche Scientifique
    Inventors: Fabrice Pardo, Stéphane Collin, Roland Teissier, Jean-Luc Pelouard
  • Patent number: 6710370
    Abstract: An image sensor is disclosed including passivation walls extending above the pixel contact pads into a photosensor layer (e.g., amorphous silicon) such that the pixel contact pads are isolated to reduce cross-talk. The passivation walls are formed from SiO2 or SiON to further reduce cross-talk. An embodiment includes metal structures provided under interface regions (e.g., under the passivation walls) separating adjacent pixels that are negatively biased to prevent cross-talk, and optionally extend under the contact pad to increase pixel capacitance. One embodiment omits p-type dopant from the lower amorphous silicon photodiode layer, and additional photodiode material layers are disclosed. Another disclosed sensor structure utilizes a textured surface to increase light absorption. A color filter structure for image sensors is also disclosed.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: March 23, 2004
    Assignee: Xerox Corporation
    Inventors: Robert A. Street, James B. Boyce, John C. Knights
  • Publication number: 20040012064
    Abstract: One method of achieving the above subjects is by connecting one of electroconductive members 12, which are pre-connected to the top and bottom of a semiconductor chip 11 and have thermal conductivity, to an electroconductive member 13, which is used with the semiconductor chip 11 to constitute a laminated structure, in electrically insulated form on the same surface as the installation surface of the electroconductive member 13 so as to straddle the laminated structure constituted by the semiconductor chip 11 and the electroconductive member 13.
    Type: Application
    Filed: July 2, 2003
    Publication date: January 22, 2004
    Inventors: Atsuhiro Yoshizaki, Keiichi Mashino, Hiromichi Anan, Yoshitaka Ochiai
  • Patent number: 6670258
    Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: December 30, 2003
    Assignee: Digirad Corporation
    Inventors: Lars S. Carlson, Shulai Zhao, John Sheridan, Alan Mollet
  • Patent number: 6667528
    Abstract: A photodetector (and method for producing the same) includes a semiconductor substrate, a buried insulator formed on the substrate, a buried mirror formed on the buried insulator, a semiconductor-on-insulator (SOI) layer formed on the conductor, alternating n-type and p-type doped fingers formed in the semiconductor-on-insulator layer, and a backside contact to one of the p-type doped fingers and the n-type doped fingers.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: December 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Guy Moshe Cohen, Kern Rim, Dennis L. Rogers, Jeremy Daniel Schaub, Min Yang
  • Patent number: 6661073
    Abstract: A semiconductor infrared detector includes in the following order: a semiconductor substrate; a layer of electrically insulating material; and patterns formed in a semiconductor layer. The patterns are formed from at least one island that is connected to bridges which are connected to polarization electrodes. The bridges are lines having an approximately constant width lp and the islands are zones having a width li that is greater than that of the lines.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: December 9, 2003
    Assignee: Centre National de la Recherche Scientifique
    Inventors: Didier Stievenard, Christophe Delerue, Bernard Legrand
  • Patent number: 6657230
    Abstract: An electro-optical device such as an active-matrix-driven liquid crystal device is improved to suppress undesirable effects of dents and steps that appear on pixel electrode surfaces due to presence of contact holes that interconnect a semiconductor layer and pixel electrodes through the intermediary of a conductive layer. The liquid crystal device has a TFT array substrate carrying a TFT, data lines, scanning lines, capacitance lines and pixel electrodes. The pixels and TFTs are electrically connected via contact holes through the intermediary of barrier layers. At least each contact hole is formed in a non-aperture region at a position symmetrical with respect to two adjacent data lines.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: December 2, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Masao Murade
  • Patent number: 6653706
    Abstract: A high efficiency optical interconnect (OI) deposited directly on a silicon based IC by a low temperature process that utilizes a heterogeneous crystalline structure of a III-V compound material to convert light pulses into electrical signals. The high efficiency is established by pulsing the light beams with a shorter duration than the life time of the generated carriers and by reducing the structural volume and consequently the internal capacitance of the III-V compound to a functional height of approximately 1 micron. The analog MSM characteristic of the OI is bypassed by differential two-beam signal processing, wherein the intensity difference of two synchronous light beams is transformed in two parallel OI's into two electrical signals that compensate in a central node. The resulting polarity in the node switches either a PMOS or a NMOS transistor, which connect either a positive or negative voltage to the output node.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: November 25, 2003
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: David A. B. Miller, James S. Harris, Jr.
  • Publication number: 20030214006
    Abstract: In the manufacture of a semiconductor device, there are provided a method that enables reduction in the number of manufacturing steps thereof and a structure for realizing the method, to thereby realize improvement in yield and reduction in manufacturing cost. Wirings (source wiring, drain wiring, and the like), which are respectively formed in a row direction and a column direction on an element substrate, are formed of the same conductive film. In this case, one of the respective wirings in the row direction and the column direction is discontinuously formed at a portion where the wirings intersect with each other, and an insulating film is formed on the wirings. Thereafter, a connection wiring for connecting discontinuous wirings is formed of the same film as that for forming an electrode provided on the insulating film. As a result, a continuous wiring is formed.
    Type: Application
    Filed: May 7, 2003
    Publication date: November 20, 2003
    Inventors: Osamu Nakamura, Hideaki Kuwabara, Noriko Shibata
  • Patent number: 6649951
    Abstract: In order to reduce the capacitance of a light-receiving element, the present invention provides a light-receiving element comprises a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, provided on the first semiconductor region, a third semiconductor region of the first conductivity type, provided between the second semiconductor region and an insulating film and an electrode region of the second conductivity type, provided in the second semiconductor region where the third semiconductor region is absent on and above the second semiconductor region, and connected to an anode or cathode electrode consisting of a conductor.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: November 18, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiraku Kozuka, Toru Koizumi, Koji Sawada
  • Patent number: 6646289
    Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: November 11, 2003
    Assignee: Shellcase Ltd.
    Inventor: Avner Badehi
  • Patent number: 6642537
    Abstract: A quantum well infrared photodetector (QWIP) that provides two-color image sensing. Two different quantum wells are configured to absorb two different wavelengths. The QWIPs are arrayed in a focal plane array (FPA). The two-color QWIPs are selected for readout by selective electrical contact with the two different QWIPs or by the use of two different wavelength sensitive gratings.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: November 4, 2003
    Assignee: California Institute of Technology
    Inventors: Sarath D. Gunapala, Kwong Kit Choi, Sumith V. Bandara
  • Patent number: 6639143
    Abstract: A solar cell using a ferroelectric material(s) is provided with a ferroelectric layer at the front surface or the rear surface thereof, or at the front and the rear surfaces thereof. The ferroelectric layer is formed with a ferroelectric material such as BaTiO3, BST((Ba,Sr)TiO3), PZT((Pb,Zr)TiO3) and SBT(SrBi2Ta2O7).
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: October 28, 2003
    Assignee: Samsung SDI Co. Ltd.
    Inventors: Jeong Kim, Dong-Seop Kim, Soo-Hong Lee
  • Patent number: 6639261
    Abstract: An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output transistor. The doped polysilicon contact line in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a doped polysilicon contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: October 28, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 6624492
    Abstract: A semiconductor integrated circuit having gate array area and IP (Intellectual Property) portion. A semiconductor integrated circuit has a lower wiring region and an upper wring region on a semiconductor substrate. A gate array region is on the semiconductor substrate. An IP (Intellectual Property) region comprises a plurality of semiconductor devices formed on the semiconductor substrate and has a predetermined function. A first wiring layer is in the lower layer wiring region above the semiconductor substrate and a second wiring layer is above the IP region. A third wiring layer is in the upper wiring region of the gate array region. The third wiring layer is wider than the first and second wiring layers.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: September 23, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Kaneko, Yoshihisa Tamura
  • Patent number: 6621102
    Abstract: In a pixel structure of an active matrix liquid crystal display device, a common electrode branching out from a common line which is maintained at a specified voltage and a pixel electrode connected to a drain of a thin-film transistor arranged on a common plane are wound around each other in spiral form. Electric fields generally oriented parallel to a substrate are produced between the common electrode and pixel electrode arranged in each pixel on the substrate. These electric fields drive a liquid crystal material to provide a visual display. The pixel electrode is surrounded, or fenced off, by the common electrode in each pixel so that the former is kept unaffected from interference from a nearby gate line and/or source line.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: September 16, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Shunpei Yamazaki
  • Patent number: 6617667
    Abstract: A layout of a carrier in an optical component having the carrier and an optical device is described. The layout comprises a pair of terminals, a resistor connected to a first terminal, a wire bond connected in series with the resistor for connecting the resistor to an optical device, and a first ground patch connected to a second terminal and for connecting to an optical device for providing a common ground on a first surface on a substrate on which the carrier is based, whereby the pair of terminals, the resistor, the wire bond and an optical device form an optical signal transmission system in the optical component.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: September 9, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Institute of Microelectronics
    Inventors: Mui Seng Yeo, Yong Kee Yeo, Mahadevan K. Iyer, Eitaro Ishimura, Gou Sakaino
  • Patent number: 6614575
    Abstract: An optical structure includes a substrate having semiconductor material and a grating structure. The grating structure has the property of emitting at least one frequency band so that light having a frequency from that frequency band cannot propagate in the grating structure. The grating structure has a configuration of pores and a defective region. The pores are disposed outside the defective region in a periodic array, and the periodic array is disturbed in the defective region. A surface of the grating structure is provided with a conductive layer at least in the vicinity of the defective region. A method for producing the optical structure is also provided.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: September 2, 2003
    Assignee: Infineon Technologies AG
    Inventors: Ulrike Grüning, Volker Lehmann, Reinhard Stengl, Hermann Wendt, Hans Reisinger
  • Patent number: 6608299
    Abstract: A photoelectric conversion apparatus is comprised of a light-receiving element having a first semiconductor region of a first conduction type, and a second semiconductor region of a second conduction type for storing a charge generated by photoelectric conversion adjacent to the first semiconductor region, a readout electrode for reading a signal based on the charge stored in the second semiconductor region; and at least a pair of electrode portions spaced from each other along a photoreceptive surface so as to place a photoreceptive portion of the second semiconductor region in between, and connected to the first semiconductor region. Applied to the pair of electrode portions is a voltage that completely depletes the photoreceptive portion of the second semiconductor region and that can create a potential gradient for moving the charge stored in the second semiconductor region, to the readout electrode side.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: August 19, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiraku Kozuka
  • Patent number: 6605488
    Abstract: A technique and structure for simplifying the stitching process is disclosed. According to one aspect of the present system, a floor plan that minimizes the number of blocks for a two-dimensional stitching project is described. Another technique describes a special layout method for a row/column decoder that reduces the number of blocks when stitching.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: August 12, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Anders Andersson
  • Patent number: 6600157
    Abstract: A semiconductor device is provided which comprises a thin film transistor (TFT) comprising a gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, and a pair of electrodes having a semiconductor layer and an ohmic contact layer therebetween; and a gate wiring connected to the gate electrode, and a signal wiring connected to one of the pair of electrodes, wherein the gate wiring and the signal wiring are arranged in superposition in the film thickness direction with an interlayer insulating layer therebetween to have a plurality of crossings with each other and the interlayer insulating layer has a plurality of steps overstriding a lower wiring at the crossings. A radiation detection device and a radiation detection system that have the semiconductor device are also provided.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: July 29, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Minoru Watanabe, Satoshi Okada, Toshiko Koike
  • Publication number: 20030137025
    Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.
    Type: Application
    Filed: January 14, 2003
    Publication date: July 24, 2003
    Inventor: Howard E. Rhodes
  • Patent number: 6580109
    Abstract: Fast and efficient photodiodes with different structures are fabricated using CMOS process technology by adapting transistor structures to form the diode structures. The anode regions of the photodiodes correspond to either PLDD regions of PMOS transistors or P-wells of NMOS transistors to provide two different photodiode structures with different anode region depths and thus different drift region thicknesses. An antireflective film used on the silicon surface of the photodiodes is employed as a silicide-blocking mask at other locations of the device.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: June 17, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Danielle A. Thomas, Giles E. Thomas
  • Patent number: 6573488
    Abstract: A plurality of resistive regions constituting a resistive region gradually increase in width from one end to the other end and have substantially the same resistivity. If, therefore, this semiconductor position sensitive detector is placed such that charges generated in accordance with incident light from an object at a long distance flow into narrow resistive regions, since the narrow resistive regions have high resistances, the output currents from the two ends of the resistive region greatly change to improve the position detection precision even in a case wherein the incident light position only slightly moves on the surface as the distance to the object changes.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: June 3, 2003
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Tatsuo Takeshita, Masayuki Sakakibara
  • Patent number: 6555739
    Abstract: A photovoltaic array includes a plurality of solar cells electrically coupled in series with one another via a plurality of electrically conductive interconnect members and end members. The solar cells and interconnect members are bonded to the array surface of a substrate with double-sided pressure sensitive adhesive, and the interconnect members and end members are electrically coupled to the solar cells via a dry electrical contact. The method of manufacturing the array reduces complexity, time, and costs.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: April 29, 2003
    Assignee: Ekla-Tek, LLC
    Inventor: Elias Kawam
  • Patent number: 6552259
    Abstract: In this bypass-function added solar cell, a plurality of island-like p+ regions, which is third regions, are formed at a boundary between a p-type region and an n-type region layer constituting a substrate so that the p+ regions project into the region and the region and are separated away from the surface of the substrate. Therefore, in this solar cell, unlike prior art counterparts, the insulating film for isolating the p+ regions and the n electrodes constituting the np+ diode from one another is no longer necessary, thus allowing a reduction in manufacturing cost. As a result, a bypass-function added solar cell with a bypass-diode function added thereto can be provided with low cost and by simple process.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: April 22, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigeyuki Hosomi, Tadashi Hisamatsu
  • Publication number: 20030067000
    Abstract: The present invention relates to a device having a solid conjugated semiconductor comprising a hole transport material (HTM), wherein the hole transport material is mixed with oxidized hole transport material as a dopant; to a mixture which can be used as doped hole transport material; and to methods for the preparation of devices having a solid conjugated semiconductor. The present invention also relates to a solar cell comprising such a device and to other devices made with conjugated semiconductors, such as diodes (LEDs), transistors etc.
    Type: Application
    Filed: September 3, 2002
    Publication date: April 10, 2003
    Inventors: Gabriele Nelles, Akio Yasuda, Stephane Gaering, Hans-Werner Schmidt, Mukundan Thelakkat, K.R. Haridas
  • Patent number: 6531711
    Abstract: The productivity of a photoelectric conversion device is increased by separately conducting a step of forming a microcrystalline semiconductor film and an amorphous semiconductor film without adding an impurity gas.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: March 11, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Yasuyuki Arai, Shunpei Yamazaki
  • Patent number: 6528824
    Abstract: In a light-emitting device wherein a light shield portion is disposed in touch with a transparent electrode included in a pixel, the light shield portion (105 in FIG. 1) is disposed at the peripheral part of the transparent electrode (101), whereby that part of light (visible light) emitted in an EL layer (102) which escapes from the peripheral part of the transparent electrode (101) can be intercepted or reflected. Thus, the loss of the light emitted in the EL layer (102) and the leakage thereof to an adjacent pixel can be prevented, and the efficiency of deriving the light can be sharply heightened.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: March 4, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hirokazu Yamagata, Junya Maruyama
  • Patent number: 6521967
    Abstract: A three-color QWIP focal plane array is based on a GaAs/AlGaAs material system. Three-color QWIPs enable target recognition and discriminating systems to precisely obtain the temperature of two objects in the presence of a third unknown parameter. The QWIPs are designed to reduce the normal reflection over a significant wavelength range. One aspect of the present invention involves two photon absorptions per transition in a double quantum well structure which is different from typical QWIP structures. This design is expected to significantly reduce the dark current as a result of higher thermionic barriers and therefore allow the devices to operate at elevated temperatures. The device is expected to be fabricate using a GaAs/AlxGa1−xAs material system on a semi-insulating GaAs substrate by Molecular Beam Epitacy (MBE).
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: February 18, 2003
    Assignee: California Institute of Technology
    Inventors: Sumith V. Bandara, John K. Liu, Daniel Wilson, Sarath D. Gunapala, William Parrish
  • Patent number: 6512279
    Abstract: A photoelectric converter of a high signal-to-noise ratio, low cost, high productivity and stable characteristics and a system including the above photoelectric converter. The photoelectric converter includes a photoelectric converting portion in which a first electrode layer, an insulating layer for inhibiting carriers from transferring, a photoelectric converting semiconductor layer of a non-single-crystal type, an injection blocking layer for inhibiting a first type of carriers from being injected into the semiconductor layer and a second electrode layer are laminated in this order on an insulating substrate.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: January 28, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Noriyuki Kaifu, Hidemasa Mizutani, Shinichi Takeda, Isao Kobayashi, Satoshi Itabashi
  • Patent number: 6489642
    Abstract: An image sensor, includes a semiconductor substrate; a photosensor having, a first photosensing region including a first stack of one or more layers of transparent materials overlying the substrate, the first photosensing region having a spectral response having peaks and valleys, and a second photosensing region including a second stack of one or more layers of transparent materials overlying the substrate, the second photosensing region having a spectral response having peaks and valleys; and wherein at least one peak or valley of the spectral response of the first region is matched to at least one valley or peak respectively of the spectral response of the second region such that the average spectral response of the photosensor is smoother than the individual spectral response of either the first or second photosensing regions.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: December 3, 2002
    Assignee: Eastman Kodak Company
    Inventors: William G. America, Christopher R. Hoople, Loretta R. Fendrock, Stephen L. Kosman
  • Patent number: 6489677
    Abstract: An optical semiconductor device module includes an optical semiconductor device package, an optical semiconductor device such as a laser diode accommodated in the package, and a cooling area on an inner face of a metal bottom plate of the package and operable to cool the optical semiconductor device. A groove permitting molten solder to flow therein is formed in at least part of the solder joint area on the inner face of the metal bottom plate.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: December 3, 2002
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Takahiro Okada, Toshio Kimura
  • Patent number: 6476455
    Abstract: An infrared sensor includes a concavity made on a side of a semiconductor substrate and a plurality of sensing areas formed in a thin film area on the back side of the bottom of the concavity. Groups of two thermocouples, three thermocouples and four thermocouples reside in a sensing area in the central part of the thin film area, in another sensing area adjacent the central sensing area and in yet other sensing areas adjacent to the central sensing area, respectively, to compensate for the heterogeneity of heat transfer in the thin film area. Therefore, sensitivity loss is suppressed in the sensing area having a boundary with the substrate. More specifically, the difference in sensitivity between the sensing areas is reduced.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: November 5, 2002
    Assignee: Denso Corporation
    Inventors: Inao Toyoda, Kazuaki Hamamoto
  • Publication number: 20020158297
    Abstract: A conventional dye-sensitized solar cell is a wet cell employing an electrolyte such as an iodine solution or the like, it is necessary to seal the solar cell with a sealing compound or the like in order to contain the iodine solution therein. Therefore, there are many problems in that, for example, leakage of electrolyte solution occurs when the sealing is broken. Furthermore, when only a flat-shaped titanium electrode is used, current and voltage of practically required levels can not be secured because the absorption area of solar rays is small. The solar cell of the present invention, employing a porous titanium dioxide semiconductor, is characterized in that the titanium dioxide semiconductor is held between a pair of electrodes so that the titanium dioxide semiconductor and at least one of the electrodes form a rectification barrier.
    Type: Application
    Filed: November 6, 2001
    Publication date: October 31, 2002
    Inventors: Yuji Fujimori, Suwa-Shi, Tsutomu Miyamoto, Shiojiri-shi
  • Publication number: 20020153584
    Abstract: A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.
    Type: Application
    Filed: June 7, 2002
    Publication date: October 24, 2002
    Inventors: Gary A. Frazier, Alan C. Seabaugh
  • Publication number: 20020153583
    Abstract: A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.
    Type: Application
    Filed: June 7, 2002
    Publication date: October 24, 2002
    Inventors: Gary A. Frazier, Alan C. Seabaugh
  • Patent number: 6469358
    Abstract: Exemplary embodiments of the present invention use a vertically stacked quantum well infrared detector where each “tuned” quantum well of the detector can be biased separately from any other quantum well of the detector. The vertically stacked detector can include three or more quantum well layers that are “tuned” to different peak wavelengths to permit detection of infrared radiation of three or more different bands or colors. The simultaneous detection of infrared radiation in three or more different spectral bands permits the determination of more information about an infrared source.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: October 22, 2002
    Assignee: Lockheed Martin Corporation
    Inventor: Robert J. Martin
  • Patent number: 6459132
    Abstract: A photosensing device having a photoelectric conversion element and a TFT with a high S/N ratio and with stable characteristics can be provided by carrying out patterning of source and drain electrodes of the TFT part and patterning of an upper electrode of the photoelectric conversion element separately and by carrying out removal of an n+-layer between the source and drain electrodes of the TFT part in a separate step.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: October 1, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventor: Chiori Mochizuki
  • Patent number: 6455873
    Abstract: Microelectronic devices have a semiconductor/conducting polymer interface are disclosed. The conducting polymer may be electrically contacted in a manner to assure that it remains exposed to the environment. If the environment is an inert electrolyte to which additional electrodes are contacted, the conducting polymer can be electrochemically oxidized or reduced to control its electrochemical potential and a tunable (variable barrier) diode results. This tunable diode is a device that rectifies current like a traditional diode, but unlike traditional diodes, the effective barrier height of the tunable diode can be actively controlled. This control can be an element of an active device or a means for fabricating fixed barrier diodes with controlled barrier heights. Alternatively, the environment can contain an analyte to be sensed, either directly or through a mediating layer. The electrical characteristics (e.g.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: September 24, 2002
    Assignee: State of Oregon Acting by and through the State Board of Higher Education on behalf of the University of Oregon
    Inventor: Mark C. Lonergan
  • Patent number: 6452087
    Abstract: Disclosed is a photovoltaic device comprising on a substrate (1) a plurality of photovoltaic elements (10) each composed of a lamination body of a first electrode (2), a photovoltaic conversion layer (3), and a second electrode (4), the thickness of a side end (B) in the first electrode (2) in the vicinity of a separating trench (S) existing between the first electrode (2) and the adjacent first electrode (2) being larger than the thickness of an element region (A) in the first electrode (2).
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: September 17, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Manabu Sasaki, Katsunobu Sayama, Kunimoto Ninomiya, Shigeo Yata, Hiroshi Ishimaru