Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least {fraction (1/100)} of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

Abstract: A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).

Abstract: Disclosed are semiconductor systems, such as integrated circuits utilizing Schotky barrier and/or diffused junction technology, which semiconductor systems incorporate material(s) that form rectifying junctions in both metallurgically and/or field induced N and P-type doping regions, and methods of their use. Disclosed are Schottky barrier based inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems and which can be operated as modulators, N and P-channel MOSFETS and CMOS formed therefrom, and (MOS) gate voltage controlled rectification direction and gate voltage controlled switching devices, and use of such material(s) to block parasitic current flow pathways. Simple demonstrative five mask fabrication procedures for inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Abstract: A method for forming a Schottky diode structure is disclosed. The method includes the steps of: a) Providing a substrate; b) forming a rare-earth containing layer over the substrate; and c) forming a metal layer over the rare-earth containing layer. The Schottky diode structure with a rare-earth containing layer has the properties of high-temperature stability, high Schottky barrier height (SBH), and low reverse leakage current.

Abstract: A compound semiconductor transistor has a structure in which a first insulating film is formed only under a overhang of a gate electrode an upper part of which is formed widely, and a second insulating film for threshold voltage adjustment is formed on the side of a gate electrode and the first insulating film.

Abstract: An RF diode, and method for its manufacture, in which a well, doped n-conductive or p-conductive, is formed in a high-ohmic silicon substrate. A silicon epitaxial layer is provided over a first subregion of a surface of the well wherein the layer has the same conductivity type as the doped well. The silicon epitaxial layer is provided with a first Schottky contact layer onto which a first contact metallization is applied. A second subregion located next to the first subregion of the surface of the well is provided with a second Schottky contact layer onto which a second contact metallization is applied.

Abstract: A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.

Abstract: A Schottky-barrier sensor has a semiconductor substrate having a pair of metal contacts formed thereon. The contacts form a Schottky barrier at each interface between metal and substrate, and the substrate is mounted on a surface. Strain, temperature and other physical parameters which affect the Schottky-barrier potential can be measured by voltage or current measuring equipment conductively connected to the Schottky-barrier semiconductor device.

Abstract: In a method for fabricating a semiconductor device, an insulating layer is formed on a semiconductor substrate, then a resist layer is formed on the insulating layer to have an opening therein. Next, removing the insulating layer at the bottom of the opening, then a reflow process is performed to the resist layer to have a curved surface thereon.

Abstract: A new conceptional transistor and a method for manufacturing, which increases the integration of semiconductor devices using conventional MOS devices are provided. The present invention provides a transistor in which a structure of metal-insulator film-metal dot-metal (MIMIM), metal-insulator film-metal dot-semiconductor (MIMS), or semiconductor-metal dot-semiconductor (SMS) is formed, using junction of electrodes operating as a source and a drain having a metal dot of nm therebetween, and the current flow between source and drain is controlled by controlling tunneling and Schottky barrier formed between the source and the metal dot using the method of controlling electrical potential of metal dot through charging effect of gate electrode isolated by a thick insulator.

Abstract: The present invention relates to a schottky-barrier diode capable of decreasing a leakage current due to damage generated on inner walls of trenches, and securing a large operation region for itself. In the device, an N.sup.- -type epitaxial layer is formed on a N.sup.+ -type silicon substrate. In a predetermined region in the epitaxial layer, a P.sup.+ -type base diffusion layer having high impurity concentration is formed. Trenches are formed through from the surface of the base diffusion layer to the epitaxial layer. In each of the trenches, an N.sup.- -type selective epitaxial growth region is formed. A schottky metal is formed on a surface comprising the surfaces of the base diffusion layer, which includes the selective epitaxial growth regions, and the epitaxial layer. Surface regions as the surfaces of the selective epitaxial growth regions filling the trenches function as diode operation regions.

Abstract: A heterojunction semiconductor device includes a first Schottky contact layer made of a first semiconductor, a second Schottky contact layer made of a second semiconductor and a metal electrode. The first Schottky contact layer, the second Schottky contact layer and the metal electrode are laminated in this order on a semiconductor substrate or on a main structure of a semiconductor device laminated on a semiconductor substrate from the substrate side or from the main structure side. The first Schottky contact layer serves as a barrier layer toward the second Schottky contact layer, and a layer thickness of the second Schottky contact layer is greater than the mean free pass of carriers in the second Schottky contact layer.

Abstract: A Schottky diode having a series of stacked layers starting with a conventional substrate having a semi-insulating GaAs layer and an un-doped GaAs buffer layer. An n-type Si--GaAs channel layer is grown on the GaAs buffer layer. A low-temperature-grown GaAs barrier layer covers the center portion of the upper surface of the n-type channel layer. The Schottky diode comprises two terminals. One diode terminal comprises a ohmic contact deposited on the upper surface of the channel layer. This ohmic contact, which is ring-shaped, encircles the barrier layer. The other diode terminal includes a metal layer that forms a Schottky contact with the upper surface of the barrier layer. The Ga-to-As ratio in the low-temperature-grown GaAs barrier layer is adjusted so that the barrier layer contains a sufficient number of free electrons to support current flow for bias voltages above the Schottky barrier height.

Abstract: A semiconductor device structure having a semiconductor device on a substrate with a layer of benzocyclobutane (BCB) disposed about the device with a via between the top surface of the BCB and the device is disclosed. A bond pad is in contact with the via and is connected to a bond ribbon.

Abstract: A semiconductor device has an improved schottky barrier junction. The device includes: a substrate; an epitaxial layer covering the substrate and lightly doped with a dopant selected from a group consisting of a rare earth element and an oxide of a rare earth element; and a metal layer covering the epitaxial layer and forming said schottky barrier junction with said epitaxial layer.

Abstract: A metal-semiconductor-metal (MSM) photodetector, specifically a new, improved low noise device is disclosed. The disclosed device is a MSM photodiode in which the cathode and anode are made of different materials with optimal Schottky barrier heights. One of these materials is chosen to provide a high ratio of Schottky barrier height to hole transport and the other to provide a high ratio of Schottky barrier height to electron transport. The disclosed MSM photodetector is designed to allow each Schottky barrier to be individually optimized to the point that a wide bandgap Schottky barrier enhancement layer and its associated heterointerface may become unnecessary. Elimination of the charge buildup at the heterointerface enhances carrier extraction resulting in photodetectors with elevated quantum efficiency and enhanced bandwidths.

Abstract: Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion.

Abstract: A MOS transistor formed in a silicon on insulator structure includes a rectifying connection between a body portion and the gate. The connection decreases the threshold voltage of the transistor in the reverse bias state and limits a difference in voltage between the body and gate in the forward bias state of the rectifying contact.

Abstract: A semiconductor device includes a semiconductor substrate on which are successively disposed, a semiconductor laminated layer structure including at least two semiconductor layers, a first semiconductor layer containing a first dopant impurity providing a first conductivity type, and a second semiconductor layer containing the first dopant impurity in a concentration higher than in the first semiconductor layer. A semiconductor diode includes a first electrode in ohmic contact with the second semiconductor layer, and a second electrode in Schottky contact with the second semiconductor layers. A transistor includes a gate electrode in the recess and making a Schottky contact with the first semiconductor layer, and a source electrode and a drain electrode disposed on opposite sides of the recess on the second semiconductor layer, and in ohmic contact with the second semiconductor layer.

Abstract: In a Schottky barrier diode, concentration of an electrical field at an edge of an insulation layer is suppressed to improve the reverse breakdown voltage. An n- layer of a compound semiconductor substrate having an n+ layer and the n- layer is configured in the form of a mesa. An insulation layer is formed on at least a skirt portion and a slant portion of the mesa. An anode is formed on the insulation layer and n- layer, and a cathode is formed on the n+ layer. Thus, concentration of an electrical field at an edge of the insulation layer is canceled at least in part by an electrical field generated at the anode on the slant portion to improve the reverse breakdown voltage.

Abstract: A latch-type SRAM memory cell having a number of MOS transistors arranged to maintain symmetry with each other circuitwise, in which the source regions of the MOS transistors are arranged so as to be adjacent semiconductor regions of opposite conductivity with respect thereto. Zener diodes are formed between the adjacent source and semiconductor regions with each of these Zener diodes being connected between their respective source regions and a power supply. Since current to each source region of paired MOS transistors flows effectively to the power supply or ground side via a Zener diode using a tunneling effect, a rise in the source region potential can be reduced, and an increase in the transistor threshold value can be controlled. In this way, symmetry of the paired transistors can be maintained, and the performance of the memory cell, e.g., memory cell data retention ability and drive current ability, can be increased.

Abstract: (MOS) device systems-utilizing Schottky barrier source and drain to channel region junctions are disclosed. Experimentally derived results which demonstrate operation of fabricated N-channel and P-channel Schottky barrier (MOSFET) devices, and of fabricated single devices with operational characteristics similar to (CMOS) and to a non-latching (SRC) are reported. Use of essentially non-rectifying Schottky barriers in (MOS) structures involving highly doped and the like and intrinsic semiconductor to allow non-rectifying interconnection of, and electrical accessing of device regions is also disclosed. Insulator effected low leakage current device geometries and fabrication procedures therefore are taught.

Abstract: A field-effect transistor has its gate length made to be minute, and a short channel effect is prevented. The field-effect transistor which attains the above objects has first and second semiconductor regions having different impurity concentrations disposed so as to be adjacent to each other. A source electrode is disposed on the second semiconductor region with a high impurity concentration, a drain electrode on the first semiconductor region with a low impurity concentration, and a gate electrode on the first semiconductor region side of the second semiconductor region.

Abstract: A high operating voltage bipolar transistor (42) includes a base including a first region (52) of a lightly doped layer (44) of semiconductor material of a first conductivity type. The transistor (42) also includes a collector including a buried layer (50) and a collector region (48). The lightly doped layer (44) is formed over the buried layer (50) and the collector region (48) extends through the lightly doped layer (44) and contacts the buried layer (50). The transistor (42) also includes an emitter formed in the base. The transistor (42) provides a high operating voltage without requiring an increased thickness epitaxial layer or additional processing steps. A high Hfe transistor and high voltage Schottky diode are also described.

Abstract: A FET has comb-shaped electrode assemblies for source, drain and gate of the FET. Each of the source and drain electrode assemblies has a plurality of electrodes contacting the active region of the FET and formed as a first layer metal laminate, and a bus bar connecting the electrodes together to a corresponding pad and formed as a second layer metal laminate. The gate electrode layer has a plurality of gate electrodes contacting the active layer in Schottky contact, a gate bus bar connecting the gate electrodes together, a gate pad connected to the gate bus bar. The gate bus bar is formed as a first layer metal laminate intersecting the stem portion of the comb-shaped source bus bar. The two-layer metal structure of the FET reduces the number of photolithographic steps and thereby fabrication costs of the FET.

Abstract: A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate is provided. Then, a silicon carbide drift layer is provided upon the substrate, wherein the drift layer has two spaced-apart protrusions or fingers which extend away from the substrate. Each protrusion of the drift layer has a source region of silicon carbide provided thereon. A gate material is then provided along the drift layer between the two protrusions. A conductive gate contact is provided upon the gate material and a conductive source contact is provided upon each source region. A conductive drain contact is provided along the substrate. Other gate types for the static induction transistor are contemplated. For example, a planar Schottky barrier gate may be employed.

Abstract: The present invention is to provide a Static Induction semiconductor device with a Static Induction Schottky shorted structure where the main electrode region is composed of regions of higher and lower impurity densities relative to each other, the main electrode forms an ohmic contact with the higher impurity density region and also forms a Schottky contact with a Static Induction Schottky shorted region of the lower impurity density region surrounded by tile higher impurity density region, and it is excellent in turn-off performance and easy to use, by substantially reducing tile minority carrier storage time, the fall time and the quantity of gate pull-out charges in order that charges may easily be pulled out from the cathode or source electrode as well as from the gate electrode at turn-off.

Abstract: A switching element is provided with two electrodes (1, 2) with a semiconducting dielectric (3) therebetween, one electrode (2) having a material which forms a Schottky contact with the semiconducting dielectric (3), while a space charge region (3') of the Schottky contact forms a tunnelling barrier for electrons during operation. It is desirable in many applications for the switching element to hold a certain switching state, such as open or closed, during a longer period. The switching element may then be used, for example, as a memory element. The dielectric (3) includes a ferroelectric material with a remanent polarization which influences a dimension of the tunnelling barrier. In this manner the switching element has various switching states depending on the remanent polarization of the dielectric (3). These switching states are held until the polarization of the dielectric (3) changes.

Abstract: A method of producing a semiconductor device including a Schottky barrier diode (SBD) comprising the steps of: selectively forming an insulating layer having a first contact hole and a second contact hole, on a (100) silicon semiconductor substrate; selectively forming a polysilicon layer extending from the first contact hole to the second contact hole, the polysilicon layer having a viahole within the first contact hole for selectively exposing the silicon semiconductor substrate; and selectively depositing a refractory metal (tungsten or molybdenum) layer on the polysilicon layer and an exposed portion of the substrate within the viahole by a selective CVD process, so that the SBD is formed between the exposed portion and the metal layer. The refractory metal layer is formed on the silicon of the exposed portion of the substrate and the polysilicon layer and is not formed on the insulating layer, and thus it is unnecessary to perform a photolithography process for patterning the refractory metal layer.

Abstract: A process for producing a radiation resistant power MOSFET is disclosed. The gate oxide is formed toward the end of the processing and is not exposed to substantial thermal cycling. Arsenic doping is used in the early part of the process to form the source region, and diffused too slowly to be adversely affected by later thermal cycling process steps. The source region has a relatively high resistance to act as a ballasting resistor to prevent burnout of one of a large number of parallel connected cells.

Abstract: A semiconductor device, comprising a transistor, a constant voltage diode having a first end of a first conductivity type connected to an emitter of the transistor and a second end of a second conductivity type, a reverse current preventive diode having a first end of the first conductivity type connected to a collector of the transistor and a second end of the second conductivity type connected to the second end of the constant voltage diode, and a high speed diode reverse-bias connected between the transistor collector and the emitter of the transistor.

Abstract: An injection control-type Schottky barrier rectifier, including: a semiconductor region having a first conductivity type; a first diffusion region, which is formed in the semiconductor region and which has a second conductivity type, the second conductivity type being different from the first conductivity type, for forming a depletion layer in the semiconductor region when a turn-off voltage is applied to the Schottky barrier rectifier; a second diffusion region, which is formed in the semiconductor region and which has the second conductivity type, for causing conductivity modulation in the semiconductor region when a turn-on voltage is applied to the Schottky barrier rectifier; a barrier electrode which is ohmically connected with the first diffusion region and which forms a Schottky junction with the surface of the semiconductor region which is opposite to the second diffusion region with respect to the first diffusion region; a gate insulator film formed on the surface of the semiconductor region between

Abstract: A trench MOS Schottky barrier rectifier includes a semiconductor substrate having first and second faces, a cathode region of first conductivity type at the first face and a drift region of first conductivity type on the cathode region, extending to the second face. First and second trenches are formed in the drift region at the second face and define a mesa of first conductivity type therebetween. The mesa can be rectangular or circular in shape or of stripe geometry. Insulating regions are defined on the sidewalls of the trenches, adjacent the mesa, and an anode electrode is formed on the insulating regions, and on the top of the mesa at the second face. The anode electrode forms a Schottky rectifying contact with the mesa.

Abstract: A semiconductor device, comprising a transistor, a constant voltage diode having a first end of a first conductivity type connected to an emitter of the transistor and a second end of a second conductivity type, a reverse current preventive diode having a first end of the first conductivity type connected to a collector of the transistor and a second end of the second conductivity type connected to the second end of the constant voltage diode, and a high speed diode reverse-bias connected between the transistor collector and the emitter of the transistor.

Abstract: A GaAs field effect transistor with a source contact including both an ohmic contact and a Schottky barrier, the Schottky barrier between the ohmic contact and the gate, is disclosed. The Schottky barrier provides a high frequency source contact close to the active channel and thereby reduces the parasitic source resistance at microwave and higher frequencies.

Abstract: A semiconductor device utilizing a non-doped diamond layer between a substrate and an active diamond layer. Such a structure decreases the resistivity and increases the carrier density. Further, when contacts are formed on the active layer, this layer structure reduces reverse leak current.

Abstract: A field-effect transistor in which a metal gate (14) is defined on top of an insulating substrate (12). A free-standing semiconductor thin film (16), obtained by the epitaxial lift-off process, is bonded to both the top of the metal gate and the insulating substrate. Electrodes (20, 22) attached to the top of ends of the semiconductor film complete the transistor.

Abstract: This is a FET device and the device comprises: a buffer layer 30; a channel layer 32 of doped narrow bandgap material over the buffer layer; and a resistive layer 34 of low doped wide bandgap material over the channel layer, the doping of the channel layer and the resistive layer being such that no significant transfer of electrons occurs between the resistive layer and the channel layer. This is also a method of making a FET device.

Abstract: A rectifying contact includes a first semiconducting diamond layer, a second undoped diamond layer on the first layer, and a third relatively highly doped diamond layer on the second layer. The first semiconducting diamond layer may be formed on a supporting substrate. A bonding contact is preferably formed on the third relatively highly doped diamond layer for facilitating electrical connection thereto. The bonding contact is preferably a titanium carbide/gold bilayer. In one embodiment, an ohmic contact may be formed on the first semiconducting diamond layer by an electrically conductive substrate and an associated metal layer on an opposite side of the substrate from the semiconducting diamond layer. In another embodiment, an ohmic contact may be formed on the first semiconducting diamond layer by a fourth relatively highly doped diamond layer and an associated bonding contact on the fourth diamond layer.

Abstract: A high bandwidth RF sampler using equivalent time sampling comprising an RF coplanar waveguide integrated with sampling diodes on a gallium arsenide substrate. A monolithic, integrated nonlinear transmission line is integrated on the same substrate to receive sample pulses. These pulses are reshaped by the nonlinear transmission line to have a very fast edge. This edge is differentiated by a shunt inductance of a short circuit termination of a slot line portion of the RF signal coplanar waveguide. The resulting delta function sample pulses cause the sample diodes and integrated capacitors to develop an intermediate output frequency which is a replica of the RF signal at a lower frequency and no voltage conversion loss. RF signals of up to 300 Ghz can be sampled using this circuit.

Abstract: A method and apparatus of testing semiconductor properties of a protein. Mercury electrodes are formed in an aqueous solution of protein and protein is adsorbed of the surface of the mercury electrodes. The electrical properties of the protein adsorbed thereon can be determined by applying current and voltage thereto.

Abstract: An integrated gate and semiconductor barrier layer diode which functions as a regular diode when the gate is turned off and as, a Schottky barrier diode with the gate turned on.

Abstract: In a semiconductor device, an interconnection of differentially doped diffusion regions formed on a substrate includes an interconnecting layer disposed between the two diffusion regions so that the two regions are coupled to one another. The interconnect region is defined by the existing mask boundaries of N+ dopant and P+ dopant regions such that N+ and P+ dopant is not allowed to enter the interconnect region. Thus, the interconnect region is defined without requiring additional masking and etching steps. Once the interconnect region is defined, then the interconnecting layer is formed by a deposition and sintering process. The interconnecting layer provides a schottky barrier and ohmic contact.

Abstract: An improved junction type photovoltaic element, characterized by having an organic semiconductor layer formed of a polysilane compound of 6000 to 200000 in weight average molecular weight which is represented by the following general formula (I): ##STR1## Wherein, R.sub.1 stands for an albyl group of 1 to 2 carbon atoms; R.sub.2 stands for an alkyl group, cycloalkyl group, aryl group or aralkyl group of 3 to 8 carbon atoms; R.sub.3 stands for an alkyl group of 1 to 4 carbon atoms; R.sub.4 stands for an alkyl group of 1 to 4 carbon atoms; A and A' respectively stands for an alkyl group, cycloalkyl group, aryl group or aralkyl group of 4 to 12 carbon atoms wherein the two substituents may be the same or different one from the other; and each of n and m is a mole ratio showing the proportion of the number of respective monomers versus the total of the monomers in the polymer wherein n+m=1, 0<n.ltoreq.1 and 0.ltoreq.m<1.

Abstract: A COM switching device includes an n.sup.+ -type layer formed on a p.sup.+ -type layer, p.sup.+ -type regions formed in the surface areas of an n.sup.- -type layer formed on the n.sup.+ -type layer, n.sup.+ -type regions formed in the surface areas of the p.sup.+ -type regions, and a gate electrode formed on an insulating layer over the surface areas of the p.sup.+ -type regions which lie between the n.sup.+ -type regions and the n.sup.- -type layer. The n.sup.+ -type layer is formed such that the amount of impurities per unit area is between 5.times.10.sup.13 cm.sup.-2 and 1.times.10.sup.15 cm.sup.-2, and the p.sup.+ -type layer is formed to have an impurity concentration between 2.times.10.sup.18 and 8.times.10.sup.18 cm.sup.-3.

Abstract: Schottky barrier diode comprises a Schottky contact layer having an increased periphery to area ratio. In the illustrated embodiment, the Schottky contact layer comprises a plurality of individual contact regions interconnected by an overlying metallization layer.

Abstract: A semiconductor device comprises: a drain region made of one conductivity type semiconductor substrate having first and second major surfaces; a source region made of one conductivity type first impurity region and formed inside said drain region with being in contact with said first major surface of the drain region; a gate electrode formed in a first groove having a U shape and covered with an insulating film, said U-shaped first groove being dug from said first major surface of the drain region into said inside of the drain region and positioned in contact with one side of said source region; a second groove dug from said first major surface into said inside of the drain region and positioned in contact with the other side of said source region, a metal functioning as a source electrode being embedded into said second groove so as to constitute a Schottky junction with said drain region; a drain electrode electrically connected to said second major surface of the drain region; and, a channel region formed

Abstract: A semiconductor device including a single crystal semiconductor host material having a surface; an ultrathin pseudomorphic single crystal epitaxial interlayer formed on the surface of the host material, wherein the interlayer is formed of a material and has a thickness selected so that the material of the interlayer is elastically deformed on the surface of the host material to match the lattice constant of the interlayer material with the lattice constant of the host material; and a further material incompatible with the host material when interfaced directly with the host material, but compatible with the interlayer, provided on the interlayer and thereby interfaced with the host material to perform a predetermined function with respect to the interlayer and the host material.