Abstract: A structure and manufacturing method of an SiC dual metal trench diode. P-type impurity is doped into the bottom of the trench layer of the dual metal trench Schottky diode to eliminate leakage current or avalanche breakdown in the corner of the trench layer in order to increase the concentration of the epitaxial layer. N-type impurity can also be doped into the region between the Schottky contact metal and the epitaxial layer to adjust the Schottky barrier and thus reduce forward voltage required for current to flow through.

Abstract: A rectifier structure that exhibits a low turn-on voltage and allows rapid switching without ringing is provided. The structure utilizes a thin epitaxial layer interposed between the two layers comprising the rectifier junction. Preferably the epitaxial layer is of the same conductivity as the underlying layer while being comprised of the same material as the outermost layer.

Abstract: A Schottky diode has a barrier height which is adjusted by boron implant through a titanium silicide Schottky contact and into the underlying N− silicon substrate which receives the titanium silicide contact. The implant is a low energy, of about 10 keV (non critical) and a low dose of less than about 1E12 atoms per cm2 (non-critical).

Abstract: A high-speed, soft-recovery semiconductor device that reduces leakage current by increasing the Schottky ratio of Schottky contacts to pn junctions. In one embodiment of the present invention, an n− drift layer is formed on an n+ cathode layer 1 by epitaxial growth, and ring-shaped ring trenches having a prescribed width are formed in the n− drift layer. Oxide films are formed on the side walls of each ring trench. The ring trenches are arranged such that the centers of the rings of the ring trenches adjacent to one another form a triangular lattice unit. A p− anode layer is formed at the bottom of each ring trench. Schottky contacts are formed at the interface between an anode electrode and the surface of the n− drift layer. Ohmic contact is established between the surfaces of polysilicon portions and the anode electrode.

Abstract: It is an object to provide a semiconductor device which can prevent an operation thereof from being uncontrollable to obtain a high reliability, and can be manufactured easily and can reduce a manufacturing cost. A p-type impurity layer (102) containing a p-type impurity in a relatively high concentration (p+) is provided as an operation region of a diode in one of main surfaces of a silicon substrate (101) containing an n-type impurity in a relatively low concentration (n−) and a plurality of ring-shaped Schottky metal layers (106) are concentrically provided on the main surface of the silicon substrate (101) around the p-type impurity layer (102) with a space formed therebetwen to surround the p-type impurity layer (102). A silicon oxide film (107) is provided on the main surface of the silicon substrate (101) around the p-type impurity layer (102) and an anode electrode (104) is provided on the p-type impurity layer (102).

Abstract: An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate underlying the gate electrode operates in an enhancement mode. The barrier layer is particularly useful ill compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.

Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least {fraction (1/100)} of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: A method for controlling the temperature dependence of a junction barrier Schottky diode of a semiconductor material having an energy gap between the valence band and the conduction band exceeding 2 eV provides for doing this when producing the diode by adjusting the on-state resistance of the grid portion of the diode during the production for obtaining a temperature dependence of the operation of the diode adapted to the intended use thereof.

Abstract: The present invention relates to a semiconductor arrangement with a MOS transistor which has a gate electrode (40), arranged in a trench running in the vertical direction of a semiconductor body (100), and a Schottky diode which is connected in parallel with a drain-source path (D-S) and is formed by a Schottky contact between a source electrode and the semiconductor body.

Abstract: On a first region (R1) of a surface (101S1) of an n-type silicon carbide layer (101), a Schottky drain electrode (102) is formed. Further, on a second region (R2), an ohmic source electrode (103) is formed. Furthermore, on a third region (R3), a Schottky gate electrode (104) is formed. Such a structure achieves a state where a Schottky barrier diode is formed between these electrodes (102 and 103). That can achieve a switching element using the silicon carbide layer with high breakdown voltage and low loss, which has both a switching function and a diode function (voltage blocking capability of reverse direction), with no pn junction formed in the silicon carbide layer, and thereby ensures reduction in size an weight of modules.

Abstract: A gate electrode is in Schottky contact with the surface of a semiconductor substrate and extends in a first direction. A drain electrode is disposed on one side of the gate electrode, spaced apart from the gate electrode by some distance, and is in ohmic contact with the semiconductor substrate. A source electrode is constituted of a main part, an overhanging part and a shielding part. The main part is in ohmic contact with the semiconductor substrate in the region across the gate electrode from the drain electrode. The shielding part is disposed between the gate electrode and the drain electrode and extends in the first direction. The overhanging part passes over the gate electrode and connects the shielding part with main part. The size of the overhanging part along the first direction is smaller than the side of the shielding part.

Abstract: A plurality of p anode regions are formed at one surface of an n− substrate. A trench is formed in each p anode region. An ohmic junction region is formed between an anode metallic electrode and the p anode region. The p anode region has a minimum impurity concentration at a portion near the ohmic junction region which enables ohmic contact. A cathode metallic electrode is formed at the other surface of the n− substrate with an n+ cathode region interposed. Accordingly, a semiconductor device which has an improved withstand voltage and in which the reverse recovery current is reduced can be obtained.

Abstract: The invention relates to a semiconductor component with adjacent Schottky (5) and pn (9) junctions positioned in a drift area (2, 10) of a semiconductor material. The invention also relates to a method for producing said semiconductor component.

Abstract: In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments, one conductive layer provides an electromagnetic shield that shields the substrate from AC signals carried by a contact pad made from another conductive layer on a backside of the substrate. The conductive layers can also be used to form capacitor/rectifier networks. Manufacturing methods are also provided.

Abstract: A semiconductor device comprises a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type, a base layer of a second conductivity type provided in the first semiconductor layer, for defining a vertical MISFET including source regions and a gate electrode on a gate insulation film, a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer around the base layer, a guard ring region of the second conductivity type provided around SBD-forming region, a first main electrode disposed above the first semiconductor layer and provided in common as both a source electrode of the MISFET and an anode of the SBD, a surface gate electrode disposed above the first semiconductor layer, and a second main electrode provided in common as a drain electrode of the MISFET and a cathode of the SBD.

Abstract: A composite field ring for a Schottky diode has a low concentration deep portion to increase breakdown voltage withstand and a high concentration, shallow region to enable minority carrier injection during high forward current conduction. The composite ring permits a reduction in the thickness of the epitaxially formed layer which receives the Schottky barrier metal.

Abstract: A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.

Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.

Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

Abstract: In an active matrix type display having built-in drivers, a metal layer (32) is formed over a portion of a transparent substrate and a buffer layer (11) is provided over both the region where the metal layer (32) is formed and over the region where the metal layer (32) is not formed. Above the buffer layer (11), a first polycrystalline silicon film (14) is provided over the region where the metal layer is formed and a second polycrystalline silicon film (140) is provided over the region where the metal layer is not formed. A buffer layer (11) with sufficient thickness and thermal capacity can provide sufficient distance between the active layers and the lower metal layer to alleviate thermal leakage caused by the metal layer. A first polycrystalline silicon film (14) and a second polycrystalline film (140) each having a proper grain size can be obtained through laser annealing applied under the same conditions on an amorphous silicon film formed over the buffer layer (11).

Abstract: A switching device receives two pairs of balanced signals and outputs one of the two pairs of the signals. The device is composed of two SPDT switches which share two control signals provided to the gates of the FET of the SPDT switches. The package of the device has eight external electrodes on the back side of the package. The eight external electrodes are configured so that they are aligned symmetrically with respect to the center line of the package. The device requires only a small package space and is suitable for mobile communication application such as cell phone accommodating CDMA and GPS signals.

Abstract: The invention relates to a semiconductor component which is capable of blocking such as an (IGBT), a thyristor, a GTO or diodes, especially schottky diodes. An insulator profile section (10a, 10b, 10c, 10d, 11) provided in the border area of an anode metallic coating (1, 31) is fixed (directly in the edge area) on the substrate (9) of the component. The insulator profile has a curved area (KB) and a base area (SB), said curved area having a surface (OF) which begins flat and curves outward and upward in a steadily increasing manner. A metallic coating (MET1; 30a, 30b, 30c, 30d, 31b) is deposited on the surface (OF). Said coating directly follows the surface curvature and laterally extends the inner anode metallic coating. The upper end of the curved metallic coating (MET1; 30a, 30b . . . ) is distanced and insulated from one of these surrounding outer metallic coatings (MET2; 3) by the surrounding base area (SB) of the insulator profile (10a, . . .

Abstract: On a semiconductor layer 1 consisting of a substrate of a semiconductor single crystal or the like, a metallic layer 2 of a thickness of 20 nm or less is formed. The metallic layer 2 comprises a first area A directly contacting with the semiconductor layer 1, and a second area B that is interposed by an intermediate layer 3 consisting of an insulator, a metal different from the metallic layer 2 or a semiconductor different from the semiconductor layer 1 between the semiconductor 1 and the metallic layer 2, and of a thickness of 10 nm or less. The first area and the second area are different in their Schottky currents, further in their Schottky barrier heights. Any one of the respective areas A and B has an area of nanometer level, and the respective interfaces in each of the areas A and B have an essentially uniform potential barrier, respectively. Such a film-like composite structure contributes to a minute semiconductor device of nanometer level and realization of a new functional device.

Abstract: A Schottky recitfier includes a semiconductor body and a rectifying interface between the semiconductor body and a metal layer. A plurality of trenches are formed in the surface of the semiconductor body, the trenches being separated by mesas, and regions of a conductivity type opposite to the conductivity type of the body is formed along the sidewalls and bottoms of the trenches, the regions forming PN junctions with the rest of the mesas. When the rectifier is reverse-biased, the depletion regions along the PN junctions merge to occupy the entire width of the mesas, thereby protecting the rectifying interface from barrier lowering and resulting current leakage. The use of trenches allows a high aspect ratio, i.e., the ratio of the length to the width of the current “channels” in the mesas (the length being equal to the depth of the trenches), thereby maximizing the area available for current flow and reducing the resistance of the rectifying device in the forward direction.

Abstract: A semiconductor product is described that contains a semiconducting body doped with a first conductivity type, a Schottky contact layer disposed on the semiconducting body and forms a Schottky contact with the semiconducting body, an ohmic contact layer disposed adjacent the Schottky contact layer, and a diode structure disposed laterally beside the Schottky contact. The diode structure has a first region disposed in the semiconducting body. The first region is doped with a second conductivity type and is connected to the Schottky contact layer through the ohmic contact layer. The diode structure has a second region functioning as part of an edge termination and surrounds the Schottky contact and the first region. The second region is disposed in the semiconducting body and is doped with the second conductivity type.

Abstract: An integrated semiconductor circuit device comprising a diode bridge circuit formed of a Schottky barrier diode and a periphery circuit formed of a MOS transistor which are formed on a single silicon substrate, wherein a Schottky barrier, which is a component of the Schottky barrier diode, is made of a silicide layer.

Abstract: The invention relates to a semiconductor component which is capable of blocking such as an (IGBT), a thyristor, a GTO or diodes, especially schottky diodes. An insulator profile section (10a, 10b, 10c, 10d, 11) provided in the border area of an anode metallic coating (1, 31) is fixed (directly in the edge area) on the substrate (9) of the component. The insulator profile has a curved area (KB) and a base area (SB), said curved area having a surface (OF) which begins flat and curves outward and upward in a steadily increasing manner. A metallic coating MET1; 30a, 30b, 30c, 30d, 31b) is deposited on the surface (OF). Said coating directly follows the surface curvature and laterally extends the inner anode metallic coating. The upper end of the curved metallic coating (MET1; 30a, 30b . . . ) is distanced and insulated from one of these surrounding outer metallic coatings (MET2; 3) by the surrounding base area (SB) of the insulator profile (10a, . . .

Abstract: A Schottky diode which provides a structure having no P-N junction while improving voltage resistance against a reverse bias when employed in combination with an insulated gate semiconductor device in particular. In order to attain the aforementioned object, a P-type impurity region having a surface exposed on a surface of an N-type semiconductor substrate functioning as a drain for functioning as a channel region and a gate insulator film covering it are provided. A gate electrode is extended from above the gate insulator film over a first taper of an oxide film. In a Schottky diode rendering the semiconductor substrate a cathode and having a boundary layer as a Schottky region, on the other hand, an anode electrode is extended from above the boundary layer over a second taper of the oxide film existing above an end portion of the boundary layer.

Abstract: The present invention pertains to a carrier layer and a contact enabled by the carrier layer which enables the fabrication of aluminum (including aluminum alloys and other conductive materials having a similar melting point) electrical contacts in multilayer integrated circuit vias, through holes, or trenches having an aspect ratio greater than one. In fact, the structure has been shown to enable such contact fabrication in vias, through holes, and trenches having aspect ratios as high as at least 5:1, and should be capable of filing apertures having aspect ratios up to about 12:1. The carrier layer, in addition to permitting the formation of a conductive contact at high aspect ratio, provides a diffusion barrier which prevents the aluminum from migrating into surrounding substrate material which operates in conjunction with the electrical contact.

Abstract: Trenches are formed in the surface of a second semiconductor layer of a first conductivity type. A semiconductor filled material of a second conductivity type is filled in the trench. A Schottky metal electrode is formed on the surface of the second semiconductor layer and the surface of the semiconductor filled material. A Schottky junction is formed between the Schottky metal electrode and the second semiconductor layer. An ohmic contact is formed between the Schottky metal electrode and the semiconductor filled material. An avalanche breakdown voltage is increased when the impurity concentration of the second semiconductor layer and the semiconductor filled material and the interval between the trenches are set such that both the second semiconductor layer interposed between the semiconductor filled materials and the semiconductor filled material are completely depleted when the Schottky junction is reverse biased.

Abstract: A Schottky diode comprises a semiconductor body of one conductivity type, the semiconductor body having a grooved surface, a metal layer on the grooved surface and forming a Schottky junction with the semiconductor body. The semiconductor body preferably includes a silicon substrate with the grooved surface being on a device region defined by a guard ring of a conductivity type opposite to the conductivity type of the semiconductor body, and a plurality of doped regions at the bottom of grooves and forming P-N junctions with the semiconductor body. The P-N junctions of the doped regions form carrier depletion regions across and spaced from the grooves to increase the reverse bias breakdown voltage and reduce the reverse bias leakage current.

Abstract: The specification describes a Schottky barrier device with a distributed guard ring where the guard ring is spaced from the barrier by an MOS gate so that the guard ring and barrier are connected at low bias by an inversion layer. According to the invention, the MOS gate is used to precisely space the guard ring from the Schottky barrier.

Abstract: A Schottky diode comprises a semiconductor body of one conductivity type, the semiconductor body having a grooved surface, and a metal layer on the grooved surface and forming a Schottky junction with the semiconductor body. The semiconductor body preferably includes a silicon substrate with the grooved surface being on a device region defined by a guard ring of a conductivity type opposite to the conductivity type of the semiconductor body.

Abstract: Semiconductor power devices with improved electrical characteristics are disclosed including rectifying contacts on a specially prepared semiconductor surface with little or no additional exposure to other chemical treatments, with oxide passivation and edge termination at a face of the semiconductor substrate adjacent to and surrounding the power device. The edge termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize a portion of the substrate face and preferably self-aligned to the device. The passivated, edge-terminated devices exhibit improved characteristics relative to passivated devices with characteristics approaching those of the native semiconductor with the additional advantages of passivation protection. Methods for making and using the devices are also disclosed.

Abstract: A dual-metal-trench silicon carbide Schottky pinch rectifier having a plurality of trenches formed in an n-type SiC substrate, with a Schottky contact having a relatively low barrier height on a mesa defined between adjacent ones of the trenches, and a Schottky contact having a relatively high barrier height at the bottom of each trench. The same metal used for the Schottky contact in each trench is deposited over the Schottky contact on the mesa. A simplified fabrication process is disclosed in which the high barrier height metal is deposited over the low barrier height metal and then used as an etch mask for reactive ion etching of the trenches to produce a self-aligned low barrier contact.

Abstract: On a Schottky tunnel junction with Schottky metal as a source, an extremely thin and a high density impurities semiconductor layer having a conduction type different from that of a high density impurities semiconductor constituting the base junction is formed, and height and width of this extremely thin high density impurities semiconductor layer are controlled by adjusting a voltage loaded to a MOS gate formed on this tunnel junction section, so that a main portion of the drain current comprises a carrier passing through the barrier because of the tunnel effect and a carrier moving over this barrier. In addition, a CMOS structure is made to prepare a three-dimensionally or three-dimensionally integrated circuit.

Abstract: A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.

Abstract: A method of producing a semiconductor device includes a semiconductor substrate and a gate embedding layer. A pair of side walls made of insulating layers having a width are formed on the inner surface of a first opening and the gate embedding layer is formed by using the pair of side walls and a first insulating layer as masks so that the embedded portion and the first extending portion are self-aligned and, consequently, the first extending portion is symmetrical with respect to the embedded portion. Accordingly, the first extending portion of the gate electrode is offset toward the drain electrode or source electrode.

Abstract: A Schottky barrier semiconductor device comprises an n+-type semiconductor substrate, an n−-type semiconductor layer grown on the semiconductor substrate by epitaxial growth, and two or more adjacent p+-type semiconductor regions formed on a surface of the semiconductor layer. The device comprises a metal layer having a Schottky barrier on the surface of an active region of the semiconductor layer. The p+-type semiconductor regions are formed so that a ratio of a distance between the adjacent p+-type semiconductor regions to a distance between the bottom surface of the p+-type semiconductor region and the bottom surface of the semiconductor layer may be the ratio of 1 to 1 through 2.

Abstract: An improved diode or rectifier structure and method of fabrication is disclosed involving the incorporation in a Schottky rectifier, or the like, of a dielectric filled isolation trench structure formed in the epitaxial layer adjacent the field oxide layers provided at the edge of the active area of the rectifier, for acting to enhance the field plate for termination of the electric field generated by the device during operation. The trench is formed in a closed configuration about the drift region and by more effectively terminating the electric field at the edge of the drift region the field is better concentrated within the drift region and acts to better interrupt reverse current flow and particularly restricts leakage current at the edges.

Abstract: Inner trenches (11) of a trenched Schottky rectifier (1a; 1b; 1c; 1d) bound a plurality of rectifier areas (43a) where the Schottky electrode (3) forms a Schottky barrier 43 with a drift region (4). A perimeter trench (18) extends around the outer perimeter of the plurality of rectifier areas (43a). These trenches (11, 18) accommodate respective inner field-electrodes (31) and a perimeter field-electrode (38) that are connected to the Schottky electrode (3). The inner field-electrodes (11) are capacitively coupled to the drift region (4) via dielectric material (21) that lines the inner trenches (11). The perimeter field-electrode (38) is capacitively coupled across dielectric material (28) on the inside wall (18a) of the perimeter trench 18, without acting on any outside wall (18b). Furthermore, the inner and perimeter trenches (11, 18) are closely spaced and the intermediate areas (4a, 4b) of the drift region (4) are lowly doped.

Abstract: Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Abstract: When the threshold voltage of a long-channel transistor is set during the same dopant step of a manufacturing process that sets the threshold voltage of a short-channel transistor, the threshold voltage of the long-channel transistor is increased by connecting the long-channel transistor in series with a schottky diode.

Abstract: In order to achieve an aspect of the present invention, in a field effect transistor, a compound semiconductor substrate has an active region, and a gate finger electrode is formed on the active region. Source and drain stripe electrodes are formed on the active region to sandwich the gate finger electrode apart from the gate finger electrode. An extended gate electrode is connected with the gate finger electrode and extended source and drain electrodes are connected with the source and drain stripe electrodes, respectively. A resistance section is provided between the gate finger electrode and the extended gate electrode in the transistor forming region.

Abstract: A high power rectifier device has an N− drift layer on an N+ layer. A number of trench structures are recessed into the drift layer opposite the N+ layer; respective mesa regions separate each pair of trenches. Each trench structure includes oxide side-walls, a shallow P+ region at the bottom of the trench, and a conductive material between the top of the trench and its shallow P+ region. A metal layer contacts the trench structures and mesa regions, forming Schottky contacts. Forward conduction through both Schottky and P+ regions occurs when the device is forward-biased, with the Schottky contact's low barrier height providing a low forward voltage drop. When reversed-biased, depletion regions around the shallow P+ regions and the side-walls provide a potential barrier which shields the Schottky contacts, providing a high reverse blocking voltage and reducing reverse leakage current.

Abstract: An arrangement for providing thermal overload protection for a gated electrode power semiconductor device comprises connecting the gate electrode of the device in a series circuit between the gate electrode terminal applying a bias voltage to the gate electrode and the source region adjoining the channel region controlled by the gate electrode. The series circuit includes an electrical resistor, preferably the gate electrode itself, and a temperature sensitive element blocking current flow through the gate electrode at safe operating temperatures, but allowing current flow, for de-biasing the gate electrode by IR drop through the resistor, when excessive device temperatures are sensed. The temperature sensitive element preferably comprises a reverse biased junction or Schottky barrier formed within the gate electrode.

Abstract: Power semiconductor devices having tapered insulating regions include a drift region of first conductivity type therein and first and second trenches in the substrate. The first and second trenches have first and second opposing sidewalls, respectively, that define a mesa therebetween into which the drift region extends. An electrically insulating region having tapered sidewalls is also provided in each of the trenches. The tapered thickness of each of the electrically insulating regions enhances the degree of uniformity of the electric field along the sidewalls of the trenches and in the mesa and allows the power device to support higher blocking voltages despite a high concentration of dopants in the drift region. In particular, an electrically insulating region lines the first sidewall of the first trench and has a nonuniform thickness Tins(y) in a range between about 0.5 and 1.

Abstract: The semiconductor component, such as a Schottky diode with a low leakage current, has a metal-semiconductor junction between a first metal electrode and the semiconductor. The semiconductor, which is of a first conductivity type, has a defined drift path and a plurality of supplementary zones of a second conductivity type extending from the semiconductor surface into the drift path. A number of foreign atoms in the supplementary zones is substantially equal to a number of foreign atoms in intermediate zones surrounding the supplementary zones and the number of foreign atoms does not exceed a number corresponding to a breakdown charge of the semiconductor.

Abstract: This invention discloses a Schottky barrier rectifier formed in a semiconductor chip of a first conductivity type having a cathode electrode connected thereto near a bottom surface of the semiconductor chip. The Schottky rectifier further includes an epitaxial layer of the first conductivity type of a reduced doping concentration than the semiconductor chip near a top surface of the semiconductor chip. The Schottky rectifier further includes a high resistivity region disposed near peripheral edges of the semiconductor chip containing a reduced dopant concentration than the epitaxial layer. The Schottky rectifier further includes an anode electrode defined by a conductive layer disposed on top over the epitaxial layer wherein the conductive layer having all peripheral edges disposed on top of the high resistivity region. In a preferred embodiment, e.g.