Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is first etched and then annealed in a reducing atmosphere or an inert atmosphere to promote the formation of a desired crystal structure and to remove oxygen rich compounds. The binary metal compound may be a metal oxide. Etching the metal oxide (i.e. molybdenum oxide) may result in the removal of oxygen rich phases and the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer.

Abstract: A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor.

Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.

Abstract: Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.

Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 ?? cm. Advantageously, the electrode layers are conductive molybdenum oxide.

Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a first interlayer insulating film over a substrate; forming a first conductive film over the first interlayer insulating film; forming a ferroelectric film on the first conductive film; forming a second conductive film on the ferroelectric film; forming an upper electrode of a capacitor by patterning the second conductive film; forming a capacitor dielectric film by patterning the ferroelectric film; and forming a lower electrode of the capacitor by patterning the first conductive film, wherein forming the first conductive film includes: forming a lower conductive layer made of a noble metal other than iridium over the first interlayer insulating film; and forming an upper conductive layer on the lower conductive layer, the upper conductive layer being made of a conductive material, which is different from a material for the lower conductive layer, and which is other than platinum.

Abstract: A semiconductor device having a reduced bit line parasitic capacitance and a method of making same is presented. The semiconductor device includes a first, second, third, and fourth interlayer dielectric layers, first and second bit lines, first and second landing plug and first and second storage node contacts. An optional capacitor may be added to complete a CMOS configuration for the semiconductor device. The storage node contacts traverse through the interlayer dielectric layer and are electrically coupled to their respective landing plug contacts. The storage node contacts are deliberately offset, relative to the center of the corresponding landing plug contacts, at a predetermined distance in a direction away from the first bit line. This offsetting aids reducing the parasitic capacitance between the bit line and a storage node.

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract: A thin film transistor for a thin film transistor liquid crystal display (TFT-LCD), an array substrate and manufacturing method thereof are provided. The thin film transistor comprises a source electrode, a drain electrode, and a channel region between the source electrode and drain electrode. A source extension region is connected with the source electrode, a drain extension region is connected with the drain electrode, and the source extension region is disposed opposite to the drain extension region to form a channel extension region therebetween.

Abstract: In a chip-component structure, a monolithic ceramic capacitor is a structure including a predetermined number of substantially flat internal electrodes stacked on each other. An interposer includes a substrate larger than the outer shape of the monolithic ceramic capacitor. The substrate includes a first major surface on which first front electrodes for use in mounting the monolithic ceramic capacitor are disposed and a second major surface on which first back electrodes for use in connecting to an external circuit board are disposed. The interposer includes a depression in its side surface. The depression includes a wall surface on which a connection conductor is disposed. The front surface of the substrate is overlaid with resist films extending along its edges.

Abstract: Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.

Abstract: Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1?x): x (0.01?x?0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.

Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.

Abstract: A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate.

Abstract: A wiring trench is formed in an interlayer insulating film partway in the depth direction of the interlayer insulating film. A via hole is formed extending from the bottom of the wiring trench to the bottom of the interlayer insulating film. A capacitor recess is formed reaching the bottom of the interlayer insulating film. A conductive member is embedded in the wiring trench and via hole. A capacitor is embedded in the capacitor recess, including a lower electrode, a capacitor dielectric film and an upper electrode. The lower electrode is made of the same material as that of the conductive member and disposed along the bottom and side surface of the capacitor recess. A concave portion is formed on an upper surface of the lower electrode, and the capacitor dielectric film covers an inner surface of the concave portion. The upper electrode is embedded in the concave portion.

Abstract: A method of removing non-noble metal oxides from material (e.g., semiconductor material) used to make a microelectronic device includes providing the material comprising traces of the conducting non-noble metal oxides; applying a chemical mixture (or chemical solution) to the material; removing the traces of the non-noble metal oxides from the material; and removing the chemical mixture from the material. The non-noble metal oxides comprise MoOx, wherein x is a positive number between 0 and 3. The chemical solution comprises any one of HNO3-based chemicals, H2SO4-based chemicals, HCl-based chemicals, or NH4OH-based chemicals.

Abstract: A method of manufacturing a device includes: forming a fifth insulating film on a semiconductor substrate having a peripheral circuit region and a memory cell region in which a contact pad is formed; forming a second sacrifice film in the memory cell region in which the fifth insulating film is formed; forming, after the forming of the second sacrifice, a second insulating film in the peripheral circuit region on the semiconductor substrate to have a sidewall coming into contact with the second sacrifice film; forming a third insulating film to cover an upper surface of the second sacrifice film and an upper surface of the second insulating film; forming a hole penetrating through the third insulating film, the second sacrifice film and the fifth insulating film in the memory cell region; forming a lower electrode in the hole; and removing all of the second sacrifice film.

Abstract: A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.

Abstract: The invention provides a method of forming a titanium oxide film having a rutile crystalline structure that has high permittivity. The titanium oxide film having a rutile crystalline structure is produced by forming an amorphous titanium oxide film on an amorphous zirconium oxide film using methyl cyclopentadienyl tris(dimethylamino)titanium as a titanium precursor by an ALD method, and crystallizing the amorphous titanium oxide film by annealing at a temperature of 300° C. or higher.

Abstract: Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.

Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.

Abstract: The semiconductor device comprises a device isolation region formed in a semiconductor substrate, a lower electrode formed in a device region defined by the device isolation region and formed of an impurity diffused layer, a dielectric film of a thermal oxide film formed on the lower electrode, an upper electrode formed on the dielectric film, an insulation layer formed on the semiconductor substrate, covering the upper electrode, a first conductor plug buried in a first contact hole formed down to the lower electrode, and a second conductor plug buried in a second contact hole formed down to the upper electrode, the upper electrode being not formed in the device isolation region. The upper electrode is not formed in the device isolation region, whereby the short-circuit between the upper electrode and the lower electrode in the cavity can be prevented.

Abstract: The present invention is directed to methods and a bio-capacitor sensing device for the detection of toxic chemicals using bacteria. The sensing platform comprises gold interdigitated capacitor with a defined geometry, a layer of carboxy-CNTs immobilized with viable E. coli cells as sensing elements. Also included are methods of making the bio-capacitor device and methods for detecting toxic chemicals that induce cellular stress response. The present innovation discloses the development of a bio capacitor chips immobilized with carboxy-CNTs tethered E. coli bacteria. In addition, the present invention also includes determination of behavior and characteristics of chemically stimulated bacteria on biochip using electric field including frequency and/or amplitude as controlling parameters.

Abstract: Provided is a semiconductor device manufacturing method for a capacitor having a dielectric film which can be formed into a thin film, can be formed at a low temperature, and has a readily controllable property. The manufacturing method includes: forming, on a conductor for serving as one electrode of a capacitor, a manganese oxide film for serving as a dielectric film of the capacitor; and forming, on the manganese oxide film, a conductive film for serving as the other electrode of the capacitor.

Abstract: A semiconductor device includes a dielectric layer, where the dielectric layer includes a metal oxide layer, a metal nitride carbide layer including hydrogen therein, and a reduction prevention layer inserted between the metal nitride carbide layer and the dielectric layer.

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract: A capacitor is fabricated by forming a mold layer of a silicon based material that is not an oxide of silicon, e.g., polysilicon or doped polysilicon, on a substrate, forming an opening through the mold layer, forming a barrier layer pattern along the sides of the opening, subsequently forming a lower electrode in the opening, then removing the mold layer and the barrier layer pattern, and finally sequentially forming dielectric layer and an upper electrode on the lower electrode.

Abstract: To provide a dielectric film having good crystallinity while suppressing an influence of the size effects and preventing the dielectric film from being divided by an Al-doped layer although there is provided the Al-doped layer for improving the leakage characteristics in the dielectric film of a capacitor, the dielectric film has at least one Al-doped layer, and an area density of Al atoms in one layer of the Al-doped layer is smaller than 1.4E+14 atoms/cm2. Further, to achieve the area density, there is employed a combination of formation of a dielectric film using a general ALD method and Al doping using an adsorption site blocking ALD method including adsorbing a blocker molecule restricting an adsorption site of an Al source, adsorbing the Al source, and introducing a reaction gas for reaction.

Abstract: Processes for minimizing contact resistance when using nickel silicide (NiSi) and other similar contact materials are described. These processes include optimizing silicide surface cleaning, silicide surface passivation against oxidation and techniques for diffusion barrier/catalyst layer deposition. Additionally, processes for generating a noble metal (for example platinum, iridium, rhenium, ruthenium, and alloys thereof) activation layer that enables the electroless barrier layer deposition on a NiSi-based contact material are described. The processes may be employed when using NiSi-based materials in other end products. The processes may be employed on silicon-based materials.

Abstract: A semiconductor structure is formed in the metal interconnect structure of an integrated circuit in a method that provides either two individual resistors that are vertically isolated from each other, or a metal-insulator-metal (MIM) capacitor. As a result, both semiconductor resistors and MIM capacitors can be formed in the same process flow.

Abstract: A grain boundary-insulated semiconductor ceramic contains a SrTiO3-based compound as a main component, and a diffusing agent containing a grain boundary insulating agent and a glass component. The grain boundary insulating agent is composed of a material free of lead, the glass component mainly contains a SiO2—X2O-MO—TiO2-based glass material that does not contain boron or lead and in which X represents an alkali metal, and M represents at least one of barium, strontium, and calcium, and the content of the glass component is 3 to 15 parts by weight relative to 100 parts by weight of the grain boundary insulating agent. A component base is composed of the grain boundary-insulated semiconductor ceramic.

Abstract: A smooth electrode is provided. The smooth electrode includes at least one metal layer having thickness greater than about 1 micron; wherein an average surface roughness of the smooth electrode is less than about 10 nm.

Abstract: A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.

Abstract: A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.

Abstract: Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

Abstract: A method for fabricating a capacitor is provided. The method for fabricating a capacitor includes forming a dielectric layer over a lower electrode on a substrate, forming an upper electrode over the dielectric layer, forming a hard mask over the upper electrode, etching the hard mask to form a hard mask pattern, etching the upper electrode to make the dielectric layer remain on the lower electrode in a predetermined thickness, forming an isolation layer along an upper surface of the remaining dielectric layer and the hard mask pattern, leaving the isolation layer having a shape of a spacer on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer, and etching the lower electrode to be isolated.

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device such as a capacitor and DRAM cell. In particular, a bottom electrode upon which a dielectric layer is to be grown may have a ruthenium-based surface. Lattice matching of the ruthenium surface with the dielectric layer (e.g., titanium oxide, strontium titanate or barium strontium titanate) helps promote the growth of rutile-phase titanium oxide, thereby leading to higher dielectric constant and lower effective oxide thickness. The ruthenium-based material also provides a high work function material, leading to lower leakage. To mitigate nucleation delay associated with the use of ruthenium, an adherence or glue layer based in titanium may be employed. A pretreatment process may be further employed so as to increase effective capacitor plate area, and thus promote even further improvements in dielectric constant and effective oxide thickness (“EOT”).

Abstract: Provided is a semiconductor device manufacturing method for a capacitor having a dielectric film which can be formed into a thin film, can be formed at a low temperature, and has a readily controllable property. The manufacturing method includes: forming, on a conductor for serving as one electrode of a capacitor, a manganese oxide film for serving as a dielectric film of the capacitor; and forming, on the manganese oxide film, a conductive film for serving as the other electrode of the capacitor.

Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.

Abstract: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode.

Abstract: A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

Abstract: A method of making a metal capacitor includes the following steps. A dielectric layer having a dual damascene metal interconnection and a damascene capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the damascene capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the dual damascene metal interconnection and the dielectric layer can be prevented.

Abstract: An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.

Abstract: A method of manufacturing a semiconductor device which previously form sidewalls between lower electrodes to prevent bunkers and leaning phenomena during a sacrificial layer dip out process, thereby improving characteristic of the device, is provided. The method includes forming a mesh pattern defining a storage node region over a semiconductor substrate, forming a lower electrode over the semiconductor substrate and sidewalls of the mesh pattern, forming a dielectric layer over the semiconductor substrate including the lower electrode, and forming an upper electrode over the dielectric layer.

Abstract: In a semiconductor device manufacturing method, an amorphous or microcrystalline metal oxide film is formed over a first metal film which is preferentially oriented along a predetermined crystal plane. After that, a ferroelectric film is formed by a MOCVD method. When the ferroelectric film is formed, the metal oxide film formed over the first metal film is reduced to a second metal film and the ferroelectric film is formed over the second metal film. When the ferroelectric film is formed, the amorphous or microcrystalline metal oxide film is apt to be reduced uniformly. As a result, the second metal film the orientation of which is good is obtained and the ferroelectric film the orientation of which is good is formed over the second metal film. After the ferroelectric film is formed, an upper electrode is formed over the ferroelectric film.

Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.

Abstract: A multilayer interconnection substrate is disclosed that includes a multilayer interconnection layer having at least a first interconnection layer and a second interconnection layer stacked with an insulating layer provided therebetween, and a connection via configured to electrically connect the first interconnection layer and the second interconnection layer. The connection via includes an internal conductor and a metal film covering the internal conductor. The internal conductor is an aggregate of metal particles.

Abstract: A method for fabricating a semiconductor device is provided. The method comprising forming a first layer over a substrate and a second layer over the first layer. A patterned masking layer is subsequently provided over the second layer and a patterned second layer with outwardly tapered sidewalls is formed by isotropically etching exposed portions of the second layer. A patterned first layer is the formed by etching the first layer in accordance with the patterned second layer.

Abstract: The present invention relates to a semiconductor and manufacturing method thereof, in which a nano tube structure is vertically grown to form a lower electrode of a cell region and a via contact of peripheral circuit region. Therefore, capacitance of the lower electrode is secured without an etching process for high aspect ratio. Also, the via contact can be formed for corresponding to the height of the lower electrode.