Abstract: To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.

Abstract: A method for manufacturing a semiconductor device includes at least forming a lower electrode made of titanium nitride on a semiconductor substrate, forming a dielectric film comprising zirconium oxide, in which at least the uppermost layer of the dielectric film is formed by an atomic layer deposition (ALD) method on the lower electrode, forming a first protective film on the dielectric film without exceeding the film forming temperature of the ALD method over 70° C., and forming an upper electrode made of a titanium nitride on the first protective film.

Abstract: A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

Abstract: Provided is a semiconductor device manufacturing method for a capacitor having a dielectric film which can be formed into a thin film, can be formed at a low temperature, and has a readily controllable property. The manufacturing method includes: forming an oxide film or an oxynitride film on a conductor for serving as one electrode of a capacitor; forming, on the oxide film or the oxynitride film, a manganese oxide film for serving as a dielectric film of the capacitor; and forming, on the manganese oxide film, a conductive film for serving as the other electrode of the capacitor.

Abstract: A method for producing an electrode for electric double layer capacitors is disclosed which includes: a step of mixing a particulate elastomer and a carbonaceous material with each other in a powdery form, thereby obtaining a powdery mixture; and a step of dry-forming the resultant powdery mixture, thereby forming an electrode layer. With this method, an electrode which enables to form a high-capacity electric double layer capacitor can be produced by simplified steps with high productivity.

Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs.

Abstract: Provided are a method of manufacturing a thin film transistor (TFT) substrate and a method of manufacturing an organic light emitting display apparatus, which increase the capacitance of a capacitor without increasing the probability of short circuits between wires. The method of manufacturing a TFT substrate includes (a) forming a capacitor electrode and a gate electrode on a substrate having a first region and a second region, so that the capacitor electrode is formed to correspond to the first region and the gate electrode is formed in a portion of the second region; (b) forming an interlayer insulating layer to cover the gate electrode and the capacitor electrode; and (c) etching a portion of the interlayer insulating layer in the first region by using a halftone mask to a thickness that is less than a thickness of a portion of the interlayer insulating layer in the second region.

Abstract: An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO2 pillar (25) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer (34) on the dielectric layer covers the etchant openings.

Abstract: The present disclosure includes capacitive sensors and methods of forming capacitive sensors. One capacitive sensor includes a first substrate structure having a first dielectric material formed thereon and electrodes of a first electrode array formed on the first dielectric material. The sensor includes a second substrate structure facing the first substrate structure and having a second dielectric material formed thereon and electrodes of a second electrode array formed on the second dielectric material. The sensor includes a removed portion of the first dielectric material forming a recess between adjacent electrodes of the first electrode array, and the first substrate structure is moveable with respect to the second substrate structure.

Abstract: A capacitor of a semiconductor device and a method for manufacturing the same includes a lower metal layer on and/or over a semiconductor substrate; an insulating layer formed on and/or over the lower metal layer with step difference; and an upper electrode on and/or over the insulating layer pattern, wherein a top corner of the upper electrode is rounded so that a curvature pattern is formed on the top corner of the upper electrode.

Abstract: A method for manufacturing a capacitor bottom electrode of a dynamic random access memory is provided. The method comprises providing a substrate having a memory cell region and forming a polysilicon template layer on the memory cell region of the substrate. A supporting layer is formed on the polysilicon template layer and plural openings penetrating through the supporting layer and the polysilicon template layer are formed and a liner layer is formed on at least a portion of the polysilicon template layer exposed by the openings A conductive layer substantially conformal to the substrate is formed on the substrate. A portion of the conductive layer on the supporting layer is removed so as to form plural capacitor bottom electrodes. Using the polysilicon template layer, the openings with relatively better profiles are formed and the dimension of the device can be decreased.

Abstract: Methods and compositions for the deposition of ternary oxide films containing ruthenium and an alkali earth metal.

Abstract: A fabrication method which forms vertical capacitors in a substrate. The method is preferably an all-dry process, comprising forming a through-substrate via hole in the substrate, depositing a first conductive material layer into the via hole using atomic layer deposition (ALD) such that it is electrically continuous across the length of the via hole, depositing an electrically insulating, continuous and substantially conformal isolation material layer over the first conductive layer using ALD, and depositing a second conductive material layer over the isolation material layer using ALD such that it is electrically continuous across the length of the via hole. The layers are arranged such that they form a vertical capacitor. The present method may be successfully practiced at temperatures of less than 200° C., thereby avoiding damage to circuitry residing on the substrate that might otherwise occur.

Abstract: A method for manufacturing capacitor lower electrodes of a semiconductor memory firstly forms a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs. Then a second stacked structure is formed on the first stacked structure; furthermore, a plurality of trenches extending from a top surface of the second stacked structure to a bottom surface of the first stacked structure are formed and expose the conducting plugs; finally, conductive metal materials and solid conducting cylindrical structures are deposited in the trenches in turn, and the conductive metal materials contact with the conductive plugs and the conducting cylindrical structures. Each conducting cylindrical structure is a capacitor lower electrode. Accordingly, the present invention can increase the supporting stress of the capacitor lower electrodes and further reduce the difficulty in disposing of capacitor upper electrodes and capacitor dielectric layers outside the capacitor lower electrodes.

Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.

Abstract: Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2 and one or more fluorocarbons. The openings formed in the silicon oxide-containing material may be utilized for fabrication of container capacitors, and such capacitors may be incorporated into DRAM.

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

Abstract: Methods of fabricating integrated circuit devices include forming an integrated circuit capacitor on a substrate. This integrated circuit capacitor includes a lower capacitor electrode, a capacitor dielectric region on the lower capacitor electrode and an upper capacitor electrode on the capacitor dielectric region. The upper capacitor electrode has a smaller surface area relative to the lower capacitor electrode. An interlayer insulating layer is formed on the integrated circuit capacitor. This interlayer insulating layer is polished to have a planarized surface thereon that is spaced from an upper surface of the upper capacitor electrode by a first distance and spaced from an upper surface of the lower capacitor electrode by a second distance greater than the first distance.

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes providing a substrate comprising a bottom electrode, forming a dielectric layer positioned on the bottom electrode, and forming a top electrode positioned on the dielectric layer. The dielectric layer includes a silicon nitride film, the silicon nitride film has a plurality of Si—H bonds and a plurality of N—H bonds, and a ratio of Si—H bonds to N—H bonds being equal to or smaller than 0.5.

Abstract: According to the method for manufacturing a semiconductor device, a surface of a lower insulating film (55) is planarized by CMP or the like, and an upper insulating film (56) and a protective metal film (59) are formed on the lower insulating film (55). Accordingly, the upper insulating film (56) and the protective metal film (59) are formed in such a manner they have an excellent coverage and the water/hydrogen blocking capability of the upper insulating film (56) and the protective metal film (59) is maximized.

Abstract: A conductive paste including conductive particles each of which has a size of greater than or equal to 0.1 ?m and less than or equal to 10 ?m, a resin, and a solvent is placed over a first conductor and the solvent is vaporized. In this manner, a second conductor having the conductive particles and a memory layer including the resin between the first conductor and the conductive particles is formed.

Abstract: A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

Abstract: The invention relates to a process for the production of electrolyte capacitors having a low equivalent series resistance and low residual current, electrolyte capacitors produced by this process and the use of such electrolyte capacitors.

Abstract: By forming metal capacitors in the metallization structures of semiconductor devices, complex manufacturing sequences in the device level may be avoided. The process of manufacturing the metal capacitors may be performed on the basis of well-established patterning regimes of modern metallization systems by using appropriately selected etch stop materials, which may enable a high degree of compatibility for forming via openings in a metallization layer while providing a capacitor dielectric of a desired high dielectric constant in the capacitor.

Abstract: A method of forming a semiconductor memory device includes sequentially forming an etch stop layer and then a mold layer, forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks, removing the first mask patterns and second mask patterns, filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures, and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures.

Abstract: A film structure including at least one film is formed on a face of a semiconductor substrate and then a first mask with a pattern is formed on the film structure. A second mask is formed so as to cover the first mask over a bevel region. The film structure is etched using the first and second masks and thereafter the remaining first and second masks are removed away.

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract: A method of manufacturing a capacitor of a semiconductor device includes forming a high-k dielectric pattern on a semiconductor substrate, the high-k dielectric pattern having a pillar shape including a hole therein, forming a lower electrode in the hole of the high-k dielectric pattern, locally forming a blocking insulating pattern on an upper surface of the lower electrode, and forming an upper electrode covering the high-k dielectric pattern and the blocking insulating pattern.

Abstract: Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer.

Abstract: A capacitor is formed over a semiconductor substrate. The capacitor includes a lower electrode, a capacitor dielectric film and an upper electrode in this order recited, and has an area S equal to or larger than 1000 ?m2 and L/S equal to or larger than 0.4 ?m?1, where S is an area of a capacitor region in which the lower and upper electrodes face each other across the dielectric film, and L is a total length of a circumference line of the capacitor region.

Abstract: According to one embodiment, a scalable integrated MIM capacitor in a semiconductor die includes a high-k dielectric segment over a substrate and a metal segment over the high-k dielectric segment, where the metal segment forms a capacitor terminal of the integrated MIM capacitor. The capacitor further includes a filler laterally separating consecutive capacitor terminals, where the filler can be used as a capacitor dielectric of the integrated MIM capacitor. In one embodiment, the metal segment comprises a gate metal. In another embodiment, the integrated MIM capacitor is formed substantially concurrently with one or more transistors without requiring additional fabrication process steps.

Abstract: Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source.

Abstract: A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM is disclosed. First, form a stacked structure. Second, form a photoresist layer on an upper oxide layer and then etch them. Third, deposit a polysilicon layer onto the upper oxide layer and the nitride layer. Fourth, deposit a nitrogen oxide layer on the polysilicon layer and the upper oxide layer. Sixth, partially etch the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias. Seventh, oxidize the polysilicon layer to form a plurality of silicon dioxides surround the vias. Eighth, etch the nitride layer, the dielectric layer and the lower oxide layer beneath the vias. Ninth, form a metal plate and a capacitor lower electrode in each of the vias. Tenth, etch the nitrogen oxide layer, the polysilicon layer, the nitride layer and the dielectric layer.

Abstract: The method provides a semiconductor structure and method for forming such a structure that provides for protection for resistive layers formed within the structure from contamination from adjacent layers. By encapsulating the resistive layer in a material that is resistant to the diffusion of contaminants it is possible to protect the resistive material during the processing required to manufacture the structure.

Abstract: An integrated circuit is provided that includes a fully depleted semiconductor device and a capacitor present on a semiconductor on insulator (SOI) substrate. The fully depleted semiconductor device may be a finFET semiconductor device or a planar semiconductor device. In one embodiment, the integrated circuit includes a substrate having a first device region and a second device region. The first device region of the substrate includes a first semiconductor layer that is present on a buried insulating layer. The buried insulating layer that is in the first device region is present on a second semiconductor layer of the substrate. The second device region includes the second semiconductor layer, but the first semiconductor layer and the buried insulating layer are not present in the second device region. The first device region includes the fully depleted semiconductor device. A capacitor is present in the second device region.

Abstract: A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.

Abstract: A method for manufacturing a semiconductor device comprises depositing an absorption barrier layer of a dielectric film on a semiconductor substrate including a bottom electrode contact plug so as to separate the dielectric films between capacitors without having any influence of a bias of the adjacent capacitor, thereby improving a refresh characteristic of cells.

Abstract: A method for producing an integrated device including an MIM capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate; the first plate has a first melting temperature. The method further includes depositing a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate; the layer of insulating material is deposited at a process temperature being lower than the first melting temperature. The method further includes forming a second conductive layer including a second plate of the capacitor on a portion of the layer of insulating material corresponding to the dielectric layer. In the solution according to an embodiment of the invention, the first melting temperature is higher than 500° C.

Abstract: A method for fabricating a crown-shaped capacitor includes providing a first dielectric layer with a protective pillar formed thereover, including a first conductive layer, a protective layer, and a mask layer. A second conductive layer is formed over a sidewall of the protective pillar. A first capacitance layer and a third conductive layer are formed over the first dielectric layer. A sacrificial layer is formed over the third conductive layer. The sacrificial layer, the third conductive layer, the first capacitance layer, the second conductive layer, and the mask layer above the protective layer are partially removed. The second conductive layer and the third conductive are removed to form a recess adjacent to the first capacitance layer. The protective layer is removed and an opening is formed to expose the first and second conductive layers. A second capacitance layer and a fourth conductive layer are formed in the opening. The sacrificial layer is removed to expose the third conductive layer.

Abstract: Processes for minimizing contact resistance when using nickel silicide (NiSi) and other similar contact materials are described. These processes include optimizing silicide surface cleaning, silicide surface passivation against oxidation and techniques for diffusion barrier/catalyst layer deposition. Additionally, processes for generating a noble metal (for example platinum, iridium, rhenium, ruthenium, and alloys thereof) activation layer that enables the electroless barrier layer deposition on a NiSi-based contact material are described. The processes may be employed when using NiSi-based materials in other end products. The processes may be employed on silicon-based materials.

Abstract: A method for manufacturing a semiconductor device, includes: forming an insulating film on a substrate; selectively removing the insulating film, so as to form a groove including a first groove area having a first depth and a second groove area having a second depth, the second depth being smaller than the first depth; infusing a conductive liquid material into the first groove area and the second groove area; treating the conductive liquid material, so as to form a first conductive film in the first groove area and a second conductive film in the second groove area; and forming a second insulating film on the first and the second conductive films, followed by forming a third conductive film on the second insulating film.

Abstract: Provided are a semiconductor device, a method of fabricating the same, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device includes a lower electrode, a rutile state lower vanadium dioxide layer on the lower electrode, a rutile state titanium oxide on the lower vanadium dioxide layer, and an upper electrode on the titanium oxide layer.

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.

Abstract: A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in the via. A back side dielectric layer is then depositing, covering the exposed via. A small opening is then formed, and the disposable material is removed, for example by an isotropic etch process. The via may now be filled with a metal and used as a conductor or a dielectric material. The via may also be left unfilled to be used as an air gap.

Abstract: A method for fabricating a reservoir capacitor of a semiconductor device where a first peripheral circuit region and a second peripheral circuit region are defined comprises: forming a gate on an upper portion of a semiconductor substrate of the second peripheral circuit region; forming an interlayer insulating film on the entire upper portion of the semiconductor substrate including the gate; etching the interlayer insulating film of the second peripheral circuit region to form a bit line contact hole; forming a bit line material and a sacrificial film on the upper portion of the interlayer insulating film including the bit line contact hole; and etching the sacrificial film of the first peripheral circuit region to form a trench that exposes the bit line material.

Abstract: A method for manufacturing a capacitor includes the steps of: sequentially laminating, on a substrate, a lower electrode layer, a dielectric layer and an upper electrode layer; forming a patterned mask layer on the upper electrode layer; patterning at least the upper electrode layer and the ferroelectric layer using the mask layer as a mask; removing the mask layer; and conducting a plasma treatment to contact plasma with an exposed surface of the dielectric layer.

Abstract: A method of forming a semiconductor device includes forming a hole in an insulating film, forming a first conductive film in the hole, removing at least a portion of the insulating film around the first conductive film, and reducing a thickness of the first conductive film to produce a second conductive film.

Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.

Abstract: A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration, and in subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.