Abstract: A manufacturing method for an organic light emitting display includes forming a first electrode on a target substrate and forming a bank layer including an aperture region that exposes the first electrode; bonding the target substrate and a medium substrate oppositely spaced apart from a top portion of the target substrate and having an organic material layer, an absorption layer, a reflective layer, and a donor substrate sequentially arranged thereon; transferring an organic material layer onto the first electrode exposed in the bank layer by irradiating a laser onto the medium substrate to form an organic light emitting layer; and separating the target substrate and the medium substrate from each other and forming a second electrode on the organic light emitting layer formed on the target substrate, wherein the reflectivity of the absorption layer is lower than the reflectivity of the reflective layer.

Abstract: The present invention is drawn to a layered organic device, and a method of forming the same. The method includes steps of applying a first solvent-containing organic layer to a substrate and removing solvent from the first solvent-containing organic layer to form a first solidified organic layer. Additional steps include applying a second solvent-containing organic layer to the first solidified organic layer and removing solvent from the second solvent-containing organic layer to form a second solidified organic layer. The first solidified organic layer can be crosslinked, which suppresses negative impact to components in the first solidified organic layer when the solvent of the second solvent-containing organic layer is deposited on the first solidified organic layer.

Abstract: An AMOLED display device includes a substrate, a device layer, a flat layer, a first, a second, and a third color filter layers, a first, a second, and a third pixel electrodes, a first, a second and a third organic light emitting layers. The device layer on the substrate includes active devices. The flat layer on the device layer includes contact window openings. The first color filter layer on the flat layer has a first pixel area and a first opening configured above a part of the contact window openings. The second color filter layer on the flat layer has a second pixel area and a second opening configured above a part of the contact window openings. The third color filter layer on the flat layer has a third pixel area and a third opening configured above a part of the contact window openings.

Abstract: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.

Abstract: This invention discloses that photolithography can be made compatible with the production of electronic devices containing sensitive materials, if the sensitive materials are over-coated with an ultra-thin layer of non-reactive materials (e.g. inorganic oxides) before undergoing photolithographic patterning. This protecting layer isolates the sensitive materials from solvents and etching reactants used in photolithographic patterning, and does not need to be removed from the sensitive materials after patterning is completed. This invention enables photolithography to be applied to the production of electronic devices containing sensitive materials, facilitating the development of commercially viable production processes for these devices.

Abstract: A method of manufacturing an organic light emitting display is disclosed. The method includes forming a first electrode and a bank layer including an opening area exposing the first electrode on a target substrate, forming a medium substrate including an organic layer and an absorbing layer on the target substrate, forming a mask including an opening corresponding to the opening area of the bank layer on the medium substrate, emitting light on the medium substrate through the mask and transferring the organic layer on a portion of the first electrode exposed by the bank layer to form an organic light emitting layer on the target substrate, and forming a second electrode on the organic light emitting layer.

Abstract: A method for manufacturing a solid-state image capturing apparatus including a pixel array constituted of a plurality of pixels, is provided, where each of the plurality of pixels includes a photoelectric conversion section, the method comprising the steps of: forming an impurity diffusion area in a surface area of a semiconductor substrate; and forming a plurality of different impurity diffusion areas in the surface area of the semiconductor substrate, other than the impurity diffusion area constituting the photoelectric conversion section.

Abstract: An organic semiconductor device is provided which includes an organic semiconductor layer and an insulating layer. The insulating layer is made of a cured material formed from a composition containing a resin and a crosslinking agent. The resin contains an organic resin having a hydroxyl group. The crosslinking agent contains a compound having at least two crosslinking groups. At least one of the crosslinking groups is a methylol group or an NH group. The composition contains the crosslinking agent in the range of 15 to 45 percent by weight relative to 100 parts by weight in total of the resin and the crosslinking agent.

Abstract: The present invention is directed to a method for manufacturing a semiconductor device by forming an ultraviolet radiation absorbing film of a silicon-rich film above a semiconductor substrate, measuring an extinction coefficient of the ultraviolet radiation absorbing film of a silicon-rich film for ultraviolet radiation, and etching the ultraviolet radiation absorbing film of a silicon-rich film under an etching condition using an oxygen gas flow rate corresponding to the extinction coefficient.

Abstract: A thin film transistor includes a source electrode and a drain electrode which are disposed to face each other, an organic semiconductor layer provided at least between the source electrode and the drain electrode, a plurality of gate lines extending over the source electrode, the organic semiconductor layer, and the drain electrode, and a gate insulating layer interposed between the source electrode, the drain electrode, and the organic semiconductor layer and the plurality of gate lines.

Abstract: A method (and apparatus) of replicating a pattern on a structure, includes using imprint lithography to replicate a pattern formed on a first structure onto a portion of a second structure.

Abstract: A method for manufacturing an organic light emitting diode includes a lower substrate, a luminous element provided with upper and lower electrodes, and disposed on the lower substrate, a shielding layer disposed on the luminous element for shielding outer moisture, the shielding layer being formed of at least one layer, and an upper substrate disposed on the shielding layer.

Abstract: A method for manufacturing a flexible display, includes forming a gate line including a plurality of gate electrodes with a first interval on a substrate having a coefficient of thermal expansion, sequentially depositing both a gate insulating layer covering the gate line and a semiconductor layer, etching the semiconductor layer by using a mask having a plurality of semiconductor patterns with a second interval different from the first interval to form a semiconductor, forming both a data line including a source electrode and a drain electrode on the semiconductor and the gate insulating layer, and forming a pixel electrode coupled with the drain electrode.

Abstract: The present invention provides a production method of a semiconductor device, involving formation of a flattening layer and easy process for layers formed on a semiconductor layer, and also provides a semiconductor device preferably produced by such a production method. The present invention further provides an exposure apparatus preferably used in such a production method.

Abstract: A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.

Abstract: A lower-layer film to which a fluorine-doped polymer is added is formed on a film to be processed. The lower-layer film is baked. An intermediate film is formed on the lower-layer film. A resist film is formed on the intermediate film. The resist film is baked. A resist protection film is formed. The resist film is immersion-exposed. The resist film is developed to form a resist pattern.

Abstract: A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first conductive layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing (CMP) stop layer and the underlying first conductive layer to expose the first insulating layer, thereby leaving a patterned chemical mechanical polishing (CMP) stop layer and a patterned first conductive layer; forming a second insulating layer on the patterned chemical mechanical polishing (CMP) stop layer, filling in the openings; performing a planarization process to remove a portion of the second insulating layer until the patterned chemical mechanical polishing (CMP) stop layer is exposed, thereby leaving a remaining second insulating layer in the openings; removing the patterned chemical mechanical polishing (CMP) stop layer.

Abstract: A method of making a device includes forming an underlying mask layer over an underlying layer, forming a first mask layer over the underlying mask layer, patterning the first mask layer to form first mask features, undercutting the underlying mask layer to form underlying mask features using the first mask features as a mask, removing the first mask features, and patterning the underlying layer using at least the underlying mask features as a mask.

Abstract: An organic electroluminescent display device having an organic thin film transistor (OTFT) and a method of fabricating the same is disclosed. The display device can maintain an insulation property of a TFT and concurrently, ensure a sufficient capacitance by using an organic insulating layer for a gate insulating layer and using an inorganic insulating layer for a capacitor dielectric. In one embodiment, the organic electroluminescent display device includes a substrate having a capacitor region and a transistor region, a TFT formed in the transistor region of the substrate, and having a gate electrode, an organic semiconductor layer, a source electrode, and a drain electrode, a capacitor formed in the capacitor region of the substrate, and having a lower electrode and an upper electrode, and a display element connected to one of source/drain electrodes of the TFT.

Abstract: There is a problem in that when the demand accuracy with respect to a semiconductor pattern dimension comes close to a resist molecule size with miniaturization, the device performance is deteriorated due to edge roughness of a resist pattern to exert a bad influence on the system performance. The present invention overcomes the problem by the procedure in which super-molecules which are small in dimension as compared with the conventional polymers are used as main components, the reaction number required for the change of molecule solubility is made constant and as large as possible, and an acid generator is made clathrate or combinatory n super molecules to make an acid catalyst concentration large. As a result, it is possible to form a pattern of molecular accuracy with high productivity even with respect to the pattern dimension less than 50 nm, thereby realizing the high performance system.

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract: A method of manufacturing an organic light emitting display is disclosed. The method includes forming a first electrode and a bank layer including an opening area exposing the first electrode on a target substrate, forming a medium substrate including an organic layer and an absorbing layer on the target substrate, forming a mask including an opening corresponding to the opening area of the bank layer on the medium substrate, emitting light on the medium substrate through the mask and transferring the organic layer on a portion of the first electrode exposed by the bank layer to form an organic light emitting layer on the target substrate, and forming a second electrode on the organic light emitting layer.

Abstract: An etching method which makes it possible to obtain a desired etching shape with ease, and a computer-readable storage medium storing a program for implementing the method. The etching method is executed by a substrate processing apparatus that performs plasma processing on a semiconductor wafer by plasma. The apparatus comprises a substrate accommodating chamber for accommodating the semiconductor wafer which has an oxide film and a resist film formed on the oxide film, and an upper electrode plate disposed in the substrate accommodating chamber and exposed in a processing space in the substrate accommodating chamber. At least part of the upper electrode plate is formed of a silicon-containing material. The upper electrode plate is sputtered by plasma, and the oxide film is etched by plasma.

Abstract: A method of fabricating a donor substrate for a laser induced thermal imaging (LITI) process. A base substrate is prepared. A light-to-heat conversion layer is formed on the base substrate. A buffer layer is formed on the light-to-heat conversion layer. The surface roughness of the buffer layer is increased by treating the surface of the buffer layer. A transfer layer is formed on the surface-treated buffer layer. By using the donor substrate, a patterning process can be performed better during the fabrication of the OLED.

Abstract: For integrated circuit fabrication, at least one spacer support structure is formed in a first area over a semiconductor substrate, and a mask material is deposited on exposed surfaces of the spacer support structure and on a second area over the semiconductor substrate. A masking structure is formed on a portion of the mask material in the second area, and the mask material is patterned to form spacers on sidewalls of the spacer support structure and to form a mask pattern under the masking structure. The spacer support structure and the masking structure are comprised of respective high carbon content materials that have been spin-coated and have substantially a same etch selectivity.

Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first polymer layer and a second polymer layer over an etch target layer. The second polymer layer is patterned at a first substrate temperature. The first polymer layer is etched at a second substrate temperature using an etch gas that does not include oxygen (O2). The first polymer layer is etched using the patterned second polymer layer as an etch mask. The etch target layer is then etched using the etched first polymer layer and the etched second polymer layer as an etch mask.

Abstract: A method of forming a porous low dielectric constant (low-k) dielectric film on a substrate is described, wherein the dielectric constant of the low-k dielectric film is less than a value of approximately 4. The method comprises exposing the low-k dielectric film to infrared (IR) radiation and adjusting a residual amount of cross-linking inhibitor, such as pore-generating material, within the low-k dielectric film.

Abstract: A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.

Abstract: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.

Abstract: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.

Abstract: Organic FETs are produced having high mobilities in the accumulation mode and in the depletion mode. Significantly higher mobility is obtained from FETs in which RR-P3HT film is applied by dip-coating to a thickness of only about 20 ? to 1 ?m. It was found that the structural order of the semiconducting polymer at the interface between the semiconducting polymer and the SiO2 gate-insulator is important for achieving high carrier mobility. Heat-treatment under an inert atmosphere also was found to increase the on/off ratio of the FET.

Abstract: A silica-based coating film on a substrate surface is prepared by forming a reaction mixture comprising a tetraalkoxysilicon compound (A) and/or an alkyl/alkoxy silane compound (B), an alcohol (C), and oxalic acid (D), in such ratios that the amount of alcohol (C) ranges from 0.5 to 100 mols per mol of all alkoxy groups present in the silicon compounds (A) and (B), and the amount of oxalic acid (D) ranges from 0.2 to 2 mols per mol of all alkoxy groups in the silicon compounds (A) and (B), and while maintaining the mixture at a SiO2 concentration ranging from 0.5 to 11%, as calculated from silicon atoms in the mixture, by means of the alcohol (C); heating the reaction mixture at a temperature ranging from 50 to 180° C.

Abstract: Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer.

Abstract: An organic electroluminescent device has an anode formed on a substrate, a hole injection layer formed on the anode, wherein the hole injection layer is subjected with an electron shower treatment, an emitting layer formed on the hole injection layer, and a cathode formed on the emitting layer. With the electron shower treatment, impurities from the hole injection layer can be removed, and electrical surface resistance of the hole injection layer cab be increased so that performance and life characteristics of the organic electroluminescent device are improved.

Abstract: A method for fabricating an AMOLED display device is provided. A substrate is provided. A device layer having multiple active devices is formed on the substrate. A flat layer is configured on the device layer. A first, a second and a third color photoresistant layers are respectively configured on the flat layer and are patterned to form a first, a second and a third color filter layers. The first, the second and the third color filter layers respectively define a first, a second and a third pixel areas and are used for etching masks to etch the flat layer for exposing parts of the active devices. A first, a second and a third pixel electrode are respectively configured in the mentioned pixel areas and are electrically connected with the active devices. A first, a second and a third organic light emitting layers are respectively configured on the mentioned pixel electrodes.

Abstract: A method of manufacturing a device includes doping a low voltage threshold area and a high voltage threshold area. Gate structures are formed over the low voltage threshold and high voltage threshold areas while protecting the gate structure over the low voltage threshold area. A silicidation process is performed over the high voltage threshold area while the gate structure over the low voltage threshold area remains protected. Siliciding includes depositing metal on the gate of the high voltage threshold area and annealing the metal, the metal is deposited either by CVD or sputtering followed by anneal to fully suicide the gate structure of the high voltage threshold area. The metal, preferably cobalt or nickel is deposited to a thickness of approximately 500 ?, annealed for about 3 minutes at about 400° C.

Abstract: Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their symmetric upper portions may be used to accurately etch well-defined, high aspect ratio features in the underlying substrate. Some disclosed methods also enable simultaneous formation of hardmask structures of various dimensions, of both conventional and subresolution size, to enable etching structural features of different sizes in the underlying substrate.

Abstract: The invention includes masking methods. In one implementation, a masking material which includes boron doped amorphous carbon is formed over a feature formed on a semiconductor substrate. The masking material includes at least about 0.5 atomic percent boron. The masking material is substantially anisotropically etched effective to form an anisotropically etched sidewall spacer which includes the boron doped amorphous carbon on a sidewall of the feature. The substrate is then processed proximate the spacer while using the boron doped amorphous carbon-including spacer as a mask. After processing the substrate proximate the spacer, the boron doped amorphous carbon-including spacer is etched from the substrate. Other implementations and aspects are contemplated.

Abstract: A patterning method comprising (a) providing a substrate having a sacrificial layer made of a first material, partially or totally formed on the substrate; (b) forming pattern grooves, which are free from the first material and have a line width of a first resolution or lower, on the sacrificial layer by using a first means; (c) filling the pattern grooves with a second material by using a second means; and (d) removing the first material present in a remaining sacrificial layer by way of irradiation or heating, wherein the first material has a threshold fluence of less than a threshold fluence of the second material, the first material is removed in step (d) under a dose ranging from the threshold fluence of the first material to that of the second material, and the pattern is formed on the substrate by the second material.

Abstract: A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.

Abstract: When a via-hole 26 and an interconnection trench 32 are formed in an interconnection films 16, 18 by using as a mask a hard mask 20 covering the region except via-hole forming region, and a hard mask 22 covering the region except an interconnection trench forming region, the hard mask 20 is isotropically etched to expose the upper surface of the inter-layer insulating film 18 at a periphery of the via-hole forming region and leave the hard mask 20 in the interconnection trench forming region except the periphery, and then the hard mask 20 and the insulating films 18, 16 are anisotropically etched, whereby the via-hole 26 having increased-width portion 34 at the upper part, and the interconnection trench 32 connected to the via-hole 26 at the increased-width portions 26 are formed.

Abstract: Provided is a method of forming an oxide-based nano-structured material including growing a nano-structured material using a nano-nucleus having the same composition as the desired oxide-based nano-structured material. A solution is coated on a substrate, the solution including: an organic precursor containing M which is a transition metal or a semi metal; and an organic solvent in which the organic precursor is dissolved. A nano-nucleus having a composition of MxOy is formed on the substrate by annealing the substrate. A nano-structured material having a composition of MxOy is formed by growing the nano-nucleus while supplying a reaction precursor containing M into the nano-nucleus, and the nano-structured material is annealed.

Abstract: The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A layer comprising amorphous carbon is provided over the substrate outer surface. A masking layer is provided outwardly of the amorphous carbon-comprising layer. A resist layer is provided outwardly of the masking layer. At least a portion of the peripheral region of the outer surface includes the amorphous carbon-comprising layer and the resist layer, but is substantially void of the masking layer. The amorphous carbon-comprising layer is patterned using the resist layer and the masking layer effective to form a mask over the semiconductor substrate. After the patterning, the semiconductor substrate is processed inwardly of the mask through openings formed in the mask.

Abstract: The present method prevents malfunctions in switching caused by a light leakage current in an active matrix type thin film transistor substrate for a liquid crystal display and prevents display failures, by selectively disposing a self assembled monolayer film in a gate electrode-projected region of the surface of an insulator film with high definition, and by selectively improving the orientation order of an organic semiconductor film only in the gate electrode-projected region without improving the order at an irradiated portion with light outside the gate electrode-projected region.

Abstract: An object of the present invention is to provide an EL display device having high operation performance and reliability. A third passivation film 45 is disposed under the EL element 203 comprising a pixel electrode (anode) 46, an EL layer 47 and a cathode 48, and diffusion of alkali metals from the EL element 203 formed by ink jet method into TFTs is prevented. Further, the third passivation film 45 prevents penetration of moisture and oxygen from the TFTs, and suppress degradation of the EL element 203 by dispersing the heat generated by the EL element 203.

Abstract: A method for forming a pattern in a semiconductor device includes performing a double exposure process for a multifunctional hard mask layer over a semiconductor substrate using a line/space mask to form a multifunctional hard mask layer pattern having a first contact hole region. The multifunctional hard mask layer pattern is subjected to a resist flow process to form a multifunctional hard mask layer pattern having a second contact hole region with rounded edges, where the size of the second contact hole region is smaller than that of the first contact hole region.

Abstract: A chemical solution coating method includes: a first step of disposing a semiconductor substrate on a substrate supporting unit with a first face to be coated with a chemical solution facing upward; a second step of moving a chemical solution spraying member for spraying the chemical solution to an initial position which is positioned in the vicinity of the first face of the semiconductor substrate and where the chemical solution is to be applied; and a third step of moving the chemical solution spraying member from the initial position in accordance with a predetermined travel pattern and, simultaneously, spraying the chemical solution from the chemical solution spraying member toward the first face of the semiconductor substrate.

Abstract: A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.

Abstract: Dielectric materials comprising release agents are described. Also described are a process for improving the proccessability of dielectric materials during hot embossing, substrates prepared by hot embossing, and integrated-circuit packages comprising the improved substrate.

Abstract: A method (and apparatus) of replicating a pattern on a structure, includes using imprint lithography to replicate a pattern formed on a first structure onto a portion of a second structure.