Involving Dielectric Removal Step (epo) Patents (Class 257/E21.244)
  • Patent number: 8513033
    Abstract: A design method of a semiconductor device includes setting an inspection region of layout data generated based on circuit data, calculating an area ratio of a first area to a second area, the first area indicating an area of the inspection region, the second area indicating a sum of a surface area of a plane that a first member contacts with a second member, the second member contacting with the first member constituting a circuit element included in the inspection region, the second member further having different heat reflective properties from the first member, and arranging a dummy element in the layout data so that the area ratio is within a predetermined range in each inspection region of the layout data.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: August 20, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Naoyoshi Kawahara, Shinya Maruyama, Shinichi Miyake
  • Patent number: 8415232
    Abstract: A wafer is divided into individual devices along division lines formed on the front side of the wafer. The devices are respectively formed in a plurality of regions partitioned by the division lines. A protective member is provided on the front of the wafer, and the back of the wafer is ground to a predetermined thickness. A laser beam is applied to the wafer from the back side of the wafer along the division lines with the focal point of the laser beam set inside the wafer at a position corresponding to each division line, thereby forming a plurality of modified layers inside the wafer along the division lines. The wafer is divided along the modified layers into the individual devices, and the back side of the wafer is ground to remove the modified layers and reduce the thickness of each device to the finished thickness.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: April 9, 2013
    Assignee: Disco Corporation
    Inventors: Keiichi Kajiyama, Takatoshi Masuda
  • Patent number: 8329552
    Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
  • Publication number: 20120052692
    Abstract: Methods for fabricating porous low-k materials are provided, such as plasma enhanced chemically vapor deposited (PE-CVD) and chemically vapor deposited (CVD) low-k films used as dielectric materials in between interconnect structures in semiconductor devices. More specifically, a new method is provided which results in a low-k material with significant improved chemical stability and improved elastic modulus, for a porosity obtained.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 1, 2012
    Applicant: IMEC
    Inventors: Mikhail Baklanov, Quoc Toan Le, Laurent Souriau, Patrick Verdonck
  • Patent number: 8124535
    Abstract: A method of fabricating a solar cell is provided. A saw damage removal process is performed on a silicon substrate. A dry surface treatment is performed to a surface of the silicon substrate on form an irregular surface. A metal-activated selective oxidation is performed to the irregular surface. By using an aqueous solution, the irregular surface is etched to form a nanotexturized surface of the silicon substrate. A dopant diffusion process is performed on the silicon substrate to form a P-N junction. An anti-reflection layer is formed on the silicon substrate. An electrode is formed on the silicon substrate.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: February 28, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Ching-Hsi Lin, Chien-Rong Huang, Dimitre Zahariev Dimitrov
  • Patent number: 8093678
    Abstract: A semiconductor device. The device includes an active region isolated by an isolation structure on a substrate, and a dielectric layer overlying the active region and the isolation structure. The dielectric layer comprises a lower part overlying the active region beyond the boundary of the active region and the isolation structure, and a protruding part overlying the boundary of the active region and the isolation structure.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: January 10, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Shan Lu, Feng-Liang Lai, Shean-Ren Horng
  • Patent number: 8017464
    Abstract: As a method for constituting a pre-metal interlayer insulating film, such method is considered as forming a CVD silicon oxide-based insulating film having good filling properties of a silicon oxide film by ozone TEOS, reflowing the film at high temperatures to planarize it, then stacking a silicon oxide film having good CMP scratch resistance by plasma TEOS, and, further, planarizing it by CMP. However, it was made clear that, in a process for forming a contact hole, crack in the pre-metal interlayer insulating film is exposed in the contact hole, into which barrier metal intrudes to cause short-circuit defects. In the present invention, in the pre-metal process, after forming the ozone TEOS film over an etch stop film, the ozone TEOS film is once etched back so as to expose the etch stop film over a gate structure, and, after that, a plasma TEOS film is formed over the remaining ozone TEOS film, and then the plasma TEOS film is planarized by CMP.
    Type: Grant
    Filed: September 12, 2009
    Date of Patent: September 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masao Sugiyama, Yoshiyuki Kaneko, Yoshinori Kondo, Masayoshi Hirasawa
  • Publication number: 20110201209
    Abstract: Methods and systems for planarization of a die-to-wafer integration. A planarization coating may be applied to the die-to-wafer assembly, and a planarization plate may be used in the planarization process. The planarization plate may include perforations configured to allow a portion of the planarization coating to extrude through the planarization plate.
    Type: Application
    Filed: February 17, 2010
    Publication date: August 18, 2011
    Inventors: Sharath Hosali, Gregory Smith, Larry Smith
  • Patent number: 7993960
    Abstract: Provided are an electronic device including a bank structure and a method of manufacturing the same. The method of manufacturing the electronic device requires a fewer number of processes and comprises a direct patterning of insulating layers, such as fluorinated organic polymer layers, is possible using cost-efficient techniques such as inkjet printing.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: August 9, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Arthur Mathea, Joerg Fischer, Marcus Schaedig
  • Patent number: 7960821
    Abstract: An integrated circuit device and method of making the integrated circuit device are disclosed. An exemplary apparatus includes: a semiconductor layer; and a dielectric layer on the semiconductor layer, the dielectric layer having conductive vias and dummy vias formed therein, wherein the conductive vias and dummy vias extend varying distances into the dielectric layer, the conductive vias extending through the dielectric layer to the semiconductor layer, and the dummy vias extending through the dielectric layer to a distance above the semiconductor layer.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: June 14, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei Shun Chen, Chin-Hsiang Lin, Vencent Chang, Lawrence Lin, Lai Chien Wen, Jhun Hua Chen
  • Patent number: 7943470
    Abstract: The semiconductor device according to the present invention includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a silicon film in contact with an inner surface of the isolation trench, a silicon film in contact with an outer surface of the isolation trench, and an insulation film provided between the silicon films. According to the present invention, the silicon film within the isolation trench can be substantially regarded as a part of the silicon substrate. Therefore, even when the width of the isolation trench is increased to increase the etching rate, the width of the insulation film becoming a dead space can be made sufficiently small. Consequently, the chip area can be decreased.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: May 17, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Shiro Uchiyama
  • Publication number: 20110070745
    Abstract: A polishing method includes performing conditioning process of injecting a conditioning agent onto a surface of a non-foam polishing pad arranged on a polishing table at a predetermined pressure, and polishing a surface of a polishing target while supplying a polishing slurry containing oxide particles and a surfactant onto the polishing pad, wherein an average of a residual cerium amount is equal to or smaller than 0.35 at % when a plurality of measurement regions, each 200 ?m? in area including the surface of the polishing pad, in a cross section of the polishing pad are measured after the conditioning process.
    Type: Application
    Filed: May 6, 2010
    Publication date: March 24, 2011
    Inventors: Yukiteru MATSUI, Satoko Seta, Takatoshi Ono, Hajime Eda
  • Patent number: 7897488
    Abstract: A wafer dividing method for dividing a wafer having a film on the front side thereof.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: March 1, 2011
    Assignee: Disco Corporation
    Inventors: Yosuke Watanabe, Ryugo Oba, Masaru Nakamura
  • Publication number: 20110006406
    Abstract: A method is provided for producing a porogen-residue-free ultra low-k film with porosity higher than 50% and a high elastic modulus above 5 GPa. The method starts with depositing a SiCOH film using Plasma Enhanced Chemical Vapor Deposition (PE-CVD) or Chemical Vapor Deposition (CVD) onto a substrate and then first Performing an atomic hydrogen treatment at elevated wafer temperature in the range of 200° C. up to 350° C. to remove all the porogens and then performing a UV assisted thermal curing step.
    Type: Application
    Filed: July 7, 2010
    Publication date: January 13, 2011
    Applicants: IMEC, Katholieke Universiteit Leuven, K.U. LEUVEN R&D
    Inventors: Adam Michal Urbanowicz, Patrick Verdonck, Denis Shamiryan, Kris Vanstreels, Mikhail Baklanov, Stefan De Gendt
  • Patent number: 7825029
    Abstract: A method for the patterned coating of a substrate with at least one surface is provided. The method is suitable for the rapid and inexpensive production of precise patterns. The method includes the steps of: producing at least one negatively patterned first coating on the at least one surface, depositing at least one second layer, which includes a material with a vitreous structure, on the surface, and at least partially removing the first coating.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: November 2, 2010
    Assignee: Schott AG
    Inventors: Jurgen Leib, Florian Bieck, Dietrich Mund
  • Patent number: 7759763
    Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: July 20, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
  • Patent number: 7736948
    Abstract: Individual devices (100) are locally attached to a carrier substrate (10), so that they can be removed therefrom individually. This is achieved through the use of a patterned release layer, particularly a layer that is removable through decomposition into gaseous or vaporized decomposition products. The mechanical connection between the carrier substrate (10) and the individual devices (100) is provided by a bridging portion (43) of an adhesion layer (40).
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: June 15, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Ronald Dekker, Greja Johanna Adriana Maria Verheijden, Theodorus Martinus Michielsen, Carel Van Der Poel, Cornelis Adrianus Henricus Antonius Mutsaers
  • Patent number: 7670938
    Abstract: The present invention is directed to methods of forming contact openings. In one illustrative embodiment, the method includes forming a feature above a semiconducting substrate, forming a layer stack comprised of a plurality of layers of material above the feature, the layer stack having an original height, reducing the original height of the layer stack to thereby define a reduced height layer stack above the feature, forming an opening in the reduced height layer stack for a conductive member that will be electrically coupled to the feature and forming the conductive member in the opening in the reduced height layer stack.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: March 2, 2010
    Assignee: GlobalFoundries, Inc.
    Inventors: David D. Wu, Mark W. Michael
  • Patent number: 7601607
    Abstract: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: October 13, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Wuping Liu, Raymond Joy, Beichao Zhang, Liang Choo Hsia, Boon Meng Seah, Shyam Pal
  • Patent number: 7575995
    Abstract: There are provided a method of forming a fine metal pattern and a method of forming a metal line using the same. In the method of forming a fine metal pattern, a substrate is prepared where a first interlayer insulating layer is formed. A via plug is formed on the first interlayer insulating layer. A plurality of sidewall buffer patterns are formed on the first interlayer insulating layer having the via plug, wherein the plurality of the sidewall buffer patterns are spaced apart from each other by a predetermined distance. The sidewall layer is deposited on the first interlayer insulating layer and the sidewall buffer patterns. The sidewall layer is etched such that sidewall patterns remains on sidewalls of the sidewall buffer patterns.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: August 18, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Kim Ki Yong
  • Patent number: 7572697
    Abstract: A method of manufacturing flash memory devices wherein, after gate lines are formed, an HDP oxide film having at least the same height as that of a floating gate is formed between the gate lines. Spacers are formed between the remaining spaces using a nitride film. Accordingly, the capacitance between the floating gates can be lowered. After an ion implantation process is performed, spacers can be removed. It is therefore possible to secure contact margin of the device.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: August 11, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Ok Hong
  • Patent number: 7564114
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming an interface layer, removing a portion of the interface layer, annealing the interface layer, and forming a dielectric material over the interface layer.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: July 21, 2009
    Assignee: Qimonda North America Corp.
    Inventor: Shrinivas Govindarajan
  • Patent number: 7560329
    Abstract: The semiconductor device comprises a gate electrode 112 formed over a semiconductor substrate 10, a sidewall spacer 116 formed on the side wall of the gate electrode 112, a sidewall spacer 144 formed on the side wall of the gate electrode 112 with the sidewall spacer 116 formed on, and an oxide film 115 formed between the sidewall spacer 116 and the sidewall spacer 144, and the semiconductor substrate 10. The film thickness of the oxide film 115 between the sidewall spacer 144 and the semiconductor substrate 10 is thinner than the film thickness of the oxide film 115 between the sidewall spacer 116 and the semiconductor substrate 10.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: July 14, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Shinichi Nakagawa
  • Patent number: 7544618
    Abstract: A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to provide a rinsed surface; and polishing the rinsed surface by providing a second polishing composition to provide a second polished surface.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: June 9, 2009
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Fu Chen, Yung-Tai Hung, Chi-Tung Huang, Yun-Chi Yang
  • Patent number: 7537971
    Abstract: A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor includes performing an ion implantation process onto a photodiode region in a first conductivity type semiconductor layer to form a second conductivity type first impurity region, and performing an annealing process in a gas atmosphere including first conductivity type impurity atoms to form a first conductivity type second impurity region underneath a surface of the first conductivity type semiconductor layer in the second conductivity type first impurity region, wherein the first conductivity type second impurity region is doped with the diffused first conductivity impurity atoms.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: May 26, 2009
    Assignee: MagnaChip Semiconductor Ltd.
    Inventor: Han-Seob Cha
  • Publication number: 20090121295
    Abstract: Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.
    Type: Application
    Filed: November 9, 2007
    Publication date: May 14, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian J. Greene, Rajesh Rengarajan
  • Patent number: 7528059
    Abstract: By forming a capping layer after a CMP process for planarizing the surface topography of an ILD layer, any surface irregularities may be efficiently sealed, thereby reducing the risk for forming conductive surface irregularities during the further processing. Consequently, yield loss effects caused by leakage paths or short circuits in the first metallization layer may be significantly reduced.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: May 5, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Sandra Bau, Johannes Groschopf
  • Patent number: 7510972
    Abstract: A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface damaged layer and polishing remnants to be controlled easily. An insulating film on a substrate, which has been revealed by chemical mechanical polishing, is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film which has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: March 31, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Kenya Iwasaki
  • Patent number: 7459720
    Abstract: The present invention provides a single crystal wafer, wherein the main surface has a plane or a plane equivalent to a plane tilting with respect to a [100] axis of single crystal by angles of ? (0°<?<90°) for the [011] direction, ? (0°<?<90°) for the [01-1] direction and ? (0°??<45°) for the [10-1] or [101] direction. Thus, a single crystal wafer that can sufficiently bear device production processes even with a small wafer thickness is provided and thereby loss of single crystal raw material is reduced. Further, by using such a wafer, MIS type semiconductor devices and solar cells are provided at a low cost.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: December 2, 2008
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Tatsuo Ito, Koichi Kanaya
  • Patent number: 7419909
    Abstract: Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with a second pitch in the second region that are alternately arranged with the first patterns, forming a space insulating layer that covers the first and second patterns and comprises gap regions that are alternately arranged with the first patterns so as to correspond with the second patterns, forming third patterns that correspond to the second patterns in the gap regions, respectively, etching the space insulating layer between the first and second patterns and between the first and third patterns, such that the space insulating layer remains between the second patterns and the third patterns, and etching the lower layer using the first, second, and third patterns and the remaining space insulating layer between the second and third patterns as an
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: September 2, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Kim, Jae-Kwan Park, Dong-Hwa Kwak, Su-Jin Ahn, Yoon-Moon Park, Jue-Hwang Sim, Jang-Ho Park, Sang-Yong Park
  • Patent number: 7396737
    Abstract: A method of manufacturing a semiconductor device including forming a pad oxide layer on a semiconductor substrate, forming a spacer oxide layer pattern on sidewalls of the pad oxide layer, and forming a nitride layer on the pad oxide layer. The method further includes forming a groove in the nitride layer by selectively removing the spacer oxide layer pattern, forming a trench in a region where the groove is formed, and filling the trench with a thermal oxide layer so as to form a shallow trench isolation (STI) layer. In the method, the line width of the STI layer depends on the thickness of the spacer oxide layer, and so the STI layer can be formed to a line width W smaller than a design rule.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: July 8, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jong-Woon Choi
  • Patent number: 7393737
    Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: July 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
  • Patent number: 7393789
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: July 1, 2008
    Assignee: MICRON Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar M. Subramanian
  • Patent number: 7361598
    Abstract: Disclosed is a method for fabricating a semiconductor device capable of preventing scratches. The method includes the steps of: forming a substrate divided into a peripheral region and a cell region where a capacitor including a metal plate electrode on which particles with a pointed shape are generated is formed; forming an inter-layer insulation layer with a poor step coverage on the metal plate electrode, the particles with the pointed shape and a surface of the substrate in the peripheral region; etching a portion of the inter-layer insulation layer, thereby exposing predetermined portions of lateral sides of the particles with the pointed shape; selectively removing the exposed portions of the particles with the pointed shape to separate top portions of the particles with the pointed shape from the inter-layer insulation layer; and planarizing the inter-layer insulation layer through a chemical mechanical polishing (CMP) process.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: April 22, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yang-Han Yoon
  • Patent number: 7358587
    Abstract: In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending therethrough to expose a portion of the underlying substrate and comprising an upper corner at a periphery of the opening, the upper corner having a corner angle with a first degree of sharpness; b) reducing the sharpness of the corner angle to a second degree; c) after reducing the sharpness, forming a layer of material within the opening and over the etch-stop layer; and d) planarizing the material with a method selective for the material relative to the etch-stop layer to remove the material from over the etch-stop layer while leaving the material within the opening.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: April 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: John T. Moore, Guy T. Blalock
  • Patent number: 7358196
    Abstract: Described herein are methods of forming a thin silicon dioxide layer having a thickness of less than eight angstroms on a semiconductor substrate to form the bottom layer of a gate dielectric. A silicon dioxide layer having a thickness of less than eight angstroms may be formed by two different methods. In one method, a sulfuric acid solution is applied to a semiconductor substrate to grow a silicon dioxide layer of less than eight angstroms. The growth of the silicon dioxide layer by the sulfuric acid solution is self-limiting. In another method, a hydrogen peroxide containing solution is applied to a semiconductor substrate for a time sufficient to grow a silicon dioxide layer having a thickness of greater than eight angstroms and then applying an etching solution to etch the silicon dioxide layer down to a thickness of less than eight angstroms.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: April 15, 2008
    Assignee: Applied Materials, Inc.
    Inventor: Steven Verhaverbeke
  • Patent number: 7338905
    Abstract: An electric conductive film is formed on the insulating surface of a substrate, the substrate having a trench formed on the insulating surface, and the conductive film being filled in the trench. Chemical mechanical polishing is executed to expose the insulating surface of the substrate and leave a portion of the conductive film in the trench. The surface of the substrate having the exposed conductive film in the trench and the exposed insulating surface is exposed to first liquid. After being exposed to the first liquid, the surface of the substrate is exposed to second liquid. The first liquid is either solution which contains at least one first substance selected from a first group consisting of benzotriazole, derivative of benzotriazole and interfacial active agent, or water. The second solution is solution which contains the first substance at a density higher than a density of the first liquid.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: March 4, 2008
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Shirasu, Toshiyuki Karasawa, Nobuhiro Misawa, Tamotsu Yamamoto, Kenji Nakano
  • Publication number: 20080044964
    Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.
    Type: Application
    Filed: August 3, 2007
    Publication date: February 21, 2008
    Inventors: Arvind Kamath, James Cleeves, Joerg Rockenberger, Patrick Smith, Fabio Zurcher
  • Publication number: 20080009136
    Abstract: A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a polishing method using the slurry composition, a polysilicon layer may be rapidly polished, and also dishing and erosion of the polysilicon layer may be suppressed.
    Type: Application
    Filed: September 17, 2007
    Publication date: January 10, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.,
    Inventors: Hyo-Jin Lee, Kyung-Hyun Kim, Yong-Sun Ko
  • Patent number: 7282434
    Abstract: A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulating film comprising silicon oxide as a major component, forming a third insulating film comprising silicon carbide as a major component, and forming a fourth insulating film comprised of fluorine-containing silicon oxide. The fourth insulating film is removed at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask. A first conductive layer is buried inside the wiring groove and the first conductive layer is removed from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: October 16, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tsuyoshi Tamaru, Kazutoshi Oomori, Noriko Miura, Hideo Aoki, Takayuki Oshima
  • Patent number: 7276426
    Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is placed within a reaction chamber. The substrate comprises a center region and an edge region surrounding the center region. The substrate comprises openings within the center region, and openings within the edge region. While the substrate is within the reaction chamber, a layer of insulative material is formed across the substrate. The layer is thicker over the one of the center region and edge region than over the other of the center region and edge region. The layer is exposed to an etch which removes the insulative material faster from over the one of the center region and edge region than from over the other of the center region and edge region.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Neal R. Rueger
  • Patent number: 7271100
    Abstract: A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a polishing method using the slurry composition, a polysilicon layer may be rapidly polished, and also dishing and erosion of the polysilicon layer may be suppressed.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: September 18, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-Jin Lee, Kyung-Hyun Kim, Yong-Sun Ko
  • Publication number: 20070048449
    Abstract: In the present invention, a holding table incorporating a heater is provided, for example, in a treatment container of a planarization unit. A pressing plate having a lower surface formed flat is disposed above the holding table. The pressing plate is movable in the vertical direction and can lower to the holding table to press a resist film on the substrate from above. The pressing plate intermittently presses the upper surface of the resist film to planarize the upper surface while the heater is heating the substrate on the holding table at a predetermined temperature to dry the resist film. According to the present invention, a coating film applied on the substrate can be sufficiently planarized and dried.
    Type: Application
    Filed: August 16, 2006
    Publication date: March 1, 2007
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hiroshi Shinya, Shouichi Terada, Tsuyoshi Mizuno, Yukihiro Wakamoto
  • Patent number: 7148103
    Abstract: Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electronic circuit (1) with a first conductive layer (6; 6) that is patterned by subjecting an exposed layer portion thereof to Reactive Ion Etching (RIE); manufacturing the second electronic circuit (2) with a second conductive layer (6; 8) that is patterned by subjecting an exposed layer portion thereof to RIE; providing a tile structure (25; 26); providing the tile structure (25; 26) with at least one dummy conductive layer (6; 8) produced in the same processing step as the second conductive layer (6; 8); and exposing the dummy conductive layer (6; 8), at least partially, to obtain an exposed dummy layer portion, and RIE-etching of that exposed portion too when the second (6; 8) conductive layer is subjected to RIE.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: December 12, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Antonius Maria Petrus Johannes Hendriks, Guido Jozef Maria Dormans, Robertus Dominicus Joseph Verhaar