By Chemical Means (epo) Patents (Class 257/E21.251)
  • Patent number: 10435794
    Abstract: There is provided an etching method of a semiconductor substrate that includes a first layer containing germanium (Ge) and a second layer containing at least one specific metal element selected from nickel platinum (NiPt), titanium (Ti), nickel (Ni), and cobalt (Co), the method including: bringing an etching solution which contains a non-halogen acidic compound into contact with the second layer and selectively removing the second layer.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 8, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Naotsugu Muro, Tetsuya Kamimura, Satomi Takahashi, Akiko Koyama, Atsushi Mizutani
  • Patent number: 10439034
    Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, a gate insulating layer, a gate electrode, an interlayer insulating layer, a contact hole, a metal layer, and a source line. The gate electrode is disposed on the gate insulating layer. The interlayer insulating layer covers the gate electrode. The contact hole penetrates the gate insulating layer and the interlayer insulating layer, causes a portion of the surface of the semiconductor substrate to be exposed, and includes an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer. The metal layer covers an upper surface of the interlayer insulating layer, the inner surface of the contact hole, and at least part of the portion of the surface of the semiconductor substrate exposed by the contact hole.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 8, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takashi Hasegawa, Kouichi Saitou, Chiaki Kudou
  • Patent number: 10431498
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of gate structures on the base substrate with each gate structure including a gate electrode and sidewall spacers on each aide surface of the gate electrode, forming source/drain doped regions in the base substrate on opposite sides of each gate structure, forming a sacrificial layer on side surfaces of each sidewall spacer, and performing a pre-amorphous ion implantation process on the source/drain doped regions using the sacrificial layer as a mask.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: October 1, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10242876
    Abstract: Provided is a method including the following steps: forming an insulating film having a thickness of 0.5 ?m or greater on an epitaxial layer provided with a well region, a source region, and a contact region, each being an impurity diffusion region; forming, in the insulating film, an opening that has a dimension of 2 mm×2 mm or greater in a plan view to expose at least part of the impurity diffusion region from the insulating film. The step of forming the opening in the insulating film is performed by the following separate steps: removing the insulating film so as to leave one-half or less of the thickness of the insulating film unremoved, through dry etching by the use of a photoresist; and removing the insulating film until the opening reaches the upper surface of the epitaxial layer, through wet etching by the use of the same photoresist.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: March 26, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Chikamori, Nobuaki Yamanaka, Takamichi Iwakawa
  • Patent number: 9881972
    Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Denzil S. Frost, Tuman Earl Allen, III
  • Patent number: 9824917
    Abstract: The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chih-chao Yang, Daniel Charles Edelstein
  • Patent number: 9741871
    Abstract: A junction field effect transistor (JFET) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate and a gate region formed on the base semiconductor substrate. The gate region forms a junction with the base semiconductor substrate. The JFET further comprises a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region and a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region. A gate stack is deposited on the gate region, a first source/drain stack is deposited on the first source/drain region and a second source/drain stack is deposited on the second source/drain region. At least one of the gate stack, first source/drain stack and second source/drain stack overlaps onto another one of the gate stack, first source/drain stack and second source/drain stack.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi, Yanning Sun
  • Patent number: 9741581
    Abstract: A method for preventing buckling in a substrate using a tensile hard mask is provided. The method may include forming a mask over a substrate, the hard mask including a first area having a pattern for forming a plurality of openings and an adjacent second area free of openings, and the hard mask includes a tensile stress therein. The hard mask may be used to form the plurality of openings in the substrate. Partially eroding the hard mask leaves the substrate with the plurality of openings therein and a substantially planar surface, having diminished buckling.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: August 22, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunit S. Mahajan, Parul Dhagat, Anne C. Friedman, Timothy A. Brunner, Shahrukh A. Khan
  • Patent number: 9728444
    Abstract: Lift-off methods for fabricating metal line patterns on a substrate are provided. For example, a method to fabricate a device includes forming a sacrificial layer on a substrate and forming a photoresist mask over the sacrificial layer, isotropically etching a portion of the sacrificial layer exposed through an opening of the photoresist mask to form an undercut region in the sacrificial layer below the photoresist mask, wherein the undercut region defines an overhang structure, and anisotropically etching a portion of the sacrificial layer exposed through the opening of the photoresist mask to form an opening through the sacrificial layer down to the substrate. Metallic material is deposited to cover the photoresist mask and to at least partially fill the opening formed in the sacrificial layer without coating the overhang structure with metallic material. The sacrificial layer is dissolved to lift-off the metallic material covering the photoresist mask.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Sebastian U. Engelmann, Steve Holmes, Jyotica V. Patel
  • Patent number: 9728607
    Abstract: A silicon carbide substrate having a gate insulating film provided in contact with a first main surface, having a gate electrode provided in contact with the gate insulating film, and having a source region exposed from first main surface is prepared. A first recess having a first inner wall surface is formed in an interlayer insulating film by performing a first isotropic etching with respect to the interlayer insulating film with use of a mask layer. A second recess having a second inner wall surface is formed by performing a first anisotropic etching with respect to the interlayer insulating film and the gate insulating film with use of the mask layer and thereby exposing the source region from gate insulating film. An interconnection is formed which is arranged in contact with the first inner wall surface and the second inner wall surface and electrically connected to a source electrode.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: August 8, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Masaki Kijima
  • Patent number: 9702042
    Abstract: The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chih-chao Yang, Daniel Charles Edelstein
  • Patent number: 9601452
    Abstract: A thermally-conductive and mechanically-robust bonding method for attaching a metal nanowire (MNW) array to an adjacent surface includes the steps of: removing a template membrane from the MNW; infiltrating the MNW with a bonding material; placing the bonding material on the adjacent surface; bringing an adjacent surface into contact with a top surface of the MNW while the bonding material is bondable; and allowing the bonding material to cool and form a solid bond between the MNW and the adjacent surface. A thermally-conductive and mechanically-robust bonding method for attaching a metal nanowire (MNW) array to an adjacent surface includes the steps of: choosing a bonding material based on a desired bonding process; and without removing the MNW from a template membrane that fills an interstitial volume of the MNW, depositing the bonding material onto a tip of the MNW.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 21, 2017
    Assignees: Northrup Grumman Systems Corporation, The Board of Trustees of the Leland Stanford Junior University
    Inventors: John A. Starkovich, Edward M. Silverman, Jesse B. Tice, Hsiao-Hu Peng, Michael T. Barako, Kenneth E. Goodson
  • Patent number: 9565770
    Abstract: In an embodiment, there is provided a method of creating a package, the method comprising: providing an initial substrate, wherein the initial substrate comprises a carrier foil, a functional copper foil, and an interface release layer between the carrier foil and the functional copper foil; building up copper portions on the functional copper foil; attaching a chip to a first copper portion; coupling the chip to a second copper portion; encapsulating at least the chip and the copper portions with a mold; and removing the carrier foil and interface release layer.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: February 7, 2017
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Albert Wu, Hyun J Shin
  • Patent number: 9536780
    Abstract: The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chih-chao Yang, Daniel Charles Edelstein
  • Patent number: 9425270
    Abstract: A contact structure is provided, including a substrate, an active layer, an inter-layer dielectric (ILD) layer, a contact opening, and a conductive layer. The active layer is disposed over the substrate, and the insulating layer is disposed over the active layer; an inter-layer dielectric (ILD) layer over the insulating layer. The contact opening penetrates a portion of the ILD layer and the insulating layer to expose a portion of the active layer, wherein the contact opening includes a first recess portion, and the first recess portion is defined by a bottom surface of the ILD layer, a sidewall of the insulating layer and a top surface of the active layer. The conductive layer is in the contact opening and is electrically connected to the active layer.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: August 23, 2016
    Assignee: INNOLUX CORPORATION
    Inventors: Yu-Tsung Liu, Chung-Wen Yen
  • Patent number: 9368394
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a semiconductor substrate; forming a conductive region at least partially in the semiconductor substrate; forming a dielectric layer over the substrate; forming a hard mask over the dielectric layer, the hard mask having an opening over the conductive region; dry etching the dielectric layer by a first etching gas to form a recessed feature, wherein a surface of the conductive region is therefore exposed at a bottom of the recessed feature, and a byproduct film is formed at an inner surface of the recessed feature; and dry etching the dielectric layer by a second etching gas, wherein the second etching gas chemically reacts with the byproduct film and the conductive region, and a sacrificial layer is therefore built up around the bottom of the recessed feature.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 14, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Li Hung, Te-Ming Kung, Chih-Hao Chen, Kei-Wei Chen, Ying-Lang Wang, Hung Jui Chang, Horng-Huei Tseng
  • Patent number: 8871601
    Abstract: Embodiments of the present invention include diffusion barriers, methods for forming the barriers, and semiconductor devices utilizing the barriers. The diffusion barrier comprises a self-assembled monolayer (SAM) on a semiconductor substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the semiconductor substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the barrier comprises an assembly of one or more monomeric subunits of the following structure: Si—(CnHy)-(LM)m where n is from 1 to 20, y is from 2n?2 to 2n, m is 1 to 3, L is a Group VI element, and M is a metal, such as copper. In some embodiments, (CnHy) can be branched, crosslinked, or cyclic.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: October 28, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Xuena Zhang, Mankoo Lee, Dipankar Pramanik
  • Patent number: 8815736
    Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: August 26, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Peter Javorka, Stefan Flachowsky, Clemens Fitz
  • Patent number: 8759983
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Akihiro Kajita, Kazuyuki Higashi
  • Patent number: 8704224
    Abstract: A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: An-Chun Tu, Chen-Ming Huang, Chih-Jen Wu, Chin-Hsiang Lin
  • Patent number: 8613287
    Abstract: An apparatus for preventing stiction of a three-dimensional MEMS (microelectromechanical system) microstructure, the apparatus including: a substrate; and a plurality of micro projections formed on a top surface of the substrate with a predetermined height in such a way that a cleaning solution flowing out from the microstructure disposed thereabove is discharged.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: December 24, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chang Han Je, Myung Lae Lee, Sung Hae Jung, Gunn Hwang, Chang Auck Choi
  • Patent number: 8609459
    Abstract: A nanostructure quick-switch memristor includes an upper electrode, a lower electrode and three layers of nanomembrane provided between the upper electrode and the lower electrode. The three layers of nanomembrane consist of an N-type semiconductor layer, a neutral semiconductor layer on the N-type semiconductor layer, and a P-type semiconductor layer on the neutral semiconductor layer. The nanostructure quick-switch memristor of the present invention has the quick switching speed, simple manufacturing method, and low manufacturing cost.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: December 17, 2013
    Assignee: Heilongjiang University
    Inventors: Dianzhong Wen, Xiaohui Bai
  • Patent number: 8501501
    Abstract: A sample with at least a first structure and a second structure is measured and a first model and a second model of the sample are generated. The first model models the first structure as an independent variable and models the second structure. The second model of the sample models the second structure as an independent variable. The measurement, the first model and the second model together to determine at least one desired parameter of the sample. For example, the first structure may be on a first layer and the second structure may be on a second layer that is under the first layer, and the processing of the sample may at least partially remove the first layer, wherein the second model models the first layer as having a thickness of zero.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: August 6, 2013
    Assignee: Nanometrics Incorporated
    Inventors: Ye Feng, Zhuan Liu
  • Publication number: 20130181265
    Abstract: Disclosed herein are various methods of forming a gate cap layer above a replacement gate structure, and a device having such a cap layer. In one example, a device disclosed herein includes a replacement gate structure having a dished upper surface, sidewall spacers positioned proximate the replacement gate structure and a gate cap layer positioned above the replacement gate structure, wherein the gate cap layer has a bottom surface that corresponds to the dished upper surface of the replacement gate structure.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Gunter Grasshoff, Catherine Labelle
  • Patent number: 8466068
    Abstract: The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a damascene process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a damascene process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to trenches for forming memory lines and at least one depth corresponds to holes for forming vias. Numerous other aspects are disclosed.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: June 18, 2013
    Assignee: SanDisk 3D LLC
    Inventor: Roy E. Scheuerlein
  • Publication number: 20130034962
    Abstract: The invention discloses a method for reducing a minimum line width in a spacer-defined double patterning process of the present invention. In the method, the silicon nitride spacers can be converted into trenches in the interlayer dielectric layer by using a silicon dioxide film as a mask and by means of a chemically mechanical polishing process and an etching process, so that the minimum line width of the trenches can be determined by the width of the silicon nitride spacers, and thus a smaller line width can be achieved and the process can be simple and easy to control.
    Type: Application
    Filed: December 29, 2011
    Publication date: February 7, 2013
    Applicant: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventor: Liujiang Yu
  • Publication number: 20130017685
    Abstract: To provide a method of manufacturing a semiconductor device, including: forming a thin film different from a silicon oxide film on a substrate by supplying a processing gas into a processing vessel in which the substrate is housed; removing a deposit including the thin film adhered to an inside of the processing vessel by supplying a fluorine-containing gas into the processing vessel after executing forming the thin film prescribed number of times; and forming a silicon oxide film having a prescribed film thickness on the inside of the processing vessel by alternately supplying a silicon-containing gas, and an oxygen-containing gas and a hydrogen-containing gas into the heated processing vessel in which a pressure is set to be less than an atmospheric pressure after removing the deposit.
    Type: Application
    Filed: February 18, 2011
    Publication date: January 17, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naonori Akae, Kotaro Murakami, Yoshiro Hirose, Kenji Kameda
  • Patent number: 8349078
    Abstract: The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm?2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 8, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Yu Saitoh, Kazuhide Sumiyoshi, Akihiro Hachigo, Makoto Kiyama, Seiji Nakahata
  • Publication number: 20120261767
    Abstract: Systems and methods for reducing gate leakage current and positive bias temperature instability drift are provided. In one embodiment, a system comprises a p-channel field effect transistor (PFET) device on a semiconductor substrate, and a high voltage transistor on the substrate. The system also comprises a plurality of silicides formed in the substrate, the plurality of silicides formed proximate to the PFET device and the high voltage transistor. Further, the system comprises a buffer oxide layer formed over the substrate, the PFET device, and the high voltage transistor and a moisture barrier formed over the buffer layer, the moisture barrier comprised of silicon oxynitride. Additionally, the system comprises an interlayer dielectric device formed over the moisture barrier and a plurality of electrical contacts extending through the interlayer dielectric, the moisture barrier, and the buffer oxide layer, wherein the plurality of electrical contacts are electrically connected to the plurality of silicides.
    Type: Application
    Filed: March 19, 2012
    Publication date: October 18, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventor: Michael D. Church
  • Publication number: 20120184107
    Abstract: In a semiconductor device manufacturing method, the formation of a sacrificial oxide film and removal thereof by wet etching and/or the formation of a silicon dioxide film and removal thereof by wet etching are performed. In the process for manufacturing a semiconductor device, the formation of the sacrificial oxide film and/or the silicon dioxide film is performed within a processing chamber of a plasma processing apparatus using a plasma in which O(1D2) radicals produced using a processing gas that contains oxygen are dominant.
    Type: Application
    Filed: September 29, 2010
    Publication date: July 19, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yoshihiro Sato, Toshihiko Shiozawa, Tatsuo Nishita, Yoshihiro Hirota
  • Patent number: 8148175
    Abstract: A manufacturing apparatus for a semiconductor device, treating a SiN film formed on a wafer with phosphoric acid solution, including a processing bath to store phosphoric acid solution provided for treatment of the wafer, a control unit for calculating integrated SiN etching amount of the phosphoric acid solution, determining necessity of quality adjustment of the phosphoric acid solution, based on correlation between the integrated SiN etching amount calculated and etching selectivity to oxide film, and calculating a quality adjustment amount of the phosphoric acid solution as needed, and also including a mechanism to adjust the quality of the phosphoric acid solution based on the quality adjustment amount calculated.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisashi Okuchi
  • Publication number: 20110294298
    Abstract: A method for fabricating a textured single crystal including depositing pads made of metal on a surface of a single crystal. A protective layer is deposited on the pads and on the single crystal between the pads; and etching the surface with a first compound that etches the metal more rapidly than the protective layer is carried out. Processing continues with etching the surface with a second compound that etches the single crystal more rapidly than the protective layer; and etching the surface with a third compound that etches the protective layer more rapidly than the single crystal. The textured substrate may be used for the epitaxial growth of GaN, AlN or III-N compounds (i.e. a nitride of a metal the positive ion of which carries a +3 positive charge) in the context of the fabrication of LEDs, electronic components or solar cells.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 1, 2011
    Applicant: Saint-Gobain Cristaux et Detecteurs
    Inventors: Fabien LIENHART, Guillaume Lecamp, François-Julien Vermersch
  • Publication number: 20110189859
    Abstract: An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 4, 2011
    Inventors: Ping-Chia Shih, Yu-Cheng Wang, Chun-Sung Huang, Yuan-Cheng Yang, Chung-Che Huang, Chin-Fu Lin
  • Patent number: 7960200
    Abstract: In accordance with the present invention, accurate and easily controlled sloped walls may be formed using AlN and preferably a heated TMAH for such purpose as the fabrication of MEMS devices, wafer level packaging and fabrication of fluidic devices. Various embodiments are disclosed.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: June 14, 2011
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Guillaume Bouche, Ralph N. Wall
  • Patent number: 7960258
    Abstract: The present invention discloses a method for fabricating a nanoscale thermoelectric device, which comprises steps: providing at least one template having a group of nanoscale pores; forming a substrate on the bottom of the template; injecting a molten semiconductor material into the nanoscale pores to form a group of semiconductor nanoscale wires; removing the substrate to obtain a semiconductor nanoscale wire array; and using metallic conductors to cascade at least two semiconductor nanoscale wire arrays to form a thermoelectric device having a higher thermoelectric conversion efficiency.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: June 14, 2011
    Assignee: National Chiao Tung University
    Inventors: Chuen-Guang Chao, Jung-Hsuan Chen, Ta-Wei Yang
  • Patent number: 7939421
    Abstract: A method for fabricating an integrated circuit structure includes the steps of forming a second dielectric layer on a substrate including a first conductive layer and a first dielectric layer, forming the second dielectric layer on the first conductive layer and the first dielectric layer, forming a hole exposing the first conductive layer in the second dielectric layer, forming a barrier layer inside the hole, and forming a second conductive layer on the barrier layer. In one embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal layer.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: May 10, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Chiang Hung Lin
  • Patent number: 7879724
    Abstract: A method of manufacturing a semiconductor device has polishing a film, and cleaning a polished surface by carrying out a first exposing the polished surface to an acidic first cleaning fluid having an effect of etching at least a partial region of the polished surface, and a second exposing the polished surface to an alkaline second cleaning fluid after the first exposing.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: February 1, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoki Idani
  • Patent number: 7838321
    Abstract: This describes a starting structure and method for forming a micro-mechanical device. These devices have several uses in both government and commercial applications. The starting structure can be sold or supplied to others who will then make a final product, or it can be used directly to make a final product. An appropriate use of this starting structure is to make deformable devices useful in an inkjet printing device.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: November 23, 2010
    Assignee: Xerox Corporation
    Inventors: Peter J. Nystrom, Nancy Jia, Kee Ryu
  • Patent number: 7727871
    Abstract: This disclosure concerns a manufacturing method of a semiconductor device comprising an etching process using an etching solution having ozone dissolved by 10 ppm or more into a liquid containing H2SO4 by 86 wt % to 97.9 wt %, HF by 0.1 wt % to 10 wt %, and H2O by 2 wt % to 4 wt %.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: June 1, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tomita, Hiroyasu Iimori
  • Patent number: 7691739
    Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: April 6, 2010
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
  • Patent number: 7659206
    Abstract: A method of treating a substrate comprises depositing silicon oxycarbide on the substrate and removing the silicon oxycarbide from the substrate. The silicon oxycarbide on the substrate is decarbonized by exposure to an energized oxygen-containing gas that heats the substrate and converts the layer of silicon oxycarbide into a layer of silicon oxide. The silicon oxide is removed by exposure to a plasma of fluorine-containing process gas. Alternatively, the remaining silicon oxide can be removed by a fluorine-containing acidic bath. In yet another version, a plasma of a fluorine-containing gas and an oxygen-containing gas is energized to remove the silicon oxycarbide from the substrate.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: February 9, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Krishna Vepa, Yashraj Bhatnagar, Ronald Rayandayan, Venkata Balagani
  • Patent number: 7655544
    Abstract: Methods and apparatus for producing self-assembling quantum nanostructures by nanoheating a substrate with one or more laser interference patterns.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: February 2, 2010
    Assignee: Utah State University
    Inventor: Haeyon Yang
  • Publication number: 20090269918
    Abstract: Methods for fabricating a semiconductor FIN structure with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures for rounding the corners and edges between the top surfaces and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures are annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures.
    Type: Application
    Filed: April 28, 2008
    Publication date: October 29, 2009
    Inventors: Yi Ma, Robert Bertram Ogle
  • Patent number: 7598168
    Abstract: A method of forming a dual damascene semiconductor interconnection and an etchant composition specially adapted for stripping a sacrificial layer in a dual damascene fabrication process without profile damage to a dual damascene pattern are provided. The method includes sequentially forming a first etch stop layer, a first intermetal dielectric, a second intermetal dielectric, and a capping layer on a surface of a semiconductor substrate on which a lower metal wiring is formed; etching the first intermetal dielectric, the second intermetal dielectric, and the capping layer to form a via; forming a sacrificial layer within the via; etching the sacrificial layer, the second intermetal dielectric, and the capping layer to form a trench; removing the sacrificial layer remaining around the via using an etchant composition including NH4F, HF, H2O and a surfactant; and forming an upper metal wiring within the thus formed dual damascene pattern including the via and the trench.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: October 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-cheol Han, Kyoung-woo Lee, Mi-young Kim
  • Publication number: 20090166682
    Abstract: The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a damascene process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a damascene process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to trenches for forming memory lines and at least one depth corresponds to holes for forming vias. Numerous other aspects are disclosed.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventor: ROY E. SCHEUERLEIN
  • Publication number: 20090111273
    Abstract: The invention defines a pillar pattern or an island pattern by forming a contact hole and filling the contact hole with a hard mask material by using a spacer formation process, so that the mask pattern formation process margin for island (e.g., pillar) pattern formation is increased. Accordingly, the yield and reliability of the formation process of a semiconductor device are improved.
    Type: Application
    Filed: May 7, 2008
    Publication date: April 30, 2009
    Inventor: Cheol Kyun Kim
  • Publication number: 20090053895
    Abstract: There is provided a method for forming a porous dielectric film stably by: forming a surface densification layer by processing a surface of an SiOCH film formed by a plasma CVD process while using an organic silicon compound source; and releasing CHx groups or OH group from the SiOCH film underneath the surface densification layer by hydrogen plasma processing through the surface densification layer with a controlled rate.
    Type: Application
    Filed: July 11, 2008
    Publication date: February 26, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yasuhiro OSHIMA, Shinji Ide, Yusaku Kashiwagi, Kotaro Miyatani
  • Publication number: 20090017596
    Abstract: Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing composition. The conversion may utilize one or more oxygen-containing species (such as ozone) and a temperature of less than or equal to 300° C. In some embodiments, the spin-on material is formed within an opening in a semiconductor material to form a trenched isolation region. Other dielectric materials may be formed within the opening in addition to the silicon dioxide-containing composition formed from the spin-on material. Such other dielectric materials may include silicon dioxide formed by chemical vapor deposition and/or silicon dioxide formed by high-density plasma chemical vapor deposition.
    Type: Application
    Filed: July 9, 2007
    Publication date: January 15, 2009
    Inventors: Robert J. Hanson, Janos Fucsko
  • Publication number: 20080311755
    Abstract: A method of treating a dielectric layer on a substrate is described. The method comprises forming the dielectric layer on the substrate, wherein the dielectric layer comprises a dielectric constant value less than the dielectric constant of SiO2. A feature pattern is formed in the dielectric layer using an etching process. Following the etching process, the feature pattern is treated using a nitrogen-containing plasma in order to form nitride surface layers by introducing nitrogen to the exposed surfaces of the dielectric layer in the feature pattern. Thereafter, the feature pattern is selectively etched to partially or fully remove the nitride surface layers.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 18, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kelvin Kyaw ZIN, Shin OKAMOTO
  • Patent number: 7456086
    Abstract: A process for producing an insulation structure with openings of a low aspect ratio is disclosed. In one embodiment, a dopant is introduced into the insulation structure with a concentration which on average increases or decreases in the vertical direction from a pre-processed semiconductor surface, the openings are formed in a dry-etching step and the aspect ratio of the openings is reduced by increasing the basic surface area of the openings using a subsequent wet-chemical etching step.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: November 25, 2008
    Assignee: Infineon Technologies AG
    Inventor: Stefan Tegen