By Dry-etching (epo) Patents (Class 257/E21.252)
  • Patent number: 10964653
    Abstract: A method for making a semiconductor device is disclosed. A substrate comprising semiconductor device elements is provided. A top conductive pad and an anti-reflective coating are patterned over the substrate. The anti-reflective coating is disposed on the top conductive pad. At least one passivation film is formed over the substrate and the anti-reflective coating. The at least one passivation film and the anti-reflective coating are etched to form a trench therein so as to expose a portion of the top conductive pad.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ya-Ping Su, Han-Wen Fung, Chia-Chi Chung, Chih-Hsien Hsu, Chun Yan Chen, Chien-Sheng Wu, Tien-Chih Huang, Wei-Da Chen, Chien-Hua Tseng
  • Patent number: 10950436
    Abstract: A method of fabricating an array substrate, an array substrate, a display panel, and a display device are provided. In an embodiment, a gate insulating layer above a channel region is doped with fluorine atoms. Since a fluorine-containing inorganic layer can absorb hydrogen atoms, it can block hydrogen atoms from diffusing downward into a metal oxide semiconductor, thereby avoiding affecting electrical properties of thin film transistors. Simultaneously, only a metal is required to use as a metal gate layer, which simplifies process and reduces production costs.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: March 16, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Ming Xiang
  • Patent number: 10937891
    Abstract: A spacer structure and a fabrication method thereof are provided. First and second conductive structures are formed over a substrate. A first patterned dielectric layer is formed to cover the first conductive structure and exposing the second conductive structure. A second dielectric layer is formed to cover the first patterned dielectric layer and an upper surface and sidewalls of the second conductive structure. The second dielectric layer disposed over an upper surface of the first conductive structure and the upper surface of the second conductive structure is removed. The first patterned dielectric layer and the second dielectric layer disposed on sidewalls of the first conductive structure form a first spacer structure, and the second dielectric layer disposed on the sidewalls of the second conductive structure forms a second spacer structure. A width of the first spacer structure is larger than a width of the second spacer structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Fu-Jier Fan, Kong-Beng Thei, Szu-Hsien Liu
  • Patent number: 10875216
    Abstract: An imprint apparatus that forms a pattern on a substrate by using a mold, the apparatus comprises a supply unit configured to supply an imprint material to the substrate; a contact unit configured to contact the imprint material that has been supplied to the substrate with a mold; a substrate stage configured to move the substrate; a gas supply unit that is provided between the supply unit and the contact unit, and supply gas toward the substrate; and a flow volume adjustment unit configured to adjust a flow volume of the gas that is supplied from the gas supply unit, while the substrate stage moves the substrate from a supply position at which the imprint material is supplied by the supply unit to a contact position at which the imprint material is contacted with the mold by the contact unit.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: December 29, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takahiro Toyoshima
  • Patent number: 10867842
    Abstract: A method includes forming a first hard mask layer and a second hard mask layer over the first hard mask layer, and forming a tri-layer including a bottom layer, a middle layer, and a patterned upper layer. The method further includes etching the middle layer to extend an opening in the patterned upper layer into the middle layer, wherein the opening has a first portion in the middle layer, and the first portion has a first top width and a first bottom width smaller than the first top width; etching the bottom layer to extend the opening into the bottom layer; and etching the second hard mask layer to extend the opening into the second hard mask layer. The opening has a second portion in the second hard mask layer, and the second portion has a second top width and a second bottom width smaller than the second top width.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng Wang, Yu-Lien Huang
  • Patent number: 10868002
    Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10859644
    Abstract: A method includes depositing a hardmask layer over a magnetoresistive (MR) structural layer formed on a substrate, the hardmask layer being formed from tungsten or a tungsten-based composition. A photoresist layer is deposited over the hardmask layer and is patterned to expose a first portion of the hardmask layer. A first etch process is performed to remove the first portion of the hardmask layer and expose a second portion of the MR structural layer and a dry etch process is performed to remove the second portion of the MR structural layer and produce an MR sensor structure. Following the dry etch process, a composite structure remains that includes the MR sensor structure and a hardmask section of the hardmask layer, the hardmask section overlying the MR sensor structure. A spacer formed from a protective, dielectric material layer may additionally be formed surrounding the composite structure.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 8, 2020
    Assignee: NXP B.V.
    Inventor: Mark Isler
  • Patent number: 10861704
    Abstract: The surface layer of a semiconductor wafer lying on a rotatable plate within an etching chamber is etched by a process whereby homogeneous etching of the surface is obtained by introducing an etching gas into the etching chamber in such a way that the flow of the etching gas is not directed directly to the wafer but is allowed first to distribute within the etching chamber before coming into contact with the surface of the semiconductor wafer to be etched.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: December 8, 2020
    Assignee: SILTRONIC AG
    Inventor: Franz Hoelzlwimmer
  • Patent number: 10854453
    Abstract: A substrate processing technique is described herein for etching layers, such as dielectric layers, and more particularly low k dielectric layers in a manner that minimizes etch lag effects. Multiple etch processes are utilized. A first etch process may exhibit etch lag. A second etch process is a multi-step process that may include a deposition sub-step, a purge sub-step and an etch sub-step. The second etch process may exhibit inverse etch lag. The second etch process may be a cyclic process which performs the deposition, purge and etch sub-steps a plurality of times. The second etch process may be an atomic layer etch based process, and more particularly a quasi-atomic layer etch. The combination of the first etch process and the second etch process may provide the desired net effect for the overall etch lag when etching the dielectric layer.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 1, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Angelique D. Raley, Christopher Cole, Andrew W. Metz
  • Patent number: 10840204
    Abstract: Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 17, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Atsuko Kawasaki
  • Patent number: 10804138
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a first dielectric layer having a metal layer therein; forming a second dielectric layer on the first dielectric layer and the metal layer; forming a metal oxide layer on the second dielectric layer; performing a first etching process by using a chlorine-based etchant to remove part of the metal oxide layer to forma via opening and expose the second dielectric layer; forming a block layer on sidewalls of the metal oxide layer and a top surface of the second dielectric layer; and performing a second etching process by using a fluorine-based etchant to remove part of the block layer and part of the second dielectric layer for exposing a top surface of the metal layer.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: October 13, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 10784090
    Abstract: A plasma processing device includes a chamber; a substrate stage that supports a substrate inside the chamber; a plasma generator that generates plasma by which the substrate is processed in a space above the substrate inside the chamber; and an electromagnet. The electromagnet is provided in each of a plurality of regions, which are provided on a top of the chamber in an upper part thereof, so as to be independently movable. The plasma processing device further includes a controller configured to move the electromagnet to produce a uniform plasma density onto the substrate.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 22, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takashi Ohashi
  • Patent number: 10777387
    Abstract: The present invention disclosed herein relates to a substrate treating apparatus, and more particularly, to an apparatus for treating a substrate using plasma. Embodiments of the present invention provide substrate treating apparatuses including a chamber having a treating space defined therein, a support member disposed in the chamber to support a substrate, a gas supply unit supplying a gas into the chamber, a plasma source generating plasma from the gas supplied into the chamber, a baffle disposed to surround the support member in the chamber and having through holes to exhaust a gas in the treating space, and a shielding unit preventing an electromagnetic field from an inside of the chamber to an outside of the chamber.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 15, 2020
    Assignee: SEMES CO., LTD.
    Inventors: Hyung Joon Kim, Seung Pyo Lee
  • Patent number: 10748749
    Abstract: A plasma monitoring apparatus includes a reflective structure disposed on a processing chamber providing a space in which plasma for processing a substrate is formed, the reflective structure configured to receive fragments of light incident in a plurality of incident directions from the plasma, and output the fragments of light in a plurality of exit directions by reflecting the fragments of light within the reflective structure; at least one light sensor configured to receive the fragments of light passing through the reflective structure in the plurality of exit directions; and at least one optical spectrometer connected to the at least one light sensor.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong Il Mun, Kyeong Hun Kim, See Yub Yang, Hyung Joo Lee, Jong Woo Sun
  • Patent number: 10740667
    Abstract: Apparatus, systems, and methods for determining a temperature excursion are provided. In one example, a system can comprise a temperature switch component that experiences a temperature excursion associated with a metal alloy of the temperature switch component and one or more electrodes, wherein the temperature excursion is based on a temperature of the metal alloy exceeding a defined threshold value. Additionally, the system can comprise a radio frequency identification tag component that receives a signal, from an external reader device, utilized to determine that the temperature excursion has occurred based on a parameter change, associated with the temperature excursion, from a first parameter to a second parameter different than the first parameter.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Li-Wen Hung, Jae-Woong Nah
  • Patent number: 10692850
    Abstract: A semiconductor device includes a semiconductor substrate, an element region including an active element formed at the semiconductor substrate, a channel stopper formed in an outer peripheral region of the semiconductor substrate, and an insulating film that covers a surface of the semiconductor substrate and that has a first contact hole by which the channel stopper is exposed. The semiconductor device further includes a first field plate, a second field plate, and an equipotential ring electrode. The first field plate is formed on the insulating film, and faces the semiconductor substrate between the channel stopper and the element region through the insulating film. The second field plate is embedded in the insulating film, and faces the semiconductor substrate between the first field plate and the channel stopper through the insulating film. The equipotential ring electrode is formed along an outer peripheral region of the semiconductor substrate.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: June 23, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Hiroyuki Kaneda
  • Patent number: 10685871
    Abstract: The present invention provides a method for fabricating a semiconductor structure. A multilayer structure on is formed a substrate, the multilayer structure includes at least a first dielectric layer, a second dielectric layer and an amorphous silicon layer, next, a first etching step is performed, to forma first recess in the amorphous silicon layer and in the second dielectric layer, parts of the first dielectric layer is exposed by the first recess, afterwards, a hard mask layer is formed in the first recess, a second etching step is then performed to remove the hard mask layer and to expose a surface of the first dielectric layer, and a third etching step is performed with the remaining hard mask layer, to remove a portion of the first dielectric layer, so as to form a second recess in the first dielectric layer.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: June 16, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10651230
    Abstract: A method of manufacturing a semiconductor device is provided. The method comprises forming a first insulator above the substrate, forming a second insulator on the first insulator, performing a first etching process of etching the second insulator by fluorine and hydrogen contained gas to expose the first insulator while leaving a portion of the second insulator which covers a side face of the gate electrode and performing a second etching process of etching a portion of the first insulator exposed by the first etching process. The first etching process includes a first process and a second process performed after the first process. A reaction product is less deposited in the first process than in the second process and etching selectivity of the second insulator with respect to the first insulator is higher in the second process than in the first process.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: May 12, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Keita Torii, Takashi Usui, Takuji Mukai
  • Patent number: 10636738
    Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner, Junli Wang
  • Patent number: 10593677
    Abstract: The present invention discloses a semiconductor structure with capacitor landing pad and a method for fabricating a capacitor landing pad. The semiconductor structure with capacitor landing pad includes a substrate having a plurality of contact structures, a first dielectric layer disposed on the substrate and the contact structures, and a plurality of capacitor landing pads, each of the capacitor landing pads being located in the first dielectric layer and electrically connected to the contact structure, wherein the capacitor landing pads presents a shape of a wide top and a narrow bottom and a top surface of the capacitor landing pads have a concave shape.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: March 17, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Ching Chang
  • Patent number: 10586715
    Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Yonggang Yong Li, Aritra Dhar, Dilan Seneviratne, Jon M. Williams
  • Patent number: 10577571
    Abstract: The invention discloses cleaning compositions which employ a synergistic combination of a ester solvent, preferably a fatty acid methyl ester in combination with one or more linear alkyl amines. The alkyl amines act as to remove and suspend organic oils which have been burnt or adhered to a surface with heat and may even be used alone as a soil removal agent. The cleaning compositions have particular use in cleaning of distillation towers associated with biofuel, and vegetable oil refining, but also find use in cleaning ovens, food cooking surfaces and even dry cleaning.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: March 3, 2020
    Assignee: Ecolab USA Inc.
    Inventors: Chris Nagel, Eric Victor Schmidt, Mark Levitt, Peter J. Fernholz
  • Patent number: 10510952
    Abstract: A storage device includes a first electrode, a stacked feature, a spacer and a barrier structure. The stacked feature is position over the first electrode, and includes a storage element and a second electrode over the storage element. The spacer is positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, in which the notch of the spacer has a surface which is continuous with a top surface of the stacked feature. The barrier structure is embedded in a lateral of the spacer. The barrier structure has a top extending upwards past a bottom of the notch.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 10410873
    Abstract: A method of etching a substrate is described. The method includes disposing a substrate having a surface exposing a first material and a second material in a processing space of a plasma processing system, and performing a modulated plasma etching process to selectively remove the first material at a rate greater than removing the second material. The modulated plasma etching process comprises a power modulation cycle having sequential power application steps that includes: applying a radio frequency (RF) signal to the plasma processing system at a first power level, applying the RF signal to the plasma processing system at a second power level, and applying the RF signal to the plasma processing system at a third power level. Thereafter, the power modulation cycle is repeated at least one more cycle, wherein each modulation cycle includes a modulation time period.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: September 10, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroto Ohtake, Takuya Mori
  • Patent number: 10374062
    Abstract: The present invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate includes a substrate and an insulation layer provided on the substrate, the insulation layer including a via therein formed by etching. The insulation layer further includes a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 6, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventor: Yanfei Sun
  • Patent number: 10297551
    Abstract: A method of manufacturing a redistribution circuit structure and a method of manufacturing an INFO package at least include the following steps. An inter-dielectric layer is formed over a substrate. A seed layer is formed over the inter-dielectric layer. A plurality of conductive patterns are formed over the seed layer. The seed layer and the conductive patterns include a same material. While maintain a substantially uniform pitch width in the conductive pattern, the seed layer exposed by the conductive patterns is selectively removed through a dry etch process to form a plurality of seed layer patterns. The conductive patterns and the seed layer patterns form a plurality of redistribution conductive patterns.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Yun-Chen Hsieh
  • Patent number: 10283370
    Abstract: Exemplary methods for selectively removing silicon nitride may include flowing a fluorine-containing precursor, and oxygen-containing precursor and a silicon-containing precursor into a local plasma to form plasma effluents. The plasma effluents may remove silicon nitride at significantly higher etch rates compared to exposed silicon oxide on the substrate. The methods may also remove silicon nitride more rapidly that silicon carbide and silicon oxycarbide which broadens the utility of the present technology to semiconductor applications.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: May 7, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Onintza Ros Bengoechea, Nancy Fung
  • Patent number: 10274374
    Abstract: An infrared sensor includes an infrared sensor pixel in which a contact hole is formed to electrically connect a metal wiring layer and a support leg metal wiring layer that is located inside a support leg. The metal wiring layer is electrically connected to a signal reading circuit. The contact hole is formed by etching an insulating layer that is formed by deposition so as to cover the metal wiring layer, and has a bottom portion and a side wall portion that are each shaped into a forward tapered shape.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 30, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takaki Sugino, Kenji Shintani, Koji Misaki
  • Patent number: 10249498
    Abstract: A method of controlling doping of a substrate, the method comprising: providing the substrate in a process chamber of a doping system; performing a doping process to impart a target dose on a surface of the substrate using a abruptness depth control technique; and controlling selected operating variables of plasma doping in order to meet doping objectives.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: April 2, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Peter L. G. Ventzek, Hirokazu Ueda
  • Patent number: 10186455
    Abstract: A method of manufacturing a semiconductor interconnect structure may include forming a low-k dielectric layer over a substrate and forming an opening in the low-k dielectric layer, where the opening exposes a portion of the substrate. The method may also include filling the opening with a copper alloy and forming a copper-containing layer over the copper alloy and the low-k dielectric layer. An etch rate of the copper-containing layer may be greater than an etch rate of the copper alloy. The method may additionally include patterning the copper-containing layer to form interconnect features over the low-k dielectric layer and the copper alloy.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: January 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Tsung-Jung Tsai
  • Patent number: 10177302
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a magnetic layer, and an upper structure provided on the stacked structure, and including a first portion and a second portion surrounding the first portion and formed of material different from that of the first portion.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shuichi Tsubata, Masatoshi Yoshikawa
  • Patent number: 10177003
    Abstract: A substrate is disposed on a substrate holder within a process module. The substrate includes a mask material overlying a target material with at least one portion of the target material exposed through an opening in the mask material. A bi-modal process gas composition is supplied to a plasma generation region overlying the substrate. For a first period of time, a first radiofrequency power is applied to the bi-modal process gas composition to generate a plasma to cause etching-dominant effects on the substrate. For a second period of time, after completion of the first period of time, a second radiofrequency power is applied to the bi-modal process gas composition to generate the plasma to cause deposition-dominant effects on the substrate. The first and second radiofrequency powers are applied in an alternating and successive manner for an overall period of time to remove a required amount of exposed target material.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: January 8, 2019
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Qian Fu, Ying Wu, Qing Xu, Hua Xiang
  • Patent number: 10163688
    Abstract: Among other things, one or more interconnect structures and techniques for forming such interconnect structures within integrated circuits are provided. An interconnect structure comprises one or more kinked structures, such as metal structures or via structures, formed according to a kinked profile. For example, the interconnect structure comprises a first kinked structure having a first tapered portion and a second kinked structure having a second tapered portion. The first tapered portion and the second tapered portion are both situated at an interface between two layers. Current leakage at the interface is mitigated because a length of the interface corresponds to a distance between the first tapered portion and the second tapered portion that is relatively larger than if the first kinked structure and the second kinked structure were merely formed according to a non-tapered shape.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Hao Chen, Chung-Chi Ko, Hsin-Yi Tsai
  • Patent number: 10084056
    Abstract: A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Wen Hsu, Hung-Ling Shih, Jiech-Fun Lu
  • Patent number: 10050047
    Abstract: The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a memory array region and a boundary region surrounding the memory array region. A hard mask layer is formed over the memory array region and the boundary region. The hard mask layer is patterned to form a boundary hard mask having one or more slots to expose some portions of the boundary region while the remaining regions of the boundary region are covered by the boundary hard mask. A floating gate layer is formed within the memory array region and extending over the hard mask layer. Then, a planarization is performed to reduce a height of the floating gate layer and form a plurality of floating gates.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chin-Yi Huang, Ya-Chen Kao
  • Patent number: 10049974
    Abstract: A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and is directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD is formed above the silicide, and a via is formed through the second ILD above one of the one or more metal lines. One or more second metal lines are formed above the second ILD, one of which is formed in the via. The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert Huang, Joe Lee
  • Patent number: 10043884
    Abstract: Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device. An opening is formed in an insulating film formed over a semiconductor substrate. At that time, a mask layer for formation of the opening is formed over the insulating film. The insulating film is dry etched and then wet etched. The dry etching step is finished before the semiconductor substrate is exposed at the bottom of the opening, and the wet etching step is finished after the semiconductor substrate is exposed at the bottom of the opening.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 7, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshikazu Hanawa
  • Patent number: 10037918
    Abstract: A method includes forming a first transistor and a second transistor over a substrate, wherein the first transistor and the second transistor share a drain/source region formed between a first gate of the first transistor and a second gate of the second transistor, forming a first opening in an interlayer dielectric layer and between the first gate and the second gate, depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer, depositing a dielectric layer over the etch stop layer, applying a first etching process to the dielectric layer until the etch stop layer is exposed, performing a second etching process on the etch stop layer until an exposed portion of the etch stop layer and portions of the dielectric layer have been removed.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu
  • Patent number: 10037940
    Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 31, 2018
    Assignee: Tessera, Inc.
    Inventors: Cyprian Emeka Uzoh, Belgacem Haba, Craig Mitchell
  • Patent number: 9991363
    Abstract: A contact etch stop layer includes a nitride layer formed over a sacrificial gate structure and a polysilicon layer formed over the nitride layer. During subsequent processing, the polysilicon layer is adapted to oxidize and form an oxide layer. The oxidation of the polysilicon layer effectively shields the underlying nitride contact etch stop layer from oxidation, which protects the mechanical integrity of the nitride layer.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: June 5, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haigou Huang, Jinsheng Gao, Haifeng Sheng, Jinping Liu, Huy Cao, Hui Zang
  • Patent number: 9972633
    Abstract: A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: May 15, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Hui Yang, Chow-Yee Lim
  • Patent number: 9922928
    Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and having an opening, and a plating film provided in the opening. A slit is provided in a side face of the opening, and the plating film is also disposed in the slit. Thus, the slit is provided in the side face of the opening, and the plating film is also grown in the slit. This results in a long penetration path of a plating solution during subsequent formation of the plating film. Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (pad region).
    Type: Grant
    Filed: July 23, 2016
    Date of Patent: March 20, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Tonegawa
  • Patent number: 9905509
    Abstract: A semiconductor interconnect structure is formed as a via with an inverted-T shape to increase the reliability of the interface between the interconnect structure and an underlying electrically conductive, e.g., copper (Cu), layer of material. The inverted-T shape effectively increases a bottom critical dimension of the via, thereby reducing and/or eliminating via degradation of the interconnect structure caused by voids in the electrically conductive layer introduced during high-temperature or stress-migration baking.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: February 27, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yen-Lu Chen, Shih-Ping Hong, Ta Hung Yang
  • Patent number: 9855727
    Abstract: A glass pane is described. The glass pane has at least one pane, and one adhesive layer on the pane. The adhesive layer has at least one thermoplastic film with a luminescent pigment and a barrier film with an anti-scratch coating.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: January 2, 2018
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventor: Michael Labrot
  • Patent number: 9859402
    Abstract: The present invention provides a manufacturing method of a semiconductor device, including providing a substrate, where a first dielectric layer is formed on the substrate, at least one gate is formed in the first dielectric layer, at least one hard mask is disposed on the top surface of the gate, and at least two spacers are disposed on two sides of the gate respectively. Next, a blanket implantation process is performed on the hard mask and the first dielectric layer, so as to form an ion rich region in the first dielectric layer, in the hard mask and in the spacer respectively. An etching process is then performed to form a plurality of trenches in the first dielectric layer, and a conductive layer is filled in each trench to form a plurality of contacts in the first dielectric layer.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Rai-Min Huang
  • Patent number: 9852920
    Abstract: Provided are a method and system for increasing etch rate and etch selectivity of a masking layer on a substrate in an etch treatment system, the etch treatment system configured for single substrate processing. The method comprises placing the substrate into the etch processing chamber, the substrate containing the masking layer and a layer of silicon or silicon oxide, obtaining a supply of steam water vapor mixture at elevated pressure, obtaining a supply of treatment liquid for selectively etching the masking layer over the silicon or silicon oxide at a selectivity ratio, combining the treatment liquid and the steam water vapor mixture, and injecting the combined treatment liquid and the steam water vapor mixture into the etch processing chamber. The flow of the combined treatment liquid and the steam water vapor mixture is controlled to maintain a target etch rate and a target etch selectivity ratio of the masking layer to the layer of silicon or silicon oxide.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: December 26, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Ian J. Brown, Wallace P. Printz
  • Patent number: 9852888
    Abstract: A circulating cooling/heating device that is configured to cool and heat a circulating fluid supplied to a chamber in plasma-etching equipment includes: a reservoir configured to store the circulating fluid; a pump configured to circulate the circulating fluid between the reservoir and the chamber; a heat exchanger configured to perform heat exchange between the circulating fluid and a cooling water, the heat exchanger being immersed in the circulating fluid stored in the reservoir; and a heater configured to heat the circulating fluid in the reservoir.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: December 26, 2017
    Assignee: KELK Ltd.
    Inventor: Daisuke Goto
  • Patent number: 9847231
    Abstract: A method of etching an insulation layer on an object to be processed in a process chamber in which an upper electrode and a lower electrode are placed facing each other, includes supplying a process gas that includes fluorocarbon gas and silicon tetrafluoride (SiF4) gas into the process chamber; applying high frequency power to at least one of the upper electrode and the lower electrode, to generate plasma; and etching the insulation layer by the generated plasma via a mask.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: December 19, 2017
    Assignee: Tokyo Electron Limited
    Inventor: Toshiharu Wada
  • Patent number: 9847252
    Abstract: A method of processing a substrate includes: depositing an etch stop layer atop a first dielectric layer; forming a feature in the etch stop layer and the first dielectric layer; depositing a first metal layer to fill the feature; etching the first metal layer to form a recess; depositing a second dielectric layer to fill the recess wherein the second dielectric layer is a low-k material suitable as a metal and oxygen diffusion barrier; forming a patterned mask layer atop the substrate to expose a portion of the second dielectric layer and the etch stop layer; etching the exposed portion of the second dielectric layer to a top surface of the first metal layer to form a via in the second dielectric layer; and depositing a second metal layer atop the substrate, wherein the second metal layer is connected to the first metal layer by the via.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: December 19, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bencherki Mebarki, Srinivas D. Nemani, Mehul Naik
  • Patent number: 9805971
    Abstract: Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region. A contact dielectric layer is formed on the substrate. The contact dielectric layer covers the substrate and device component. At least one contact opening is formed through the contact dielectric layer. Upper portion of the contact opening includes wider opening with tapered sidewall profile while lower portion of the contact opening includes narrower opening with vertical sidewall profile.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Rui Li, Chin Chuan Neo, Hai Cong