By Dry-etching (epo) Patents (Class 257/E21.252)
  • Patent number: 10510952
    Abstract: A storage device includes a first electrode, a stacked feature, a spacer and a barrier structure. The stacked feature is position over the first electrode, and includes a storage element and a second electrode over the storage element. The spacer is positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, in which the notch of the spacer has a surface which is continuous with a top surface of the stacked feature. The barrier structure is embedded in a lateral of the spacer. The barrier structure has a top extending upwards past a bottom of the notch.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 10410873
    Abstract: A method of etching a substrate is described. The method includes disposing a substrate having a surface exposing a first material and a second material in a processing space of a plasma processing system, and performing a modulated plasma etching process to selectively remove the first material at a rate greater than removing the second material. The modulated plasma etching process comprises a power modulation cycle having sequential power application steps that includes: applying a radio frequency (RF) signal to the plasma processing system at a first power level, applying the RF signal to the plasma processing system at a second power level, and applying the RF signal to the plasma processing system at a third power level. Thereafter, the power modulation cycle is repeated at least one more cycle, wherein each modulation cycle includes a modulation time period.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: September 10, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroto Ohtake, Takuya Mori
  • Patent number: 10374062
    Abstract: The present invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate includes a substrate and an insulation layer provided on the substrate, the insulation layer including a via therein formed by etching. The insulation layer further includes a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 6, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventor: Yanfei Sun
  • Patent number: 10297551
    Abstract: A method of manufacturing a redistribution circuit structure and a method of manufacturing an INFO package at least include the following steps. An inter-dielectric layer is formed over a substrate. A seed layer is formed over the inter-dielectric layer. A plurality of conductive patterns are formed over the seed layer. The seed layer and the conductive patterns include a same material. While maintain a substantially uniform pitch width in the conductive pattern, the seed layer exposed by the conductive patterns is selectively removed through a dry etch process to form a plurality of seed layer patterns. The conductive patterns and the seed layer patterns form a plurality of redistribution conductive patterns.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Yun-Chen Hsieh
  • Patent number: 10283370
    Abstract: Exemplary methods for selectively removing silicon nitride may include flowing a fluorine-containing precursor, and oxygen-containing precursor and a silicon-containing precursor into a local plasma to form plasma effluents. The plasma effluents may remove silicon nitride at significantly higher etch rates compared to exposed silicon oxide on the substrate. The methods may also remove silicon nitride more rapidly that silicon carbide and silicon oxycarbide which broadens the utility of the present technology to semiconductor applications.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: May 7, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Onintza Ros Bengoechea, Nancy Fung
  • Patent number: 10274374
    Abstract: An infrared sensor includes an infrared sensor pixel in which a contact hole is formed to electrically connect a metal wiring layer and a support leg metal wiring layer that is located inside a support leg. The metal wiring layer is electrically connected to a signal reading circuit. The contact hole is formed by etching an insulating layer that is formed by deposition so as to cover the metal wiring layer, and has a bottom portion and a side wall portion that are each shaped into a forward tapered shape.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 30, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takaki Sugino, Kenji Shintani, Koji Misaki
  • Patent number: 10249498
    Abstract: A method of controlling doping of a substrate, the method comprising: providing the substrate in a process chamber of a doping system; performing a doping process to impart a target dose on a surface of the substrate using a abruptness depth control technique; and controlling selected operating variables of plasma doping in order to meet doping objectives.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: April 2, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Peter L. G. Ventzek, Hirokazu Ueda
  • Patent number: 10186455
    Abstract: A method of manufacturing a semiconductor interconnect structure may include forming a low-k dielectric layer over a substrate and forming an opening in the low-k dielectric layer, where the opening exposes a portion of the substrate. The method may also include filling the opening with a copper alloy and forming a copper-containing layer over the copper alloy and the low-k dielectric layer. An etch rate of the copper-containing layer may be greater than an etch rate of the copper alloy. The method may additionally include patterning the copper-containing layer to form interconnect features over the low-k dielectric layer and the copper alloy.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: January 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Tsung-Jung Tsai
  • Patent number: 10177302
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a magnetic layer, and an upper structure provided on the stacked structure, and including a first portion and a second portion surrounding the first portion and formed of material different from that of the first portion.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shuichi Tsubata, Masatoshi Yoshikawa
  • Patent number: 10177003
    Abstract: A substrate is disposed on a substrate holder within a process module. The substrate includes a mask material overlying a target material with at least one portion of the target material exposed through an opening in the mask material. A bi-modal process gas composition is supplied to a plasma generation region overlying the substrate. For a first period of time, a first radiofrequency power is applied to the bi-modal process gas composition to generate a plasma to cause etching-dominant effects on the substrate. For a second period of time, after completion of the first period of time, a second radiofrequency power is applied to the bi-modal process gas composition to generate the plasma to cause deposition-dominant effects on the substrate. The first and second radiofrequency powers are applied in an alternating and successive manner for an overall period of time to remove a required amount of exposed target material.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: January 8, 2019
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Qian Fu, Ying Wu, Qing Xu, Hua Xiang
  • Patent number: 10163688
    Abstract: Among other things, one or more interconnect structures and techniques for forming such interconnect structures within integrated circuits are provided. An interconnect structure comprises one or more kinked structures, such as metal structures or via structures, formed according to a kinked profile. For example, the interconnect structure comprises a first kinked structure having a first tapered portion and a second kinked structure having a second tapered portion. The first tapered portion and the second tapered portion are both situated at an interface between two layers. Current leakage at the interface is mitigated because a length of the interface corresponds to a distance between the first tapered portion and the second tapered portion that is relatively larger than if the first kinked structure and the second kinked structure were merely formed according to a non-tapered shape.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Hao Chen, Chung-Chi Ko, Hsin-Yi Tsai
  • Patent number: 10084056
    Abstract: A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Wen Hsu, Hung-Ling Shih, Jiech-Fun Lu
  • Patent number: 10049974
    Abstract: A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and is directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD is formed above the silicide, and a via is formed through the second ILD above one of the one or more metal lines. One or more second metal lines are formed above the second ILD, one of which is formed in the via. The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert Huang, Joe Lee
  • Patent number: 10050047
    Abstract: The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a memory array region and a boundary region surrounding the memory array region. A hard mask layer is formed over the memory array region and the boundary region. The hard mask layer is patterned to form a boundary hard mask having one or more slots to expose some portions of the boundary region while the remaining regions of the boundary region are covered by the boundary hard mask. A floating gate layer is formed within the memory array region and extending over the hard mask layer. Then, a planarization is performed to reduce a height of the floating gate layer and form a plurality of floating gates.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chin-Yi Huang, Ya-Chen Kao
  • Patent number: 10043884
    Abstract: Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device. An opening is formed in an insulating film formed over a semiconductor substrate. At that time, a mask layer for formation of the opening is formed over the insulating film. The insulating film is dry etched and then wet etched. The dry etching step is finished before the semiconductor substrate is exposed at the bottom of the opening, and the wet etching step is finished after the semiconductor substrate is exposed at the bottom of the opening.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 7, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshikazu Hanawa
  • Patent number: 10037940
    Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 31, 2018
    Assignee: Tessera, Inc.
    Inventors: Cyprian Emeka Uzoh, Belgacem Haba, Craig Mitchell
  • Patent number: 10037918
    Abstract: A method includes forming a first transistor and a second transistor over a substrate, wherein the first transistor and the second transistor share a drain/source region formed between a first gate of the first transistor and a second gate of the second transistor, forming a first opening in an interlayer dielectric layer and between the first gate and the second gate, depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer, depositing a dielectric layer over the etch stop layer, applying a first etching process to the dielectric layer until the etch stop layer is exposed, performing a second etching process on the etch stop layer until an exposed portion of the etch stop layer and portions of the dielectric layer have been removed.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu
  • Patent number: 9991363
    Abstract: A contact etch stop layer includes a nitride layer formed over a sacrificial gate structure and a polysilicon layer formed over the nitride layer. During subsequent processing, the polysilicon layer is adapted to oxidize and form an oxide layer. The oxidation of the polysilicon layer effectively shields the underlying nitride contact etch stop layer from oxidation, which protects the mechanical integrity of the nitride layer.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: June 5, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haigou Huang, Jinsheng Gao, Haifeng Sheng, Jinping Liu, Huy Cao, Hui Zang
  • Patent number: 9972633
    Abstract: A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: May 15, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Hui Yang, Chow-Yee Lim
  • Patent number: 9922928
    Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and having an opening, and a plating film provided in the opening. A slit is provided in a side face of the opening, and the plating film is also disposed in the slit. Thus, the slit is provided in the side face of the opening, and the plating film is also grown in the slit. This results in a long penetration path of a plating solution during subsequent formation of the plating film. Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (pad region).
    Type: Grant
    Filed: July 23, 2016
    Date of Patent: March 20, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Tonegawa
  • Patent number: 9905509
    Abstract: A semiconductor interconnect structure is formed as a via with an inverted-T shape to increase the reliability of the interface between the interconnect structure and an underlying electrically conductive, e.g., copper (Cu), layer of material. The inverted-T shape effectively increases a bottom critical dimension of the via, thereby reducing and/or eliminating via degradation of the interconnect structure caused by voids in the electrically conductive layer introduced during high-temperature or stress-migration baking.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: February 27, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yen-Lu Chen, Shih-Ping Hong, Ta Hung Yang
  • Patent number: 9859402
    Abstract: The present invention provides a manufacturing method of a semiconductor device, including providing a substrate, where a first dielectric layer is formed on the substrate, at least one gate is formed in the first dielectric layer, at least one hard mask is disposed on the top surface of the gate, and at least two spacers are disposed on two sides of the gate respectively. Next, a blanket implantation process is performed on the hard mask and the first dielectric layer, so as to form an ion rich region in the first dielectric layer, in the hard mask and in the spacer respectively. An etching process is then performed to form a plurality of trenches in the first dielectric layer, and a conductive layer is filled in each trench to form a plurality of contacts in the first dielectric layer.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Rai-Min Huang
  • Patent number: 9855727
    Abstract: A glass pane is described. The glass pane has at least one pane, and one adhesive layer on the pane. The adhesive layer has at least one thermoplastic film with a luminescent pigment and a barrier film with an anti-scratch coating.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: January 2, 2018
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventor: Michael Labrot
  • Patent number: 9852920
    Abstract: Provided are a method and system for increasing etch rate and etch selectivity of a masking layer on a substrate in an etch treatment system, the etch treatment system configured for single substrate processing. The method comprises placing the substrate into the etch processing chamber, the substrate containing the masking layer and a layer of silicon or silicon oxide, obtaining a supply of steam water vapor mixture at elevated pressure, obtaining a supply of treatment liquid for selectively etching the masking layer over the silicon or silicon oxide at a selectivity ratio, combining the treatment liquid and the steam water vapor mixture, and injecting the combined treatment liquid and the steam water vapor mixture into the etch processing chamber. The flow of the combined treatment liquid and the steam water vapor mixture is controlled to maintain a target etch rate and a target etch selectivity ratio of the masking layer to the layer of silicon or silicon oxide.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: December 26, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Ian J. Brown, Wallace P. Printz
  • Patent number: 9852888
    Abstract: A circulating cooling/heating device that is configured to cool and heat a circulating fluid supplied to a chamber in plasma-etching equipment includes: a reservoir configured to store the circulating fluid; a pump configured to circulate the circulating fluid between the reservoir and the chamber; a heat exchanger configured to perform heat exchange between the circulating fluid and a cooling water, the heat exchanger being immersed in the circulating fluid stored in the reservoir; and a heater configured to heat the circulating fluid in the reservoir.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: December 26, 2017
    Assignee: KELK Ltd.
    Inventor: Daisuke Goto
  • Patent number: 9847252
    Abstract: A method of processing a substrate includes: depositing an etch stop layer atop a first dielectric layer; forming a feature in the etch stop layer and the first dielectric layer; depositing a first metal layer to fill the feature; etching the first metal layer to form a recess; depositing a second dielectric layer to fill the recess wherein the second dielectric layer is a low-k material suitable as a metal and oxygen diffusion barrier; forming a patterned mask layer atop the substrate to expose a portion of the second dielectric layer and the etch stop layer; etching the exposed portion of the second dielectric layer to a top surface of the first metal layer to form a via in the second dielectric layer; and depositing a second metal layer atop the substrate, wherein the second metal layer is connected to the first metal layer by the via.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: December 19, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bencherki Mebarki, Srinivas D. Nemani, Mehul Naik
  • Patent number: 9847231
    Abstract: A method of etching an insulation layer on an object to be processed in a process chamber in which an upper electrode and a lower electrode are placed facing each other, includes supplying a process gas that includes fluorocarbon gas and silicon tetrafluoride (SiF4) gas into the process chamber; applying high frequency power to at least one of the upper electrode and the lower electrode, to generate plasma; and etching the insulation layer by the generated plasma via a mask.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: December 19, 2017
    Assignee: Tokyo Electron Limited
    Inventor: Toshiharu Wada
  • Patent number: 9805971
    Abstract: Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region. A contact dielectric layer is formed on the substrate. The contact dielectric layer covers the substrate and device component. At least one contact opening is formed through the contact dielectric layer. Upper portion of the contact opening includes wider opening with tapered sidewall profile while lower portion of the contact opening includes narrower opening with vertical sidewall profile.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Rui Li, Chin Chuan Neo, Hai Cong
  • Patent number: 9786753
    Abstract: A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed with a two-step etching process as described in detail in the specification. The devices that embody this invention can be fabricated with higher packaging density and better and more tightly distributed device parameters such as the VF, RDSS, and BV.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: October 10, 2017
    Assignee: Diodes Incorporated
    Inventors: Yun-Pu Ku, Chiao-Shun Chuang, Cheng-Chin Huang
  • Patent number: 9780037
    Abstract: A plasma processing method can suppress both surface roughness of a wiring and surface roughness of a metal mask. The method includes generating plasma of a first processing gas containing a fluorocarbon gas and/or a hydrofluorocarbon gas to etch a diffusion barrier film until a copper wiring is exposed and generating plasma of a second processing gas containing a carbon-containing gas to form an organic film on a surface of a target object in which the diffusion barrier film is etched.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 3, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuya Kato, Toshihiko Shindo, Ryuichi Asako, Hiroshi Nagahata
  • Patent number: 9779954
    Abstract: Disclosed is a method of etching a silicon layer by removing an oxide film formed on a workpiece which includes the silicon layer and a mask provided on the silicon layer. The method includes: (a) forming a denatured region by generating plasma of a first processing gas containing hydrogen, nitrogen, and fluorine within a processing container accommodating the workpiece therein to denature an oxide film formed on a surface of the workpiece; (b1) removing the denatured region by generating plasma of a rare gas within the processing container; and (c) etching the silicon layer by generating plasma of a second processing gas within the processing container.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: October 3, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akinori Kitamura, Eiji Suzuki
  • Patent number: 9741540
    Abstract: In a method for surface treatment of an upper electrode, a first step is performed to roughen a facing surface of the upper electrode facing a lower electrode while depositing a CF-based deposit on the facing surface by using a plasma of a processing gas by supplying a first and second high frequency powers to the lower and upper electrode. A second step is performed to remove a part of the CF-based deposit by using a plasma of a processing gas by supplying the second high frequency power to the upper electrode only, and a third step is performed to remove the CF-based deposit remaining in the second step by using a plasma of a processing gas by supplying the first and second high frequency powers to the lower and upper electrode. Further, the first, second and third steps are repeated multiple times.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: August 22, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yusuke Aoki
  • Patent number: 9735028
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hao Chen, Yu-Shu Chen, Yu-Cheng Liu
  • Patent number: 9711401
    Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 18, 2017
    Assignee: Tessera, Inc.
    Inventors: Cyprian Emeka Uzoh, Belgacem Haba, Craig Mitchell
  • Patent number: 9691630
    Abstract: An etching method includes loading a target substrate W into a chamber 40, the target substrate W having a silicon nitride film formed thereon and at least one of a polysilicon film and a silicon oxide film formed adjacent to the silicon nitride film; supplying a fluorine (F)-containing gas and an O2 gas into the chamber 40, while at least the O2 gas is excited; and selectively etching the silicon nitride film with respect to at least one of the polysilicon film and the silicon oxide film using the F-containing gas and the O2 gas.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: June 27, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Nobuhiro Takahashi, Tetsuro Takahashi, Shuji Moriya, Masashi Matsumoto, Junichiro Matsunaga
  • Patent number: 9691703
    Abstract: A bond pad structure with dual passivation layers is disclosed. The bond pad structure includes: a pad material layer on a first passivation layer; a protection layer on the top surface of the pad material layer; a second passivation layer covering on the first passivation layer and the protection layer; and an opening formed through the second passivation layer and the protection layer to expose the pad material layer.
    Type: Grant
    Filed: January 10, 2016
    Date of Patent: June 27, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ye Wang
  • Patent number: 9679802
    Abstract: A method for producing interconnection lines including etching a layer of porous dielectric material forming a trench and filling the trench is provided. The etching is carried out in a plasma so as to grow, all along the etching, a protective layer on flanks of the layer of porous dielectric material. The plasma is formed from a gas formed from a first component and a second component, or a gas formed from a first component, a second component and a third component. The first component is a hydrocarbon of the CXHY type, where X is the proportion of carbon in the gas and Y the proportion of hydrogen in the gas; the second component is taken from nitrogen or dioxygen or a mixture of nitrogen and dioxygen; the third component is taken from argon or helium; and the protective layer is based on hydrocarbon.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: June 13, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Posseme
  • Patent number: 9679746
    Abstract: An ion implantation tool includes a process chamber, a platen, an ion source, and a plurality of controlling units. The platen is present in the process chamber and configured to hold a wafer. The ion source is configured to provide an ion beam onto the wafer. The controlling units are present on the platen and configured to apply a plurality of physical fields that are able to affect motions of ions of the ion beam onto the wafer.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Sheng-Wei Lee
  • Patent number: 9666472
    Abstract: The present invention provides a method for controlling a critical dimension of shallow trench isolations in a STI etch process, comprises the following steps: before the STI etch process, pre-establishing a mapping relation between a post-etch and pre-etch critical dimension difference of a BARC layer and a thickness of the BARC layer; and during the STI etch process after coating the BARC layer, measuring the thickness of the BARC layer and determining a trimming time for a hard mask layer according to a critical dimension difference corresponding to the measured thickness in the mapping relation and a critical dimension of a photoresist pattern, then performing a trimming process for the hard mask layer lasting the trimming time to make a critical dimension of the hard mask layer equal to a required critical dimension of an active area, and etching a substrate to form shallow trenches with a predetermined critical dimension.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: May 30, 2017
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Jin Xu, Qiyan Feng, Yu Ren, Yukun Lv, Xusheng Zhang
  • Patent number: 9659820
    Abstract: A method of forming a wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: May 23, 2017
    Assignees: International Business Machines Corporation, STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise, Akil K. Sutton, Terry Allen Spooner, Nicole A. Saulnier
  • Patent number: 9647095
    Abstract: A semiconductor device formed using an oxide semiconductor layer and having small electrical characteristic variation is provided. A highly reliable semiconductor device including an oxide semiconductor layer and exhibiting stable electric characteristics is provided. Further, a method for manufacturing the semiconductor device is provided. In the semiconductor device, an oxide semiconductor layer is used for a channel formation region, a multilayer film which includes an oxide layer in which the oxide semiconductor layer is wrapped is provided, and an edge of the multilayer film has a curvature in a cross section.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: May 9, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa
  • Patent number: 9607855
    Abstract: An etching method includes: disposing a target substrate including a silicon and a silicon-germanium within a chamber; and performing both of selectively etching the silicon-germanium with respect to the silicon and selectively etching the silicon with respect to the silicon-germanium by varying ratios of F2 gas and NH3 gas in an etching gas that has a gas system including the F2 gas and the NH3 gas.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: March 28, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Nobuhiro Takahashi, Masashi Matsumoto, Ayano Hagiwara, Koji Takeya, Junichiro Matsunaga
  • Patent number: 9504249
    Abstract: The present invention provides a control agent for a plant pest and/or a plant disease, the control agent being environmentally friendly and having a high control effect. The control agent is a control agent for a plant pest and/or a plant disease, containing a polyglycerin fatty acid ester as an active ingredient. The polyglycerin fatty acid ester is an ester of at least one fatty acid selected from fatty acids having 8 to 10 carbon atoms, and at least one polyglycerin obtained by polymerizing 3 to 10 glycerins.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: November 29, 2016
    Assignee: RIKEN
    Inventors: Yutaka Arimoto, Takayuki Kashima
  • Patent number: 9466701
    Abstract: Processes for preparing an integrated circuit for contact landing, processes for fabricating an integrated circuit, and integrated circuits prepared according to these processes are provided herein. An exemplary process for preparing an integrated circuit for contact landing includes providing a semiconductor structure that includes a transistor with source and drain regions, wherein at least one of the source and drain regions has a shaped contact structure overlaid with a contact etch stop layer and a pre-metal dielectric material. The pre-metal dielectric material is removed with one or more anisotropic etches, including at least one anisotropic etch selective to the pre-metal dielectric material. And, the contact etch stop layer overlaying the shaped contact structure is removed with a third anisotropic etch selective to the contact etch stop layer material to expose the shaped contact structure.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Sandeep Gaan, Sipeng Gu
  • Patent number: 9461144
    Abstract: A method of forming a semiconductor device is disclosed. The method includes exposing a dummy oxide layer of a gate structure to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature, wherein the dummy oxide layer is formed over a substrate and surrounded by a gate spacer that includes a material different from that of the dummy oxide layer. The method further includes rinsing the substrate with a solution containing de-ionized water (DIW) at a second temperature. The method may further include baking the substrate in a chamber heated to a third temperature higher than the first and second temperatures. The exposing, rinsing, and baking steps remove the dummy oxide layer thereby forming an opening in the gate spacer. The method may further include forming a gate stack having a high-k gate dielectric layer and a metal gate electrode in the opening.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: October 4, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hsi Yeh, Hsin-Yan Lu, Chao-Cheng Chen, Syun-Ming Jang
  • Patent number: 9419109
    Abstract: A semiconductor device comprises a substrate, a gate structure and a gate spacer. The substrate has a semiconductor fin protruding from a surface of the substrate. The gate structure is disposed on the semiconductor fin. The gate spacer is disposed on sidewalls of the gate structure, wherein the gate spacer comprises a first material layer and a second material layer stacked with each other and both of these two material layers are directly in contact with the gate structure.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: August 16, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jhen-Cyuan Li, Shui-Yen Lu
  • Patent number: 9412649
    Abstract: A method for fabricating a semiconductor device includes forming a hard mask (HM) layer over a material layer, forming a first trench in the HM layer, which extends along a first direction. The method also includes forming a first patterned resist layer over the HM layer. The first patterned resist layer has a first opening and a second opening a second direction. The first opening overlaps with the first trench in a middle portion of the first trench and the second opening overlaps with the first trench at an end portion of the first trench. The method also includes etching the HM layer through the first patterned resist layer to form a second trench and a third trench in the HM layer and forming a first feature to fill in a section of the first trench between the second trench and the third trench.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
  • Patent number: 9406775
    Abstract: Methods for forming a self-aligned gate-cut in close proximity to a gate contact and the resulting device are disclosed. Embodiments include providing a substrate with silicon fins and a metal gate with a nitride-cap perpendicular to and over the fins, with source/drain regions, each with an oxide-cap, on the fins on opposite sides of the gate; forming parallel dielectric lines, separated from each other, perpendicular to and over the gate; forming a photoresist over the parallel dielectric lines, forming an opening in the photoresist exposing a nitride-cap between two fins; removing the exposed nitride-cap exposing an underlying metal gate; removing the exposed metal gate and a remainder of the photoresist; forming low-k dielectric lines between the parallel dielectric lines; removing sections of the parallel dielectric lines; forming perpendicular interconnects between the low-k dielectric lines; removing a remainder of the parallel dielectric lines forming trenches; and filling the trenches with metal.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Wei, Youngtag Woo
  • Patent number: 9393767
    Abstract: A method for making a strip shaped graphene layer includes the following steps. First, a graphene film located on a surface of a substrate is provided. Second, a drawn carbon nanotube film composite is disposed on the graphene film. The drawn carbon nanotube film composite includes a polymer material and a drawn carbon nanotube film structure disposed in the polymer material. The drawn carbon nanotube film structure includes a number of carbon nanotube segments and a number of strip-shaped gaps between the adjacent carbon nanotube segments. Third, the polymer material is partly removed to expose the carbon nanotube segments. Fourth, the carbon nanotube segments and the graphene film covered by the plurality of carbon nanotube segments are etched. Fifth, the remained polymer material is removed to obtain the strip shaped graphene layer.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: July 19, 2016
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Xiao-Yang Lin, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 9396968
    Abstract: An etching method is provided that includes the steps of supplying an etching gas containing a fluorocarbon (CF) based gas into a processing chamber, generating a plasma from the etching gas, and etching a silicon oxide film through a polysilicon mask using the plasma. The polysilicon film has a predetermined pattern and is arranged on the silicon oxide film. The silicon oxide film has at least one of a silicon content per unit volume, a fluorine content per unit volume, and a volume density that varies in a depth direction.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: July 19, 2016
    Assignee: Tokyo Electron Limited
    Inventor: Kazuhiro Kubota