Abstract: An image sensor capable of overcoming a decrease in photo sensitivity resulted from using a single crystal silicon substrate, and a method for fabricating the same are provided. An image sensor includes a single crystal silicon substrate, an amorphous silicon layer formed inside the substrate, a photodiode formed in the amorphous silicon layer, and a transfer gate formed over the substrate adjacent to the photodiode and transferring photoelectrons received from the photodiode.

Abstract: A light emitting device according to the embodiment includes a first electrode; a light emitting structure including a first semiconductor layer over the first electrode, an active layer over the first semiconductor layer, and a second semiconductor layer over the second semiconductor layer; a second electrode over the second semiconductor layer; and a connection member having one end making contact with the first semiconductor layer and the other end making contact with the second semiconductor layer to form a schottky contact with respect to one of the first and second semiconductor layers.

Abstract: A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming.

Abstract: This semiconductor device includes: a substrate; and a plurality of thin-film diodes which are supported by the substrate and electrically connected in parallel with each other. The thin-film diodes include at least one thin-film diode of a first type (100A), of which the semiconductor layer (10A) has an N-type region (1A), an intrinsic region (5A), and a P-type region (3A) that are arranged in this order in a first direction X within a plane that is parallel to the substrate, and at least one thin-film diode of a second type (100B), of which the semiconductor layer (10B) has a P-type region (3B), an intrinsic region (5B), and an N-type region (1B) that are arranged in this order in the first direction X. With such a configuration adopted, the variation in photocurrent characteristic between the thin-film diodes can be reduced.

Abstract: A nano/micro-sized diode and a method of preparing the same, the diode including: a first electrode; a second electrode; and a diode layer that is disposed between the first electrode and the second electrode. The diode layer includes a first layer and a second layer. The first layer is disposed on the first electrode and has a first surface that is electrically connected to the first electrode, and an opposing second surface that has a protrusion. The second layer is disposed between the first layer and the second electrode and has a first surface having a recess that corresponds to the protrusion, and an opposing second surface that is electrically connected to the second electrode.

Abstract: A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.

Abstract: A semiconductor patch antenna for microwave radiation having a wide pin-junction or pn-junction with the depletion region or embodiments having a separating buried oxide (SiO2) layer between p- and n-doped regions as the natural resonator volume. Embodiments that do not include a metal ground plane and/or a metal patch are disclosed.

Abstract: Compounds comprising a ligand having a quinoline or isoquinoline moiety and a phenyl moiety, e.g., (iso)pq ligands. In particular, the ligand is further substituted with electron donating groups. The compounds may be used in organic light emitting devices, particularly devices with emission in the deep red part of the visible spectrum, to provide devices having improved properties.

Abstract: Disclosed are a light emitting device and a method for manufacturing the same. The light emitting device includes a substrate having a lead frame, a light emitting diode mounted on the substrate, a mold member formed on the substrate and the light emitting diode, and a reflecting member having an opening portion at one side thereof and being inclined at an outer portion of the mold member.

Abstract: A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

Abstract: A semiconductor component includes a semiconductor body having a first surface and a second surface, and having an inner region and an edge region. The semiconductor component further includes a pn-junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region. A first trench extends from the first side in the edge region into the semiconductor body. The trench has sidewalls that are arranged opposite to another and that are beveled relative to a horizontal direction of the semiconductor body.

Abstract: The present invention relates to a technology for reducing dark current noise by discharging electrons accumulated on a surface of an image sensor photodiode. In an N-type or P-type photodiode, a channel is formed between the photodiode and a power voltage terminal, so that electrons (or holes) accumulated on a surface of the photodiode are discharged to the power voltage terminal through the channel.

Abstract: To provide a stacked photoelectric conversion device and a method for producing the same, in which an interlayer is provided between photoelectric conversion layers to obtain an effect of controlling the amount of incidence light, and carrier recombination at an interface between the interlayer and a semiconductor layer is decreased to enhance photoelectric conversion efficiency. The stacked photoelectric conversion device of the present invention comprises a plurality of silicon-based photoelectric conversion layers having a p-i-n structure stacked, wherein at least a pair of adjacent photoelectric conversion layers have an interlayer of a silicon nitride therebetween, the pair of the photoelectric conversion layers are electrically connected with each other, and a p-type silicon-based semiconductor layer constituting a part of the photoelectric conversion layer and contacting the interlayer contains a nitrogen atom.

Abstract: A light emitting diode chip includes a device for protection against overvoltages, e.g., an ESD protection device. The ESD protection device is integrated into a carrier, on which the semiconductor layer sequence of the light emitting diode chip is situated, and is based on a specific doping of specific regions of said carrier. By way of example, the ESD protection device is embodied as a Zener diode that is connected to the semiconductor layer sequence by means of an electrical conductor structure.

Abstract: The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0?x?1, 0?y?1, and 0?x+y?1.

Abstract: A light emitting device includes a first semiconductor layer of a first conductivity type, an active layer adjacent to the first semiconductor layer, a second semiconductor layer of a second conductivity type and provided adjacent to the active layer, and a passivation layer provided on a side surface of the active layer. The passivation layer may be a semiconductor layer of one of the first conductivity type, the second conductivity type or a first undoped semiconductor layer. A first electrode may be coupled to the first semiconductor layer and a second electrode may be coupled to the second semiconductor layer.

Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.

Abstract: A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Abstract: Methods of fabricating bypass diodes for solar cells are described. In one embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed on the first conductive region. In another embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed within, and surrounded by, an uppermost portion of the first conductive region but is not formed in a lowermost portion of the first conductive region.

Abstract: A light emitting device may include a plurality of nano-structures having a strip shape, each including a first nano-structure and a second nano-structure, the first nano-structures being the same height on the buffer layer.

Abstract: A mesa-type bidirectional vertical power component, including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; first regions of the first conductivity type in each of the layers of the second conductivity type; and, at the periphery of each of its surfaces, two successive grooves, the internal groove crossing the layers of the second conductivity type, second doped regions of the first conductivity type being formed under the surface of the external grooves and having the same doping profile as the first regions.

Abstract: A light-emitting diode structure includes a base with a recessed portion, a light-emitting chip and a light-transmissive block. The light-emitting chip disposed in the recessed portion of the base and emits a light beam. The light-transmissive block disposed on the base covers the recessed portion and the light-emitting chip, so that the light beam emitted from the light-emitting chip is radiated outwardly via the light-transmissive block. The light-transmissive block is a flat-top multilateral cone including a bottom surface, a top surface, and several side surfaces connected to and located between the bottom surface and the top surface. A slot with a bottom portion is formed on the top surface of the light-transmissive block.

Abstract: A semiconductor thermoelectric cooler is configured to direct heat through channels of the cooler. The thermoelectric cooler has multiple electrodes and a first dielectric material positioned between side surfaces of the electrodes. A second dielectric material, different from the first dielectric material, is in contact with top surfaces of the electrodes. The first dielectric material extends above the top surface of the electrodes, separating portions of the second dielectric material, and is in contact with a portion of the top surfaces of the electrodes. The first dielectric material has a thermal conductivity different than a thermal conductivity of the second dielectric material. A ratio of the first dielectric material to the second dielectric material in contact with the top surface of the electrodes may be selected to control the heat retention. The semiconductor thermoelectric cooler may be manufactured using thin film technology.

Abstract: The present invention discloses an organic light emitting diode and a manufacturing method thereof. The OLED comprises a first electrode, a first hole-transporting layer disposed on the first electrode, a second hole-transporting layer disposed on the first hole-transporting layer, a first light-emitting layer disposed on the second hole-transporting layer, an electron-transporting layer disposed on the first light-emitting layer, an electron injection layer disposed on the electron-transporting layer and a second electrode disposed on the electron injection layer. The energy level of the first light-emitting layer in the lowest unoccupied molecular orbital is lower than that of the second hole-transporting layer, and the thickness of the first hole-transporting layer is larger than that of the second hole-transporting layer.

Abstract: An array of pixels is formed using a semiconductor layer having a frontside and a backside through which incident light is received. Each pixel typically includes a photosensitive region formed in the semiconductor layer and a trench formed adjacent to the photosensitive region. The trench causes the incident light to be directed away from the trench and towards the photosensitive region.

Abstract: Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.

Abstract: The present disclosure relates to structures of LED components that integrate thermoelectric devices with LEDs on LED emitter substrates for cooling the LEDs. The present disclosure also related to methods for integrating LED dies with thermoelectric elements. The LED component includes an LED emitter substrate with a cavity in a downward facing surface of the LED emitter substrate and thermal vias that extend from a bottom of the cavity to an area close to an upward facing surface of the LED emitter substrate. The device also includes thermoelectric elements disposed in the cavity where the thermoelectric elements connect with their corresponding thermal vias. The device further includes a thermoelectric substrate in the cavity to electrically connect to the thermoelectric elements. The device further includes an LED die on the upward facing surface of the LED emitter substrate such that the LED die is opposite the cavity.

Abstract: A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate is disclosed. The substrate includes an insulator layer and an epitaxial layer overlying the insulator layer. A bond pad region is formed extending into the epitaxial layer to a surface of the insulator layer. A bond pad is fabricated partially overlying the bond pad region. At least one imaging component is fabricated partially overlying and extending into the epitaxial layer. A passivation layer is fabricated overlying the epitaxial layer, the bond pad, and the at least one imaging component. A handle wafer is bonded to the passivation layer. A portion of the insulator layer and a portion of the bond pad region is etched to expose a portion of the bond pad.

Abstract: A diode and memory device including the diode, where the diode includes a conductive portion and another portion formed of a first material that has characteristics allowing a first decrease in a resistivity of the material upon application of a voltage to the material, thereby allowing current to flow there through, and has further characteristics allowing a second decrease in the resistivity of the first material in response to an increase in temperature of the first material.

Abstract: In some embodiments of the invention, a device includes a substrate and a semiconductor structure. The substrate includes a wavelength converting element comprising a wavelength converting material disposed in a transparent material, a seed layer comprising a material on which III-nitride material will nucleate, and a bonding layer disposed between the wavelength converting element and the seed layer. The semiconductor structure includes a III-nitride light emitting layer disposed between an n-type region and a p-type region, and is grown on the seed layer.

Abstract: An LED package structure includes a heatsink slug, a positive-electrode frame, a negative-electrode frame, and an LED module electrically connected with the positive-electrode frame and the negative-electrode frame. The LED module includes a plurality of LED chips. The heatsink slug is provided, at its surface, with a plurality of cup-like recesses. The plural LED chips are each bonded, correspondingly, on a plane in the cup-like recess. Each of the LED chips is covered with a fluorescent colloidal layer having a curved and convex contour. As a result, a specific proportion for the color lights emitted from all the LED chips and from the fluorescent material in every direction of a space can be maintained, and that a better spatial color uniformity can be achieved.

Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode including metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.

Abstract: An integrated circuit includes a Schottky diode having a cathode defined by an n-type semiconductor region, an anode defined by a cobalt silicide region, and a p-type region laterally annularly encircling the cobalt silicide region. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation. An n+-type contact region is laterally separated by the p-type region from the first silicide region and a second cobalt silicide region is formed in the n-type contact region. The silicided regions are defined by openings in a silicon blocking dielectric layer. Dielectric material is left over the p-type region. The p-type region may be formed simultaneously with source/drain regions of a PMOS transistor.

Abstract: A method for forming a field effect power semiconductor is provided. The method includes providing a semiconductor body, a conductive region arranged next to a main surface of the semiconductor body, and an insulating layer arranged on the main horizontal surface. A narrow trench is etched through the insulating layer to expose the conductive region. A polycrystalline semiconductor layer is deposited and a vertical poly-diode structure is formed. The polycrystalline semiconductor layer has a minimum vertical thickness of at least half of the maximum horizontal extension of the narrow trench. A polycrystalline region which forms at least a part of a vertical poly-diode structure is formed in the narrow trench by maskless back-etching of the polycrystalline semiconductor layer. Further, a semiconductor device with a trench poly-diode is provided.

Abstract: Electrical energy is generated in a device that includes an integrated circuit which produces thermal flux when operated. A substrate supports the integrated circuit. A structure is formed in the substrate, that structure having a semiconductor p-n junction thermally coupled to the integrated circuit. Responsive to the thermal flux produced by the integrated circuit, the structure generates electrical energy. The generated electrical energy may be stored for use by the integrated circuit.

Abstract: A method for manufacturing a semiconductor device includes: irradiating a growth substrate with laser light to focus the laser light into a prescribed position inside a crystal for a semiconductor device or inside the growth substrate, the crystal for the semiconductor device being formed on a first major surface of the growth substrate; moving the laser light in a direction parallel to the first major surface; and peeling off a thin layer including the crystal for the semiconductor device from the growth substrate, a wavelength of the laser light being longer than an absorption end wavelength of the crystal for the semiconductor device or the growth substrate, the laser light being irradiated inside a crystal for the semiconductor device or inside the growth substrate.

Abstract: A method for forming a nonvolatile memory cell is provided that includes: (1) forming a rail-shaped first conductor above a substrate, (2) forming a rail-shaped second conductor above the first conductor, and (3) forming a substantially vertical first pillar disposed between the first conductor and the second conductor. The first pillar includes a vertically oriented p-i-n diode, and the p-i-n diode includes: (a) a bottom heavily doped region having a first conductivity type, (b) a middle intrinsic or lightly doped region, and (c) a top heavily doped region having a second conductivity type opposite the first conductivity type. The bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF2 ions. Numerous additional aspects are provided.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming islands by forming deep trenches within scribe lines of a substrate. The islands have a first notch disposed on sidewalls of the islands. A first electrode stack is formed over a top surface of the islands. The back surface of the substrate is thinned to separate the islands. A second electrode stack is formed over a back surface of the islands.

Abstract: A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming.

Abstract: A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level of impurities, an undoped silicon epitaxial layer formed over the SiGe epitaxial layer by epitaxial growth, and a photodiode region formed from a top surface of the undoped silicon epitaxial layer to a predetermined depth in the SiGe epitaxial layer.

Abstract: An active matrix pixel device is provided, for example an electroluminescent display device, the device comprising circuitry supported by a substrate and including a polysilicon TFT (10) and an amorphous silicon thin film PIN diode (12). Polysilicon islands are formed before an amorphous silicon layer is deposited for the PIN diode. This avoids the exposure of the amorphous silicon to high temperature processing. The TFT comprises doped source/drain regions (16a,17a), one of which (17a) may also provide the n-type or p-type doped region for the diode. Advantageously, the requirement to provide a separate doped region for the photodiode is removed, thereby saving processing costs. A second TFT (10b) having a doped source/drain region (16b,17b) of the opposite conductivity type may provide the other doped region (16b) for the diode, wherein the intrinsic region (25) is disposed laterally between the two TFTs, overlying each of the respective polysilicon islands.

Abstract: A semiconductor device has a conductive via formed through in a first side of the substrate. A first interconnect structure is formed over the first side of the substrate. A semiconductor die or component is mounted to the first interconnect structure. An encapsulant is deposited over the first interconnect structure and semiconductor die or component. A portion of a second side of the substrate is removed to reduce its thickness and expose the TSV. A second interconnect structure is formed over the second side of the substrate. The encapsulant provides structural support while removing the portion of the second side of the substrate. The second interconnect structure is electrically connected to the conductive via. The second interconnect structure can include a redistribution layer to extend the conductivity of the conductive via. The semiconductor device is mounted to a printed circuit board through the second interconnect structure.

Abstract: Bypass diodes for solar cells are described. In one embodiment, a bypass diode for a solar cell includes a substrate of the solar cell. A first conductive region is disposed above the substrate, the first conductive region of a first conductivity type. A second conductive region is disposed on the first conductive region, the second conductive region of a second conductivity type opposite the first conductivity type.

Abstract: A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-Site, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.

Abstract: Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

Abstract: An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device—P-I-N diode structures.

Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a first pixel having a first photodiode and a first readout circuit and a second pixel having a second photodiode and a second readout circuit. The second pixel is aligned at one side of the first pixel, and a light receiving area of the first photodiode is different from a light receiving area of the second photodiode.

Abstract: An image sensor capable of overcoming a decrease in photo sensitivity resulted from using a single crystal silicon substrate, and a method for fabricating the same are provided. An image sensor includes a single crystal silicon substrate, an amorphous silicon layer formed inside the substrate, a photodiode formed in the amorphous silicon layer, and a transfer gate formed over the substrate adjacent to the photodiode and transferring photoelectrons received from the photodiode.