Abstract: A fabrication method of a pixel structure includes providing a substrate. A semiconductor layer and a first conductive layer are formed on the substrate in sequence and patterned to form a semiconductor pattern and a data line pattern. A gate insulation layer and a second conductive layer are formed on the substrate in sequence and patterned to form a gate pattern and a scan line pattern connected to each other. A source region, a drain region, a channel region, and a lightly doped region are formed in the semiconductor pattern. A third conductive layer formed on the substrate is patterned to form a source pattern and a drain pattern. A protective layer is formed on the substrate and patterned to form a contact window to expose the drain pattern. A pixel electrode electrically connected to the drain pattern through the contact window is formed on the protective layer.

Abstract: A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.

Abstract: Disclosed herein is a rapid annealing method in a mixed structure composed of a heat treatment-requiring material, dielectric layer and conductive layer, comprising that during rapid annealing on a predetermined part of the heat treatment-requiring material, by instantaneously generated intense heat due to Joule heating by application of an electric field to the conductive layer, the potential difference between the heat treatment-requiring material and the conductive layer is set lower than the dielectric break-down voltage of the dielectric layer, thereby preventing generation of arc by dielectric breakdown of the dielectric layer during the annealing.

Abstract: A thin film transistor, a method of fabricating the same, and an organic light emitting diode display device having the same, the thin film transistor including: a substrate; a silicon layer formed on the substrate; a diffusion layer formed on the silicon layer; a semiconductor layer that is crystallized using a metal catalyst, formed on the diffusion layer; a gate electrode disposed on the diffusion layer, facing a channel region of the semiconductor layer; a gate insulating layer disposed between the gate electrode and the semiconductor layer; and source and drain electrodes electrically connected to source and drain regions of the semiconductor layer.

Abstract: A method of forming a polycrystalline silicon layer includes forming an amorphous silicon layer on a substrate by chemical vapor deposition using a gas including a silicon atom and hydrogen gas, and crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal. The resultant polycrystalline silicon layer has an improved charge mobility.

Abstract: A semiconductor device includes a vertically extending semiconductor portion above a semiconductor substrate, first and second diffusion regions being disposed near the bottom and top portions of the vertically extending semiconductor portion, respectively. A gate insulating film extends along the side surface of the vertically extending semiconductor portion which is separated by the gate insulating film from a gate electrode. The level of the top portion of the gate electrode is nearly equal to or lower than the level of the bottom portion of the second diffusion regions and the level of the bottom portion of the gate electrode is nearly equal to or higher than the level of the top portion of the first diffusion region.

Abstract: A transistor includes a substrate, an active region including a source region, a channel region, and a drain region which are crystallized using an SGS crystallization method and are formed on the substrate so that a grain size of a first annealed portion and a second annealed portion are different from each other, a gate insulating layer formed on the active region, and a gate electrode formed on the gate insulating layer.

Abstract: A method for forming a thin film transistor on a substrate is disclosed. A gate electrode and a gate insulation layer are disposed on a surface of the substrate. A deposition process is performed by utilizing hydrogen diluted silane to form a silicon-contained thin film on the gate insulation layer first. A hydrogen plasma etching process is thereafter performed. The deposition process and the etching process are repeated for at least one time to form an interface layer. Finally, an amorphous silicon layer, n+ doped Si layers, a source electrode, and a drain electrode are formed on the interface layer.

Abstract: A thin film transistor array panel is provided, which includes: a substrate; a first polysilicon member that is formed on the substrate and includes an intrinsic region, at least one first extrinsic region, and at least one second extrinsic region disposed between the intrinsic region and the at least one first extrinsic region and having an impurity concentration lower than the at least one first extrinsic region; a first insulator formed on the first polysilicon member and having an edge substantially coinciding with a boundary between the at least one first extrinsic region and the at least one second extrinsic region; and a first electrode formed on the first insulator and having an edge substantially coinciding with a boundary between the intrinsic region and the at least one second extrinsic region.

Abstract: A semiconductor device in which a semiconductor layer of a thin film transistor and a first electrode of a capacitor are formed of amorphous silicon and the whole or a part of source/drain regions of the semiconductor layer and the first electrode of the capacitor are crystallized by a metal induced crystallization method, and a channel region of the semiconductor layer is crystallized by a metal induced lateral crystallization method.

Abstract: A TFT substrate includes a substrate and at least a TFT disposed thereon. The TFT includes a semiconductor island and at least a gate. The semiconductor island has a source region, a drain region, and a channel region interposed therebetween. The semiconductor island has sub-grain boundaries. The gate corresponds to the channel region. A first included angle between an extending direction of the gate and a line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 90 degrees. A second included angle between the sub-grain boundaries in the channel region and the line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 0 degree or 90 degrees. Additionally, a method of fabricating a TFT substrate, an electronic apparatus, and a method of fabricating the electronic apparatus are also provided.

Abstract: A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and including source and drain regions, each having a first metal catalyst crystallization region and a second metal catalyst crystallization region, and a channel region having the second metal catalyst crystallization region, a gate electrode disposed in a position corresponding to the channel region of the semiconductor layer, a gate insulating layer interposed between the semiconductor layer and the gate electrode to electrically insulate the semiconductor layer from the gate electrode, and source and drain electrodes electrically insulated from the gate electrode and electrically connected to the source and drain regions, respectively. An OLED display device includes the thin film transistor and a first electrode, an organic layer, and a second electrode electrically connected to the source and drain electrodes.

Abstract: The substrate with electrodes is formed of a transparent material onto which is deposited a film (1) of a transparent conductive material of thickness e1 and of refractive index n1, said film being structured to form a set of electrodes (1a) whose contours (8) delimit insulating spaces (3), wherein the insulating spaces (3) are filled with a transparent dielectric material of thickness e2 and of refractive index n2 so that the respective thicknesses of the conductive material and the dielectric material are inversely proportional to the values of the refractive indices of said materials and said dielectric material forms neither depressions nor beads at the contour (8) of the electrodes. A hardcoating layer (7) may be disposed between the substrate (5) and the electrodes and a protective film (9) added. The substrate with electrodes is obtained by UV irradiation through a single mask.

Abstract: A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device including the TFT. The TFT includes a substrate having a pixel region and a non-pixel region, a semiconductor layer, a gate insulating layer, a gate electrode, and source and drain electrodes disposed on the pixel region, at least one gettering site disposed on the non-pixel region, and at least one connection portion to connect the at least one gettering site and the semiconductor layer The method of fabricating the TFT includes patterning a polycrystalline silicon (poly-Si) layer to form a plurality of semiconductor layers, connection portions, and at least one gettering site, the semiconductor layers being connected to the at least one gettering site via the connection portions, and annealing the substrate to getter the plurality of semiconductor layers.

Abstract: A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer. A well region is ion implanted in the monocrystalline silicon substrate. A gate electrode material is deposited overlying the monocrystalline silicon layer. The gate electrode material is photolithographically patterned and etched using a minimum lithography feature size to form a first gate electrode, a second gate electrode and a spacer having the minimum lithography feature size. The gate electrode material is then isotropically etched to reduce the width of the first gate electrode, the second gate electrode and the spacer.

Abstract: A method for manufacturing a field-effect transistor includes the steps of forming a source electrode and a drain electrode each containing hydrogen or deuterium; forming an oxide semiconductor layer in which the electrical resistance is decreased if hydrogen or deuterium is added; and, causing hydrogen or deuterium to diffuse from the source electrode and the drain electrode to the oxide semiconductor layer.

Abstract: A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

Abstract: The present invention is to provide a semiconductor device that achieves high mechanical strength without reducing the circuit scale and that can prevent the data from being forged and altered illegally while suppressing the cost. The present invention discloses a semiconductor device typified by an ID chip that is formed from a semiconductor thin film including a first region with high crystallinity and a second region with the crystallinity inferior to the first region. Specifically, a TFT (thin film transistor) of a circuit requiring high-speed operation is formed by using the first region and a memory element for an identifying ROM is formed by using the second region.

Abstract: To provide a method for manufacturing a semiconductor device including a transfer step that is capable of controlling the adhesiveness of a substrate and an element-formed layer in the case of separating the element-formed layer including a semiconductor element or an integrated circuit formed over the substrate from the substrate and bonding it to another substrate. An adhesive agent made of a good adhesiveness material is formed between the semiconductor element or the integrated circuit comprising plural semiconductor elements formed over the substrate (a first substrate) and the substrate, and thus it is possible to prevent a semiconductor element from peeling off a substrate in manufacturing the semiconductor element, and further, to make it easier to separate the semiconductor element from the substrate by removing the adhesive agent after forming the semiconductor element.

Abstract: A method of manufacturing the pixel structure is provided. The method includes forming a gate, a scan line connected to the gate, and at least one auxiliary pattern on a substrate. An insulating layer, a semiconductor layer, an ohmic contact layer, and a photoresist layer are formed in sequence. Afterwards, a single exposure and development is performed on the photoresist layer to form a first portion and a second portion. Next, the ohmic contact layer and the semiconductor layer which are not covered by the photoresist layer are removed to expose a part of the insulating layer. Next, the second portion of the photoresist layer is removed. Subsequently, a part of the thickness of the semiconductor layer not covered by the first portion is removed and the exposed insulating layer is removed, so as to faun a channel layer and an insulating layer.

Abstract: The present invention relates to a method for fabricating thin film transistors (TFTs), which includes the following steps: forming a semi-conductive layer on a substrate; forming a patterned photoresist layer with a first thickness and a second thickness on the semi-conductive layer; pattering the semi-conductive layer by using the patterned photoresist layer as a mask to form a patterned semi-conductive layer; removing the second thickness of the patterned photoresist layer; performing a first ion doping process on the patterned semi-conductive layer by using the first thickness of the patterned photoresist layer as a mask; removing the first thickness of the patterned photoresist layer; and forming a dielectric layer and a gate on the patterned semi-conductive layer. The present invention also discloses a method for fabricating an array substrate including aforementioned TFTs.

Abstract: A crystallization method of an amorphous semiconductor layer includes providing an amorphous semiconductor layer having a first thickness, crystallizing the amorphous semiconductor layer in a first direction, partially reducing the crystallized semiconductor layer to a second thickness less than the first thickness and crystallizing the etched semiconductor layer in a second direction.

Abstract: In crystallization of a silicon film by annealing with a linear-shaped laser beam having an ununiform width of the short axis of the beam, the profile (intensity distribution) of the laser beam is evaluated, and the result is fed back to an oscillating condition of the laser beam or an optical condition which projects this onto the silicon film, whereby a display device comprising a high-quality crystalline silicon film is produced.

Abstract: A thin film transistor array panel includes a gate line formed on a substrate, an interlayer insulating film formed on the gate line and having an opening, a gate insulator formed in the opening, a data line formed on the interlayer insulating film and including a first conductive layer made of a transparent conductive oxide and a second conductive layer made of a metal, a source electrode connected to the data line and made of a transparent conductive oxide, a drain electrode facing the source electrode and made of a transparent conductive oxide, a pixel electrode connected to the drain electrode, and an organic semiconductor contacting the source electrode and the drain electrode.

Abstract: The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region, a bridge type channel structure formed in the active region, and a coaxial type gate electrode surrounding the bridge type channel structure of a gate region. The bridge type channel structure is separated from the semiconductor substrate thereunder by a predetermined distance in a vertical direction.

Abstract: A thin film transistor includes: a silicon nanowire on a substrate, the silicon nanowire having a central portion and both side portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode spaced apart from the source electrode on the both side portions, the source electrode and the drain electrode electrically connected to the silicon nanowire, respectively.

Abstract: A semiconductor device having high electrical characteristics is manufactured at low cost and with high throughput. A semiconductor film is crystallized or activated by being irradiated with a laser beam emitted from one fiber laser. Alternatively, laser beams are emitted from a plurality of fiber lasers and coupled by a coupler to be one laser beam, and then a semiconductor film is irradiated with the coupled laser beam so as to be crystallized or activated.

Abstract: A metallic element is effectively removed from a semiconductor film crystallized by using the metallic element. The concentration distribution of phosphorous or antimony in the depth direction of at least one of a source and a drain of a TFT semiconductor film has: a region in which the concentration is 1×1020 atoms/cm3 or less is 5 nm or greater in thickness, and 5×1019 atoms/cm3 or greater in the maximum value. By creating this concentration distribution, and by thermal annealing at about between 500 and 650° C., the metallic element within a channel forming region diffuses to the source or the drain, and at the same time as gettering is accomplished, the region in which the concentration is 1×1020 atoms/cm3 or less is made into a nucleus and the source region/drain region is recrystallized.

Abstract: An electronic device, including a substrate, a plurality of first semiconductor islands on the substrate, a plurality of second semiconductor islands on the substrate, a first dielectric film on the first subset of the semiconductor islands, second dielectric film on the second semiconductor islands, and a metal layer in electrical contact with the first and second semiconductor islands. The first semiconductor islands and the first dielectric film contain a first diffusible dopant, and the second semiconductor islands and the second dielectric layer film contain a second diffusible dopant different from the first diffusible dopant. The present electronic device can be manufactured using printing technologies, thereby enabling high-throughput, low-cost manufacturing of electrical circuits on a wide variety of substrates.

Abstract: In a thin film transistor (TFT) structure, formation of a spacer layer is used for isolating the NI junction from an insulating layer comprising a nitride, so as to decrease the amount of current leakage and improve the electric characteristics of TFT. In a back-channel etching (BCE) type TFT device, the spacer layer (comprising an oxide layer) is substantially formed at the sidewalls of the channel regions to isolate the insulating layer (comprising silicon nitride) from the NI junctions. In an etch-stop TFT device, the spacer layer (comprising an oxide layer) is substantially formed at the sidewalls of the etch-stop layer to isolate the insulating layer (i.e. etch-stop layer) from the NI junctions.

Abstract: In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed.

Abstract: Thin film transistors (TFT) and methods for making same. The TFTs generally comprise: (a) a semiconductor layer comprising source and drain terminals and a channel region therebetween; (b) a gate electrode comprising a gate and a gate dielectric layer between the gate and the channel region; (c) a first dielectric layer adjacent to the gate electrode and in contact with the source and drain terminals, the first dielectric layer comprising a material which comprises a dopant therein; and (d) an electrically functional source/drain extensions in the channel region, adjacent to the source and drain terminals, comprising a material which comprises the same dopant as the first dielectric layer.

Abstract: An array substrate for a liquid crystal display device includes a gate and a data lines on a substrate intersecting each other, the data line includes a first layer formed of a transparent conductive material and a second layer under the first layer; a thin film transistor including a gate electrode connected to the gate line formed at respective intersection of the gate and data lines, an insulating layer on the gate electrode, an active layer on the insulating layer disposed within the gate electrode, an etch stopper on the active layer, an ohmic contact layer on the etch stopper, a source electrode on the ohmic contact layer and connected to the first layer, a drain electrode spaced apart from the source electrode; a pixel electrode connected to the drain electrode, wherein the source, drain and pixel electrodes are formed of the same layer and material as the first layer.

Abstract: A manufacturing method of a thin film transistor array substrate incorporating the manufacture of a photo-sensor is provided. In the manufacturing method, a photo-sensing dielectric layer is formed between a transparent conductive layer and a metal electrode for detecting ambient light. Since the transparent conductive layer is adopted as an electrode, the ambient light can pass through the transparent conductive layer and get incident light into the photo-sensing dielectric layer. Therefore, the sensing area of the photo-sensor can be enlarged and the photo-sensing efficiency is improved. In addition, the other side of the photo sensitive dielectric layer may be a metal electrode. The metal electrode can block the backlight from getting incident into the photo-sensing dielectric layer and thus reduce the background noise. A manufacturing method of a liquid crystal display panel adopting the aforementioned thin film transistor array substrate is also provided.

Abstract: A fabricating method of an array substrate for a liquid crystal display device including forming a polycrystalline silicon film on a substrate having a display region and a peripheral region, the polycrystalline silicon film having grains of square shape, forming a first active layer in the display region and a second active layer in the peripheral region by etching the polycrystalline silicon film, forming a first gate electrode over the first active layer, a second gate electrode over the second active layer and a gate line connected to the first gate electrode, and forming first source and drain electrodes connected to the first active layer, second source and drain electrodes connected to the second active layer and data line connected to the first source electrode. Further, the second gate electrode overlaps the first active layer to form a first channel region, and the first channel region is formed inside one of the grains.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method can form a structure of a thin film transistor (TFT) having a symmetric lightly doped region, and thus provide superior operation reliability and electrical performance. In addition, the manufacturing method forms gate patterns of different TFTs by the same mask process and thereby avoids the misalignment of masks so as to improve the processing yield and reduce the manufacturing cost.

Abstract: The present invention relates to a thin film transistor for preventing short of circuit by step and a method for fabricating the thin film transistor and provides a thin film transistor including a buffer layer formed on glass substrate; an activation layer formed on the buffer layer; and a gate insulation layer formed on the buffer layer including the activation layer, with the buffer layer having a step formed between a lower part of the activation layer and a part except the lower part of the activation layer.

Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film.

Abstract: An exemplary method for fabricating an LTPS-TFT substrate is as follows. In step S1, a p-Si pattern including a source electrode contact region and a drain electrode contact region of a first type TFT, a source electrode contact region and a drain electrode contact region of a second type TFT is formed. In step S2, the source electrode contact region and the drain electrode contact region of the first type TFT are heavily doped with a first dopant. In step S3, gate electrodes of the first and the second type TFT are formed. In step S4, the source electrode contact regions and drain electrode contact regions of the first and second type TFTs are heavily doped with a second dopant. The first dopant and the second dopant are compensative, and the number ratio of the first dopant to the second dopant is approximately 2 to 1.

Abstract: A dry etching method for forming tungsten wiring having a tapered shape and having a large specific selectivity with respect to a base film is provided. If the bias power density is suitably regulated, and if desired portions of a tungsten thin film are removed using an etching gas having fluorine as its main constituent, then the tungsten wiring having a desired taper angle can be formed.

Abstract: A thin film transistor includes a multi-coaxial silicon nanowire unit including a plurality of coaxial silicon nanowires on a substrate, the multi-coaxial silicon nanowire unit including a central portion and end portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode on the respective end portions, respectively, so as to electrically connect to the multi-coaxial silicon nanowire unit.

Abstract: A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P? polysilicon layer overlying the co-planar surface, an oxide-nitride-oxide (ONO) layer overlying the P? polysilicon layer; and at least one control gate overlying the ONO layer. In one embodiment, the control gate is made of a metal layer. In another embodiment, the control gate is made of a P+ polysilicon layer.

Abstract: An object of the present invention is to provide an EL display device having a high operation performance and reliability. The switching TFT 201 formed within a pixel has a multi-gate structure, which is a structure which imposes an importance on reduction of OFF current value. Further, the current control TFT 202 has a channel width wider than that of the switching TFT to make a structure appropriate for flowing electric current. Morever, the LDD region 33 of the current control TFT 202 is formed so as to overlap a portion of the gate electrode 35 to make a structure which imposes importance on prevention of hot carrier injection and reduction of OFF current value.

Abstract: An organic EL device comprising a semiconductor element A having a source electrode, a drain electrode, and a gate electrode, a semiconductor element B having a source electrode, a drain electrode, and a gate electrode connected to the source electrode or the drain electrode of the semiconductor element A, and an organic EL element having a pixel electrode connected to the drain electrode of the semiconductor element B, in which the source electrode and the drain electrode of the semiconductor element A and the gate electrode of the semiconductor element B are set on the same plane.

Abstract: In a crystallization process of an amorphous semiconductor film, a first polycrystalline semiconductor film, in which amorphous regions are dotted within the continuous crystal region, is obtained by performing heat treatment after introducing a metallic element which promotes crystallization on the amorphous semiconductor film. At this point, the amorphous regions are kept within a predetermined range. A laser beam having a wave length region, which can give more energy to the amorphous region than to the crystal region, is irradiated to the first polycrystalline semiconductor film, it is possible to crystallize the amorphous region without destroying the crystal region. If a TFT is manufactured based on a second polycrystalline semiconductor film, which is obtained through the above-mentioned crystallization processes, the TFT with high electric characteristics and less fluctuation can be obtained.

Abstract: A method for fabricating polysilicon film is disclosed. First, a first substrate is provided, wherein a plurality of sunken patterns has been formed on the front surface of the first substrate. Then, a second substrate is provided and an amorphous polysilicon film is formed on the second substrate. Next, the amorphous polysilicon film formed on the second substrate is in contact with the front surface of the first substrate. The amorphous polysilicon film is transferred into a polysilicon film by performing an annealing process. Then, the first substrate and the second substrate are separated from each other. This method reduces the cost and the time for fabricating polysilicon film.

Abstract: A method of manufacturing a thin film transistor capable of inhibiting the characteristics variation of the thin film transistor without deteriorating the characteristics thereof is provided. A crystalline silicon film is formed by indirect heat treatment through a photothermal conversion layer and a buffer layer. By patterning the buffer layer and an insulating film, a channel protective film is selectively formed in a region corresponding to a channel region on the crystalline silicon film. Further, when an n+ silicon film and a metal layer are selectively removed, the channel protective film functions as an etching stopper. When the crystalline silicon film is formed, heat is uniformly supplied. Further, in etching, the channel region of the crystalline silicon film is protected.

Abstract: A method of manufacturing a thin-film transistor or like structure provides conductive “tails” below an overhang region formed by a top gate structure. The tails increase in thickness as they extend outward from a point under the overhang to the source and drain contacts. The tails provide a low resistance conduction path between the source and drain regions and the channel, with low parasitic capacitance. The thickness profile of the tails is controlled by the deposition of material over and on the lateral side surfaces of the gate structure.

Abstract: A method of manufacturing a thin-film transistor or like structure provides conductive “tails” below an overhang region formed by a top gate structure. The tails increase in thickness as they extend outward from a point under the overhang to the source and drain contacts. The tails provide a low resistance conduction path between the source and drain regions and the channel, with low parasitic capacitance. The thickness profile of the tails is controlled by the deposition of material over and on the lateral side surfaces of the gate structure.

Abstract: A semiconductor device having a crystalline semiconductor film with production of a cavity suppressed and a manufacturing method thereof A manufacturing method of a semiconductor device according to the invention comprises the steps of forming an amorphous silicon film on a substrate having an insulating surface, adding a metal element such as Ni for promoting crystallization to the amorphous silicon film, applying heat treatment to crystallize the amorphous silicon film, so that a crystalline silicon film is formed on the substrate, removing a silicon oxide film formed on the surface of the crystalline silicon film due to the heat treatment by a solution containing organic solvent and fluoride, and irradiating laser light or strong light to the crystalline silicon film.