Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.

Abstract: To provide a manufacturing method for a field-effect transistor, such as a thin-film transistor, enabling reductions in the number patterning steps and the number of photomasks and improvements in the throughput and the yield. In the method, an oxide film is formed by processing the surface of a crystalline semiconductor with ozone water or hydrogen peroxide water. Using the oxide film thus formed as an etch stop, a gate electrode, a source electrode, and a drain electrode of the field-effect transistor are simultaneously formed from a same starting film in one patterning step by use of one photomask. After forming the gate electrode, the source electrode, and the drain electrode, heating is performed thereon at 800° C. or higher for a predetermined time. Thereby, the contact resistances between the source electrode and the crystalline semiconductor and between the drain electrode and the crystalline semiconductor are reduced, whereby improving the electrical conductivity.

Abstract: A semiconductor device has a planarizing layer that is made of an inorganic film, and has a recessed portion formed in a region thereof in which a conductive film is disposed. A first contact hole penetrating through at least an interlayer insulating film is formed on a first wiring layer, while a second contact hole penetrating through at least the interlayer insulating film is formed on the conductive film so as to run through the inside of the recessed portion.

Abstract: A thin film transistor array panel includes a gate line formed on a substrate, an interlayer insulating film formed on the gate line and having an opening, a gate insulator formed in the opening, a data line formed on the interlayer insulating film and including a first conductive layer made of a transparent conductive oxide and a second conductive layer made of a metal, a source electrode connected to the data line and made of a transparent conductive oxide, a drain electrode facing the source electrode and made of a transparent conductive oxide, a pixel electrode connected to the drain electrode, and an organic semiconductor contacting the source electrode and the drain electrode.

Abstract: Provided is a method of manufacturing an oxide semiconductor thin film transistor using a transparent oxide semiconductor as a material for a channel. The method of manufacturing the oxide semiconductor thin film transistor includes forming a passivation layer on a channel layer and performing an annealing process for one hour or more at a temperature of about 100° C. or above.

Abstract: An oxide or nitride semiconductor layer is formed over a substrate. A first conductive layer including a first element and a second element, and a second conductive layer including the second element are formed over the semiconductor layer. The first element is oxidized or nitrogenized near an interface region between the first conductive layer and the oxide or nitride semiconductor layer by heat treatment or laser irradiation. The Gibbs free energy of oxide formation of the first element is lower than those of the second element or any element in the oxide or nitride semiconductor layer.

Abstract: A thin film transistor includes a multi-coaxial silicon nanowire unit including a plurality of coaxial silicon nanowires on a substrate, the multi-coaxial silicon nanowire unit including a central portion and end portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode on the respective end portions, respectively, so as to electrically connect to the multi-coaxial silicon nanowire unit.

Abstract: A thin film transistor substrate includes a substrate, a gate electrode on the substrate, an active layer on or below the gate electrode (the active layer at least partially overlapping the gate electrode) including a first active region and a second active region, the first active region and the second active region facing each other and extending beyond the gate electrode, a source electrode electrically connected to the first active region and a drain electrode electrically connected to the second active region, wherein the active layer includes a recess region which is at least partially recessed from a surface of the active layer facing the gate electrode, and the recess region includes a portion extending between the first active region and the second active region.

Abstract: The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: an active fin region which is arranged on an insulating layer; a threshold voltage adjusting layer arranged on top of the active fin region, which threshold voltage adjusting layer is used to adjust the threshold voltage of the semiconductor device; a gate stack which is arranged on the threshold voltage adjusting layer, on the sidewalls of the active fin region and on the insulating layer, and comprises a gate dielectric and a gate electrode formed on the gate dielectric; and a source region and a drain region formed in the active fin region on both sides of the gate stack respectively. The semiconductor device according to the invention comprises the threshold voltage adjusting layer which may adjust the threshold voltage of the semiconductor device.

Abstract: A method of crystallizing a silicon layer and a method of manufacturing a TFT, the method of crystallizing a silicon layer including forming a catalyst metal layer on a substrate; forming a catalyst metal capping pattern on the catalyst metal layer; forming a second amorphous silicon layer on the catalyst metal capping pattern; and heat-treating the second amorphous silicon layer to form a polycrystalline silicon layer.

Abstract: Provided are a crystallization apparatus and method, which prevent cracks from being generated, a method of manufacturing a thin film transistor (TFT), and a method of manufacturing an organic light emitting display apparatus. The crystallization apparatus includes a chamber for receiving a substrate, a first flash lamp and a second flash lamp, which are disposed facing each other within the chamber, wherein amorphous silicon layers are disposed on a first surface of the substrate facing the first flash lamp and a second surface of the substrate facing the second flash lamp, respectively.

Abstract: A method of manufacturing a TFT, including forming a buffer layer, an amorphous silicon layer, an insulating layer, and a first conductive layer on a substrate, forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer, forming a semiconductor layer, a gate insulating layer, and a gate electrode that have a predetermined shape by simultaneously patterning the polycrystalline silicon layer, the insulating layer, and the first conductive layer, wherein the polycrystalline silicon layer is further etched to produce an undercut recessed a distance compared to sidewalls of the insulating layer and the first conductive layer, forming source and drain regions within the semiconductor layer by doping corresponding portions of the semiconductor layer, forming an interlayer insulating layer on the gate electrode, the interlayer insulating layer covering the gate insulating layer and forming source and drain electrodes that are electrically connected to source and drain regions respectively.

Abstract: There is provided a thin film transistor including an active layer on a substrate (the active layer including polysilicon and a metal catalyst dispersed in the polysilicon, a source area, a drain area, and a channel area), a gate electrode disposed on the channel area of the active layer, a source electrode electrically connected to the source area, and a drain electrode electrically connected to the drain area, wherein the gate electrode, the source area, and the drain area of the active layer include metal ions, the source area and the drain area are separate from each other, and the channel is disposed between the source area and the drain area.

Abstract: A method of manufacturing a display device includes forming a buffer layer on a top surface of a substrate, forming an amorphous silicon layer on a top surface of the buffer layer, and forming a polysilicon layer by irradiating the amorphous silicon layer with a laser beam. A plurality of first protrusions are formed on the top surface of the polysilicon layer, and a plurality of second protrusions are formed on a surface of the buffer layer by transferring the shape of the polysilicon layer to the buffer layer. A gate insulator on the buffer layer is then formed in the shape of bumps of the second protrusions.

Abstract: In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.

Abstract: A thin film transistor device includes a first conductivity type thin film transistor and a second conductivity type thin film transistor. The first conductivity type thin film transistor includes a first patterned doped layer, a first gate electrode, a first source electrode, a first drain electrode and a first semiconductor pattern. The second conductivity type thin film transistor includes a second patterned doped layer, a second gate electrode, a second source electrode, a second drain electrode and a second semiconductor pattern. The first semiconductor pattern and the second semiconductor pattern form a patterned semiconductor layer. The first patterned doped layer is disposed under the first semiconductor pattern, and the second patterned doped layer is disposed on the second semiconductor pattern.

Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.

Abstract: A production method of a semiconductor element having a channel includes forming a resist pattern film on a thin film formed on a substrate, and pattering the thin film by etching. The production method also includes forming a second resist pattern film by applying a fluid resist material inside a channel groove after channel etching or inside a resist groove formed above a channel region before channel etching. The production method may also include forming a gate electrode, a gate insulating film, a semiconductor film, and a conductive film on an insulating substrate. The method may include applying the fluid resist material inside the channel groove, thereby forming the second resist pattern film, and patterning the semiconductor film using at least the second resist pattern film.

Abstract: A flat panel display device is disclosed that may include a light-emitting layer portion including a first electrode, a second electrode, and an organic light-emitting layer between the first and second electrodes; at least two thin film transistors for controlling the light-emitting layer portion; a scanning signal line for supplying a scanning signal to the thin film transistor; a data signal line for supplying a data signal to the thin film transistor; a light emitting region having a common power supply line for supplying current to the light-emitting layer portion; and a peripheral common power supply line having at least one curved portion and connected to the common power supply line on a panel of a non-light emitting region except the light emitting region, wherein the common power supply line has a reduced wiring width while maintaining a constant wiring resistance to thereby reduce the total size of the display panel.

Abstract: A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device including the TFT. The TFT includes a substrate having a pixel region and a non-pixel region, a semiconductor layer, a gate insulating layer, a gate electrode, and source and drain electrodes disposed on the pixel region, at least one gettering site disposed on the non-pixel region, and at least one connection portion to connect the at least one gettering site and the semiconductor layer. The method of fabricating the TFT includes patterning a polycrystalline silicon (poly-Si) layer to form a plurality of semiconductor layers, connection portions, and at least one gettering site, the semiconductor layers being connected to the at least one gettering site via the connection portions, and annealing the substrate to getter the plurality of semiconductor layers.

Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time.

Abstract: In an organic light-emitting display having superior image quality and device reliability, and a related method of manufacturing the organic light-emitting display, the organic light-emitting display comprises: a gate electrode formed on a substrate; an interlayer insulating film formed on the substrate so as to cover the gate electrode; and a transparent electrode formed on the interlayer insulating film. The interlayer insulating film comprises multiple layers having different refractive indices.

Abstract: A thin film transistor includes a multi-coaxial silicon nanowire unit including a plurality of coaxial silicon nanowires on a substrate, the multi-coaxial silicon nanowire unit including a central portion and end portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode on the respective end portions, respectively, so as to electrically connect to the multi-coaxial silicon nanowire unit.

Abstract: A manufacturing method for a low temperature polysilicon (LTPS) thin film transistor (TFT) array substrate, comprising: forming a polysilicon layer on a substrate; forming a gate insulating layer on the polysilicon layer; forming a gate metal layer on the gate insulating layer; and patterning the gate metal layer, the gate insulating layer and the polysilicon layer by using a half tone mask (HTM) or a gray tone mask (GTM) so as to obtain a gate electrode and a polysilicon semiconductor pattern in a single mask process, a central part of the polysilicon semiconductor pattern is covered by the gate electrode, and the polysilicon semiconductor pattern has two parts, which are not covered by the gate electrode at two sides of the gate electrode, for forming a source region and a drain region.

Abstract: A transistor is formed having a thin film metal channel region. The transistor may be formed at the surface of a semiconductor substrate, an insulating substrate, or between dielectric layers above a substrate. A plurality of transistors each having a thin film metal channel region may be formed. Multiple arrays of such transistors can be vertically stacked in a same device.

Abstract: A manufacturing method of a flat panel display according to an exemplary embodiment of the present invention includes: coating a first adhering member on a first supporting plate; disposing a first substrate on the first adhering member; using ultrasonic waves to adhere the first supporting plate and the first substrate; and forming a gate line, a data line, a thin film transistor connected to the gate line and the data line, and a pixel electrode connected to the thin film transistor on the first substrate. According to the manufacturing method of the flat panel display according to an exemplary embodiment of the present invention, the first adhering member made of the plurality of adhering particles is melted by using the ultrasonic waves without an additional adhering film to adhere the flexible first substrate and the first supporting plate, thereby reducing the overall manufacturing cost.

Abstract: A display device according to the present invention includes a barrier layer formed over the transistor and a planarization layer formed over the barrier layer. The planarization layer has an opening and an edge portion of the planarization layer formed at the opening of the planarization layer is rounded. Further, a resin film is formed over the planarization layer and in the opening of the planarization layer, and the resin film also has an opening and an edge portion of the resin film formed at the opening of the resin film is rounded. A light emitting member is formed over the resin film.

Abstract: A manufacturing method of a thin film transistor is provided. An insulating pattern layer having at least one protrusion is formed on a substrate. At least one spacer and a plurality of amorphous semiconductor patterns separated from each other are formed on the insulating pattern layer. The spacer is formed at one side of the protrusion and connected between the amorphous semiconductor patterns. The spacer and the amorphous semiconductor patterns are crystallized. The protrusion and the insulating pattern layer below the spacer are removed so that a beam structure having a plurality of corners is formed and suspended over the substrate. A carrier tunneling layer, a carrier trapping layer and a carrier blocking layer are sequentially formed to compliantly wrap the corners of the beam structure. Hereafter, a gate is formed on the substrate to cover the beam structure and wrap the carrier blocking layer.

Abstract: In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.

Abstract: To realize a semiconductor device including a capacitor element capable of obtaining a sufficient capacitor without reducing an opening ratio, in which a pixel electrode is flattened in order to control a defect in orientation of liquid crystal. A semiconductor device of the present invention includes a light-shielding film formed on the thin film transistor, a capacitor insulating film formed on the light-shielding film, a conductive layer formed on the capacitor insulating film, and a pixel electrode that is formed so as to be electrically connected to the conductive layer, in which a storage capacitor element comprises the light-shielding film, the capacitor insulating film, and the conductive layer, whereby an area of a region serving as the capacitor element can be increased.

Abstract: A semiconductor device 19-1 includes a source electrode 3s and a drain electrode 3d disposed on a substrate 1, an insulating partition wall 5, which has a first opening 5a reaching end portions of the source electrode 3s and the drain electrode 3d and between these electrodes 3s-3d and which is disposed on the substrate 1, a channel portion semiconductor layer 7a, which is composed of a semiconductor layer 7 formed from above the partition wall 5 and which is disposed on the bottom portion of the first opening 5a while being separated from the semiconductor 7 on the partition wall 5, a gate insulating film 9 formed all over the surface from above the semiconductor layer 7 including the channel portion semiconductor layer 7a, and a gate electrode 11a disposed on the gate insulating film 9 while overlapping the channel portion semiconductor layer 7a.

Abstract: A wiring line is electrically connected in parallel to an auxiliary wiring line via a plurality of contact holes. The contact holes are formed through an insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively without increasing the number of manufacturing steps.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a component having dielectric sub-layers are described.

Abstract: A method for producing a High Temperature Thin Film Layer On Glass (HTTFLOG) of silicon, which is a precursor component of thin film transistors (TFTs). The invention described here is a superior method of fabricating HTTFLOG precursor structures or components for liquid crystal displays (LCDs) with quicker production time and lower cost of manufacture while enabling a groundbreaking increase in small and large screen resolution. This invention is a new sub-assembly intended for original equipment manufacturer (OEM) consumption and inclusion in display products.

Abstract: A method of forming a polycrystalline layer includes forming a buffer layer on a substrate; treating the buffer layer with hydrogen plasma; forming an amorphous silicon layer on the buffer layer; forming a metallic catalyst layer for crystallizing the amorphous silicon layer on the amorphous silicon layer; and heat treating the amorphous silicon layer to form a polycrystalline silicon layer.

Abstract: When a transistor including a conductive layer having a three-layer structure is manufactured, three-stage etching is performed. In the first etching process, an etching method in which the etching rates for the second film and the third film are high is employed, and the first etching process is performed until the first film is at least exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. In the third etching process, an etching method in which the etching rates for the first to the third films are higher than those in the second etching process is preferably employed.

Abstract: A method of crystallizing a silicon layer and a method of manufacturing a TFT, the method of crystallizing a silicon layer including forming a catalyst metal layer on a substrate; forming a catalyst metal capping pattern on the catalyst metal layer; forming a second amorphous silicon layer on the catalyst metal capping pattern; and heat-treating the second amorphous silicon layer to form a polycrystalline silicon layer.

Abstract: In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.

Abstract: A method of crystallizing a silicon layer and a method of manufacturing a thin film transistor using the same, the method of crystallizing the silicon layer including forming an amorphous silicon layer on a substrate; performing a hydrophobicity treatment on a surface of the amorphous silicon layer so as to obtain a hydrophobic surface thereon; forming a metallic catalyst on the amorphous silicon layer that has been subjected to the hydrophobicity treatment; and heat-treating the amorphous silicon layer including the metallic catalyst thereon to crystallize the amorphous silicon layer into a polycrystalline silicon layer.

Abstract: The invention provides a display device having a thin film transistor and a storage capacitor storing a display signal applied to a pixel electrode through this thin film transistor on a substrate, where dielectric strength between electrodes forming the storage capacitor is enhanced for increasing the yield. In the storage capacitor, a lower storage capacitor electrode, a thin lower storage capacitor film, a polysilicon layer, an upper storage capacitor film and an upper storage capacitor electrode are layered. The polysilicon layer is formed by crystallization by laser annealing. The polysilicon layer of the storage capacitor is microcrystalline and thus the flatness of its surface is enhanced. The pattern of the polysilicon layer (storage capacitor electrode) is formed larger than the bottom portion of an opening, and the edge of its peripheral portion is located on a buffer film on the slant portion of the opening or on the buffer film on the outside of the opening.

Abstract: Provided is a method of fabricating a thin film transistor including source and drain electrodes, a novel channel layer, a gate insulating layer, and a gate electrode, which are formed on a substrate. The method includes the steps of forming the channel layer using an oxide semiconductor doped with boron; and patterning the channel layer. The channel layer formed is an oxide semiconductor thin film doped with boron. The electrical characteristics and high temperature stability of the thin film transistor are improved remarkably.

Abstract: An oxide or nitride semiconductor layer is formed over a substrate. A first conductive layer including a first element and a second element, and a second conductive layer including the second element are formed over the semiconductor layer. The first element is oxidized or nitrogenized near an interface region between the first conductive layer and the oxide or nitride semiconductor layer by heat treatment or laser irradiation. The Gibbs free energy of oxide formation of the first element is lower than those of the second element or any element in the oxide or nitride semiconductor layer.

Abstract: A semiconductor device includes at least one thin film transistor including a semiconductor layer that has a crystalline region including a channel region, a source region and a drain region, a gate insulating film disposed at least on the channel region, the source region and the drain region of the semiconductor layer, and a gate electrode arranged so as to oppose the channel region via the gate insulating film. At least a portion of the semiconductor layer includes a catalyst element capable of promoting crystallization, and the semiconductor layer further includes a gettering region that includes the catalyst element at a higher concentration than in the channel region or the source region and the drain region. The thickness of the gate insulating film on the gettering region is smaller than that on the source region and the drain region, or the gate insulating film is not disposed on the gettering region.

Abstract: The present invention relates to the field of thin film solar cells and particularly to an apparatus and method for manufacturing thin film solar cells. At least one material is deposited onto a substrate, whereby the deposited material is heated by means of heating means on a limited area of the deposited material. The substrate and the heating means are continuously moved in relation to each other until a predetermined area of the deposited material is heated, whereby the heated material is cooled in a controlled way, thus, obtaining a desired crystalline structure of the deposited material.

Abstract: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.

Abstract: To provide a thin film transistor having a high field effect mobility and a small variation in characteristics thereof, a second amorphous semiconductor layer patterned in a predetermined shape is formed on a first crystalline semiconductor layer 17 for constituting source and drain regions. By irradiating an irradiated region 21 of continuous wave laser beam while scanning along a channel length direction, the second amorphous semiconductor layer is crystallized to form a second crystalline semiconductor layer 22. The first crystalline semiconductor layer 17 is crystallized by selectively adding nickel and therefore, an orientation rate of {111} is increased.

Abstract: Systems and methods for forming a time-averaged line image having a relatively high amount of intensity uniformity along its length is disclosed. The method includes forming at an image plane a line image having a first amount of intensity non-uniformity in a long-axis direction and forming a secondary image that at least partially overlaps the primary image. The method also includes scanning the secondary image over at least a portion of the primary image and in the long-axis direction according to a scan profile to form a time-average modified line image having a second amount of intensity non-uniformity in the long-axis direction that is less than the first amount. For laser annealing a semiconductor wafer, the amount of line-image overlap for adjacent scans of a wafer scan path is substantially reduced, thereby increasing wafer throughput.

Abstract: A display substrate having a low-resistance metallic layer and a method of manufacturing the display substrate. The gate conductors are extended in a first direction. The source conductors are extended in a second direction crossing the first direction including a lower layer of molybdenum or a molybdenum alloy, and an upper layer of aluminum or an aluminum alloy. The pixel areas are defined by the gate conductors and the source conductors. A switching element is formed in each of the pixel areas and includes a gate electrode extended from the gate conductor and a source electrode extended from the source conductor. The pixel electrode includes a transparent conductive material, and is electrically connected to a drain electrode of the switching element.

Abstract: A thin film transistor which has improved characteristics, a method of fabricating the same, and an organic light emitting diode (OLED) display device having the same. The thin film transistor includes a substrate, a semiconductor layer disposed on the substrate and including a channel region, and source and drain regions, the channel region being doped with impurities, a thermal oxide layer disposed on the semiconductor layer, a silicon nitride layer disposed on the thermal oxide layer, a gate electrode disposed on the silicon nitride layer and corresponding to a predetermined region of the semiconductor layer, an interlayer insulating layer disposed on the entire surface of the substrate, and source and drain electrodes electrically connected with the semiconductor layer.

Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.