Lateral Single Gate Single Channel Transistor With Noninverted Structure, I.e., Channel Layer Is Formed Before Gate (epo) Patents (Class 257/E21.413)
  • Patent number: 7195949
    Abstract: A method of making a current type active matrix OLED device, includes providing a semiconductor layer, a conductive layer, and an insulator layer therebetween over a substrate, providing an organic light emitting diode over either the semiconductor layer or over the conductive layer for each pixel, and forming a first transistor having a channel region formed in the semiconductor layer and a gate formed in the conductive layer for each pixel for receiving a first current data signal for adjusting the emission brightness in its corresponding pixel. The method also includes forming a second transistor for each pixel for regulating current through the organic light emitting diode in response to the first current wherein each second transistor has a gate formed in the conductive layer and a channel region formed in the semiconductor layer, and annealing particular regions of the semiconductor layer by using a pulsed laser.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: March 27, 2007
    Assignee: Eastman Kodak Company
    Inventor: Dustin L. Winters
  • Patent number: 7192815
    Abstract: A method of manufacturing a thin film transistor is described. A polysilicon island is formed over a substrate. A gate insulating layer is formed over the substrate to cover the polysilicin island. A gate is formed on the gate insulating layer above the polysilicon island. A passivation layer is formed over the substrate to cover the gate and the gate insulating layer. An ion implanting process is carried out to form a source/drain in the polysilicon island beside the gate, wherein a region between the source and the drain is a channel. After the first passivation layer is removed, a patterned dielectric layer is formed over the substrate, wherein the dielectric layer exposes a portion of the source/drain. A source/drain conductive layer is formed over the dielectric layer and is electrically connected to the source/drain.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: March 20, 2007
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventor: Chia-Nan Shen
  • Publication number: 20070015069
    Abstract: A crystallization mask for laser illumination for converting amorphous silicon into polysilicon is provided, which includes: a plurality of transmissive areas having a plurality of first slits for adjusting energy of the laser illumination passing through the mask; and an opaque area.
    Type: Application
    Filed: September 19, 2006
    Publication date: January 18, 2007
    Inventors: Su-Gyeong Lee, Hyun-Jae Kim, Myung-Koo Kang
  • Publication number: 20070015066
    Abstract: A mask for sequential lateral solidification (SLS) processes including at least one first window, one second window, one third window, and one fourth window is provided. Each window has a length extending longitude on the mask. The second window is aligned to the first window. The width of the first window is greater than that of the second window. The fourth window is aligned to the third window. The width of the third window is greater than that of the fourth window.
    Type: Application
    Filed: June 16, 2006
    Publication date: January 18, 2007
    Inventor: Ming-Wei Sun
  • Patent number: 7141514
    Abstract: A transistor gate selective re-oxidation process includes the steps of introducing into the vacuum chamber containing the semiconductor substrate a process gas that includes oxygen while maintaining a vacuum pressure in the chamber. An oxide insulating layer on the order of several Angstroms in thickness is formed by generating a plasma in a plasma generation region within the vacuum chamber during successive “on” times, and allowing ion energy of the plasma to decay during successive “off” intervals separating the successive “on” intervals, the “on” and “off” intervals defining a controllable duty cycle. During formation of the oxide insulating layer, the duty cycle is limited so as to limit formation of ion bombardment-induced defects in the insulating layer, while the vacuum pressure is limited so as to limit formation of contamination-induced defects in the insulating layer.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: November 28, 2006
    Assignee: Applied Materials, Inc.
    Inventor: Thai Cheng Chua
  • Patent number: 7118937
    Abstract: The present invention relates to a method of selectively depositing an organic semiconductor material and a method of manufacturing an organic semiconductor thin film transistor array. Since the thin film transistor array is formed by locally performing a plasma process on a substrate before depositing an organic semiconductor active layer on the substrate, the organic semiconductor material is deposited on only the organic semiconductor active layer having an island shape. Therefore, it is not necessary to use a shadow mask method or a photolithography method to manufacture an active matrix array. Accordingly, the present invention has advantages in that it is possible to obtain a high resolution thin film transistor array and to prevent characteristics of the thin film transistors in the array from being deteriorated.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: October 10, 2006
    Inventors: Jin Jang, Sung-Hwan Kim, Hye-Young Choi
  • Patent number: 7112476
    Abstract: A method for fabricating a poly-silicon liquid crystal display device includes forming a poly-silicon layer including a TFT region and a storage capacitor region on a substrate, wherein the capacitor region includes an impurity injection region having a N-type impurity injection region and a P-type impurity injection region; forming a gate electrode and a storage capacitor electrode on the poly-silicon layer; injecting an N-type impurity ion with a high doping density into the N-type impurity injection region and the TFT region; injecting a P-type impurity ion with a high doping density into the P-type impurity injection region; forming an insulating layer on the gate electrode and the storage electrode; and forming a pixel electrode on the insulating layer, wherein the pixel electrode is electrically connected to the impurity injection region in the storage capacitor region.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: September 26, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: San-Ho Kim, Hoon-Ju Chung
  • Patent number: 7109108
    Abstract: A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal, and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 ?m or less in width, and allowing the metal to react with silicon. A high performance TFT can be realized.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: September 19, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Hongyong Zhang, Satoshi Teramoto
  • Patent number: 7105855
    Abstract: A method of making a current type active matrix OLED device, includes providing a semiconductor layer, a conductive layer, and an insulator layer therebetween over a substrate, providing an organic light emitting diode over either the semiconductor layer or over the conductive layer for each pixel, and forming a first transistor having a channel region formed in the semiconductor layer and a gate formed in the conductive layer for each pixel for receiving a first current data signal for adjusting the emission brightness in its corresponding pixel. The method also includes forming a second transistor for each pixel for regulating current through the organic light emitting diode in response to the first current wherein each second transistor has a gate formed in the conductive layer and a channel region formed in the semiconductor layer, and annealing particular regions of the semiconductor layer by using a pulsed laser.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: September 12, 2006
    Assignee: Eastman Kodak Company
    Inventor: Dustin L. Winters
  • Patent number: 7056774
    Abstract: Disclosed is a method of manufacturing a semiconductor device. A plurality of device separation regions are formed in an SOI layer of an SOI substrate, a desired impurity is implanted into a body portion of an Si active layer region, and therereafter a gate electrode is formed with a gate insulation film therebetween. Thereafter, an impurity is implanted into the Si active layer region to form extension portions of source/drain portions, and then an impurity different in polarity from the impurity in the source/drain portions is halo-implanted to form a reverse-characteristic layer. In the halo implantation, the range of projection is set to reach the inside of a buried oxide film. With this configuration, in a fully depleted SOI-MOSFET or the like provided with a thin film SOI layer, it is made possible to simultaneously achieve an improvement of roll-off characteristic and a reduction in parasitic resistance and to secure a sufficient driving capability.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: June 6, 2006
    Assignee: Sony Corporation
    Inventor: Kazuhide Koyama
  • Patent number: 6800540
    Abstract: Disclosed is a method for crystallizing amorphous silicon, in which a substrate on which an amorphous silicon layer is formed is first prepared, and then a mask is disposed above the substrate. The mask is divided into first and second blocks, the first block having a plurality of first transmission slits and a plurality of interception portions formed between the first transmission slits, the second block having a plurality of second transmission slits alternately arranged with the first transmission slits and a plurality of third transmission slits formed corresponding to middle portions of the first transmission slits. Afterwards, first crystalline regions are formed on the amorphous silicon layer by irradiating a laser beam through the first transmission slits.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: October 5, 2004
    Assignee: LG.Philiips LCD Co., Ltd.
    Inventor: JaeSung You
  • Publication number: 20040113287
    Abstract: A semiconductor device manufacturing unit is provided, wherein a cathode and an anode can be placed in a simple structure; wherein excellent film deposition and film thickness distribution can be gained; and wherein no cooling devices are required to be provided.
    Type: Application
    Filed: November 10, 2003
    Publication date: June 17, 2004
    Inventors: Katsushi Kishimoto, Yusuke Fukuoka, Yasushi Fujioka, Hiroyuki Fukuda, Katsuhiko Nomoto