Lateral Single Gate Single Channel Transistor With Noninverted Structure, I.e., Channel Layer Is Formed Before Gate (epo) Patents (Class 257/E21.413)
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Publication number: 20080213954Abstract: A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a lower threshold voltage. In a further aspect, a control film that is removable in a later step is formed on the surface of the channel forming region of a TFT, and doping is performed from above the control film.Type: ApplicationFiled: March 3, 2008Publication date: September 4, 2008Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Naoto Kusumoto, Hideto Ohnuma, Koichiro Tanaka
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Patent number: 7416907Abstract: A low temperature process for fabricating a high-performance and reliable semiconductor device in high yield, comprising forming a silicon oxide film as a gate insulator by chemical vapor deposition using TEOS as a starting material under an oxygen, ozone, or a nitrogen oxide atmosphere on a semiconductor coating having provided on an insulator substrate; and irradiating a pulsed laser beam or an intense light thereto to remove clusters of such as carbon and hydrocarbon to thereby eliminate trap centers from the silicon oxide film. Also claimed is a process comprising implanting nitrogen ions into a silicon oxide film and annealing the film thereafter using an infrared light, to thereby obtain a silicon oxynitride film as a gate insulator having a densified film structure, a high dielectric constant, and an improved-withstand voltage.Type: GrantFiled: July 28, 2004Date of Patent: August 26, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hongyong Zhang
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Publication number: 20080197357Abstract: A display panel includes a semiconductor layer formed on a substrate, a first insulating layer formed on the semiconductor layer, a gate line including a gate electrode and formed on the first insulating layer, a second insulating layer formed on the gate line, and a data line including a source electrode and a drain electrode formed on the second insulating layer. The second insulating layer covered with the drain electrode and the data line may be thicker than the second insulating layer not covered with the drain electrode and the data line. The data conductors are disposed on a higher interlayer insulating layer than the others such that diffused or migrating aluminum material is placed on the lower interlayer insulating layer to be prevented from being connected to the data conductors.Type: ApplicationFiled: December 28, 2007Publication date: August 21, 2008Inventors: Gyung-Soon PARK, Chun-Gi YOU
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Publication number: 20080199992Abstract: The present invention discloses a method for manufacturing a display device comprising the steps of forming a first film pattern using a photosensitive material over a substrate, forming a second film pattern in such a way that the first film pattern is exposed by being irradiated with a laser beam, modifying a surface of the second film pattern into a droplet-shedding surface, forming a source electrode and a drain electrode by discharging a conductive material to an outer edge of the droplet-shedding surface by a droplet-discharging method, and forming a semiconductor region, a gate-insulating film, and a gate electrode over the source electrode and the drain electrode.Type: ApplicationFiled: April 9, 2008Publication date: August 21, 2008Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shinji MAEKAWA, Shunpei YAMAZAKI, Hironobu SHOJI
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Patent number: 7407838Abstract: A method of manufacturing a semiconductor characterized in that, in polycrystallizing an amorphous silicon thin film formed on a substrate through an annealing process, the amorphous silicon thin film has a plane area of 1000 ?m2 or less. A thin-film transistor characterized by comprising an active silicon film which is formed of a plurality of island-like regions arranged in parallel to each other, each of the island-like regions being formed of a polycrystal silicon thin film having a plane area of 1000 ?m2 or less. A method of manufacturing a thin-film transistor comprising the steps of: forming an amorphous silicon thin film on a substrate; processing the amorphous silicon thin film into a plurality of island-like regions each having a plane area of 1000 ?m2 or less; polycrystallizing an amorphous silicon thin film that forms the island-like regions through an annealing process; and forming a thin-film transistor having at least one of the plurality of island-like regions as an active silicon layer.Type: GrantFiled: July 22, 2003Date of Patent: August 5, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Isamu Kobori, Michio Arai
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Publication number: 20080179596Abstract: The present invention relates to a thin film transistor (TFT), an organic light emitting diode (OLED) display having the TFT, and a manufacturing method thereof. The manufacturing method includes: forming a pair of ohmic contacts including amorphous silicon that contains an impurity; forming a semiconductor member including amorphous silicon; crystallizing the ohmic contacts and the semiconductor member; forming an input electrode and an output electrode on the ohmic contacts; forming an insulating layer on the input electrode, the output electrode, and the blocking member; forming a control electrode on the insulating layer; forming a switching thin film transistor; and forming an organic light emitting diode connected to the output electrode.Type: ApplicationFiled: January 11, 2008Publication date: July 31, 2008Inventors: Kyu-Sik Cho, Jong-Moo Huh
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Publication number: 20080179598Abstract: A display device includes an insulating substrate, a switching TFT formed on the substrate that receives a data voltage and that includes a first semiconductor layer, a driving TFT formed on the substrate that includes a control terminal connected to an output terminal of the switching TFT and a second semiconductor layer including polysilicon and a halogen material, an insulating layer formed on the switching TFT and the driving TFT, a first electrode formed on the insulating layer and electrically connected to an output terminal of the driving TFT, an organic light emitting layer formed on the first electrode, and a second electrode formed on the organic light emitting layer.Type: ApplicationFiled: January 23, 2008Publication date: July 31, 2008Inventors: Byoung-june KIM, Yong-mo Choi, Beohm-rock Choi, Sung-hoon Yang, Hwa-yeul Oh, Jae-ho Choi, Jong-moo Huh
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Publication number: 20080173870Abstract: A thin film transistor substrate having low resistivity and reduced contact resistance includes a gate wiring line formed on an insulating substrate, a data wiring line crossing the gate wiring line while being insulated from the gate wiring line, and a pixel electrode connected to a portion of the data wiring line and including a zinc oxide layer pattern doped with a dopant and an anti-oxidizing substance layer pattern.Type: ApplicationFiled: October 30, 2007Publication date: July 24, 2008Inventors: Byeong-beom Kim, Chang-oh Jeong, Yang-ho Bae
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Patent number: 7397063Abstract: A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.Type: GrantFiled: July 26, 2004Date of Patent: July 8, 2008Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuyoshi Itoh, Kaoru Motonami
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Patent number: 7396765Abstract: A method of fabricating a liquid crystal display device according to an embodiment of the present invention includes forming first and second conductive layers on a substrate, wherein the first layer is transparent; patterning the second conductive layer and the first conductive layer using the photo-resist pattern as a mask; etching at least one lateral part of the patterned second conductive layer using the photo-resist pattern as a mask; and removing the remaining photo-resist pattern.Type: GrantFiled: October 21, 2005Date of Patent: July 8, 2008Assignee: LG Display Co., Ltd.Inventors: Dai Yun Lee, Yong In Park
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Patent number: 7396707Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor T including a source region, a drain region, a channel region having a predetermined channel length, a first GOLD region having an impurity concentration lower than the impurity concentration of the source region, a second GOLD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The length of an overlapping portion in plane between the gate electrode and the second GOLD region in the direction of the channel length is set longer than the length in the direction of the channel region of an overlapping portion in plane between the gate electrode and the first GOLD region.Type: GrantFiled: November 30, 2006Date of Patent: July 8, 2008Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshihiko Toyoda, Takao Sakamoto, Kazuyuki Sugahara
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Publication number: 20080157094Abstract: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, including a source region, a drain region and a channel region, and made of a polycrystalline silicon layer; a gate electrode disposed to correspond to the channel region of the semiconductor layer; a gate insulating layer disposed between the semiconductor layer and the gate electrode; and source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer, respectively, wherein the polycrystalline silicon layer comprises a plurality of regions having different Raman spectrum peaks from each other.Type: ApplicationFiled: December 28, 2007Publication date: July 3, 2008Applicant: Samsung SDI Co., Ltd.Inventors: JIN-WOOK SEO, Byoung-Keon Park, Tae-Hoon Yang, Ki-Yong Lee
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Publication number: 20080142803Abstract: With the present invention, it is possible to provide a high quality image display by suppressing such faults as malfunction of a circuit or leakage of a current due to hump caused by the characteristic of a thin film transistor at a channel edge portion. An edge portion 302 of a polysilicon layer 301 functioning as a channel layer is converted into a noncrystalline or fine crystalline area. Because a silicon semiconductor film at the channel edge portion 302 is in the fine crystalline or noncrystalline state, a current flowing there is extremely small, or a current does not flow there. Thus, even when a threshold voltage Vth at a channel central portion is different from that at a channel edge portion, performance of the entire thin film transistor film is little affected, so that display faults due to hump are prevented.Type: ApplicationFiled: December 12, 2007Publication date: June 19, 2008Inventors: Takuo Kaitoh, Eiji Oue
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Publication number: 20080142808Abstract: A thin film transistor and a fabrication method thereof, in which one excimer laser annealing (ELA) makes a pixel portion and a driver portion different from each other in surface roughness and grain size.Type: ApplicationFiled: December 12, 2007Publication date: June 19, 2008Applicant: Samsung SDI Co., Ltd.Inventor: Hong-Ro LEE
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Publication number: 20080135873Abstract: Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.Type: ApplicationFiled: December 7, 2007Publication date: June 12, 2008Applicant: AmberWave Systems CorporationInventors: James Fiorenza, Mark Carroll, Anthony J. Lochtefeld
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Publication number: 20080135849Abstract: A thin film transistor includes a polysilicon layer formed over a substrate having a channel region, a source region and a drain region, a conductive layer formed in an upper layer of the polysilicon layer for covering at least a part of the source region and the drain region, an interlayer insulating film formed in a region to cover at least a region including the polysilicon layer, a contact hole formed to penetrate the interlayer insulating film with a depth to expose the conductive layer and a wiring layer formed along a sidewall of the contact hole.Type: ApplicationFiled: November 28, 2007Publication date: June 12, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Kazushi Yamayoshi
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Publication number: 20080135844Abstract: An object of the present invention is to provide an active matrix type display unit having a pixel structure in which a pixel electrode formed in a pixel portion, a scanning line (gate line) and a data line are suitably arranged, and high numerical aperture is realized without increasing the number of masks and the number of processes. In this display unit, a first wiring arranged between a semiconductor film and a substrate through a first insulating film is overlapped with this semiconductor film and is used as a light interrupting film. Further, a second insulating film used as a gate insulating film is formed on the semiconductor film. A gate electrode and a second wiring are formed on the second insulating film. The first and second wirings cross each other through the first and second insulating films. A third insulating film is formed as an interlayer insulating film on the second wiring, and a pixel electrode is formed on this third insulating film.Type: ApplicationFiled: November 16, 2007Publication date: June 12, 2008Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Shunpei Yamazaki
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Publication number: 20080138944Abstract: The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed.Type: ApplicationFiled: January 8, 2008Publication date: June 12, 2008Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shinji MAEKAWA, Hidekazu MIYAIRI
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Patent number: 7384827Abstract: Exemplary embodiments of the invention provide techniques that enable avoidance of the concentration of an electric field at the edge of a semiconductor film in a semiconductor device such as a thin film transistor, thereby enhancing the reliability. Exemplary embodiments provide a method of manufacturing a semiconductor device using a structure in which a semiconductor film, a dielectric film, and an electrode are deposited.Type: GrantFiled: March 24, 2005Date of Patent: June 10, 2008Assignee: Seiko Epson CorporationInventor: Daisuke Abe
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Patent number: 7384860Abstract: The present invention relates to a method of manufacturing a semiconductor device having an excellent gettering effect. In this method, when phosphorus is added to a poly-Si film, which has been crystallized by the addition of a metal, to subject the resultant poly-Si film to the heat treatment to carry out gettering therefor, the device is performed for the shape of the island-like insulating film on the poly-Si film which is employed when implanting phosphorus. Thereby, the area of the boundary surface between the region to which phosphorus has been added and the region to which no phosphorus has been added is increased to enhance gettering efficiency.Type: GrantFiled: September 15, 2004Date of Patent: June 10, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Osamu Nakamura, Manabu Katsumura, Shunpei Yamazaki
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Publication number: 20080128703Abstract: An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer provided over a top surface and a side surface of the island-shaped semiconductor layer, and a gate electrode provided over the island-shaped semiconductor layer with the insulating layer interposed therebetween. In the insulating layer provided to be in contact with the island-shaped semiconductor layer, a region that is in contact with the side surface of the island-shaped semiconductor layer is made to have a lower dielectric constant than a region over the top surface of the island-shaped semiconductor layer.Type: ApplicationFiled: December 3, 2007Publication date: June 5, 2008Inventors: Kazuko Ikeda, Shinya Sasagawa, Hideomi Suzawa, Shunpei Yamazaki
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Publication number: 20080121892Abstract: The invention discloses an LTPS LCD comprising a plurality of NMOS elements and PMOS elements on a substrate. Each element comprises a SiNx layer underlying or capping a gate electrode. The SiNx layer features an appropriate length extending from the bottom edge of the gate electrode. The SiNx layer can be replaced with a SiOxNy layer.Type: ApplicationFiled: November 29, 2006Publication date: May 29, 2008Inventors: Chang-Ho Tseng, Shih-Pin Wang, Chun-Yen Liu, Kuo-Bin Hsu
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Publication number: 20080116460Abstract: A non-volatile memory device is capable of reducing an excessive leakage current due to a rough surface of a polysilicon and realizing improved blocking function with an oxide film that is thinner by forming a first oxide film and a second oxide film including a silicon oxy-nitride (SiOxNy) layer using nitrous oxide (N2O) plasma. A fabricating method and a memory apparatus of the non-volatile memory device are also discussed.Type: ApplicationFiled: July 13, 2007Publication date: May 22, 2008Applicant: Samsung SDI Co., Ltd.Inventor: Byoung Deog CHOI
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Patent number: 7375373Abstract: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.Type: GrantFiled: July 2, 2002Date of Patent: May 20, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Gab Lee, Bong-Joo Kang, Beom-Seok Cho, Chang-Oh Jeong
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Patent number: 7374983Abstract: Manufacture of TFTs corresponding to various circuits makes structures thereof complex, which involves a larger number of manufacturing steps. Such an increase in the number of the manufacturing steps leads to a higher manufacturing cost and a lower manufacturing yield. In the invention, a high concentration of impurities is doped by using as masks a tapered resist that is used for the manufacture of a tapered gate electrode, and the tapered gate electrode, and then the tapered gate electrode is etched in the perpendicular direction using the resist as a mask. A semiconductor layer under the thusly removed tapered portion of the gate electrode is doped with a low concentration of impurities.Type: GrantFiled: March 15, 2005Date of Patent: May 20, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoru Okamoto
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Publication number: 20080111133Abstract: A thin film transistor includes a substrate; a semiconductor layer disposed on the substrate, and including polycrystalline silicon having a constant directivity and a uniformly distributed crystal grain boundary; a gate insulating layer; a gate electrode; an interlayer insulating layer; and source and drain electrodes.Type: ApplicationFiled: September 28, 2007Publication date: May 15, 2008Applicant: Samsung SDI Co., Ltd.Inventor: JI-SU AHN
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Publication number: 20080100228Abstract: A display device that requires less manufacturing time is presented. The display device includes a light blocking member formed on a substrate, a semiconductor layer formed on the light blocking member, and a gate insulating layer formed on the semiconductor layer. Gate conductors, a first interlayer insulating layer, data conductors, a second interlayer insulating layer, and a pixel electrode are formed. A third interlayer insulating layer is deposited with an opening that extends to the pixel electrode. An organic light emitting member is formed in the opening, and a common electrode is formed. The light blocking member contains nickel and silicon oxide. The presence of nickel-and-silicon-oxide light blocking member below the semiconductor improves the crystallizing speed for the semiconductor layer, reducing the overall manufacturing time. Further, the light blocking member is disposed under the pixel electrodes to prevent light leakage, improving the contrast ratio and image quality.Type: ApplicationFiled: October 25, 2007Publication date: May 1, 2008Inventor: Ji-Yong PARK
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Patent number: 7348197Abstract: A method for fabricating a liquid crystal display device includes providing first and second substrates; forming an active layer on the first substrate, wherein the active layer includes a source region, a drain region, a channel region, and a storage region; forming a first insulation layer on the first substrate; forming a gate electrode, a gate line, a pixel electrode, and a storage line on the first substrate, wherein storage line overlaps the storage region; forming a second insulation layer on the first substrate; forming first and second contact holes through the first and second insulation layers, wherein the first and second contact holes expose respective ones of the source and drain regions; forming a pixel hole through the second insulation layer, wherein the pixel hole exposes the pixel electrode; forming a source electrode electrically connected to the source region through the first contact hole and a drain electrode electrically connected to the drain region through the second contact hole; anType: GrantFiled: June 22, 2005Date of Patent: March 25, 2008Assignee: LG.Philips LCD Co., Ltd.Inventors: Yong In Park, Dea Yuu Lee
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Publication number: 20080067516Abstract: An embodiment of a process for manufacturing a TFT transistor on a substrate comprising the steps of: forming an amorphous silicon layer on the substrate, carrying out a crystallization process of the amorphous silicon layer to form a layer of polycrystalline silicon defining an active area of the TFT transistor in the layer of polycrystalline silicon; forming a dielectric layer on the active area; forming a gate electrode of the TFT transistor on the dielectric layer; carrying out a single ionic implantation step to realize source/drain regions of the TFT transistor, the ionic implantation step being carried out with a tilt or angled with respect to a normal to a plane defined by the substrate, the tilt angle with respect to the normal to the plane defined by the substrate being comprised in the range of approximately between 7° and 45°.Type: ApplicationFiled: August 2, 2007Publication date: March 20, 2008Inventor: Claudia Caligiore
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Publication number: 20080067520Abstract: An organic electro-luminescent display and a method of fabricating the same include an organic light emitting diode, a driving transistor which drives the organic light emitting diode, and a switching transistor which controls an operation of the driving transistor, wherein active layers of the switching and driving transistors are crystallized using silicides having different densities such that the active layer of the driving transistor has a larger grain size than the active layer of the switching layer.Type: ApplicationFiled: September 17, 2007Publication date: March 20, 2008Applicant: SAMSUNG ELECTRONICS CO., LTDInventors: Ji-sim JUNG, Jong-man KIM, Jang-yeon KWON, Kyung-bae PARK
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Publication number: 20080064152Abstract: A fabricating method of an array substrate for a liquid crystal display device including forming a polycrystalline silicon film on a substrate having a display region and a peripheral region, the polycrystalline silicon film having grains of square shape, forming a first active layer in the display region and a second active layer in the peripheral region by etching the polycrystalline silicon film, forming a first gate electrode over the first active layer, a second gate electrode over the second active layer and a gate line connected to the first gate electrode, and forming first source and drain electrodes connected to the first active layer, second source and drain electrodes connected to the second active layer and data line connected to the first source electrode. Further, the second gate electrode overlaps the first active layer to form a first channel region, and the first channel region is formed inside one of the grains.Type: ApplicationFiled: November 13, 2007Publication date: March 13, 2008Inventor: Yun-Ho Jung
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Publication number: 20080064151Abstract: A method of manufacturing a thin film transistor includes: forming an amorphous silicon layer and a blocking layer; forming a photoresist layer having first and second photoresist patterns spaced apart from each other on the blocking layer; etching the blocking layer using the first photoresist pattern as a mask to form first and second blocking patterns; reflowing the photoresist layer so the first and second photoresist patterns abut each other; forming a capping layer and a metal layer; removing the photoresist layer to expose the blocking layer and an offset region between the blocking layer and the metal layer; crystallizing the amorphous silicon layer by diffusing metals in the metal layer through the capping layer; etching the poly silicon layer using the first and second blocking patterns as a mask to form first and second semiconductor layers; and removing the first and second blocking patterns.Type: ApplicationFiled: September 21, 2007Publication date: March 13, 2008Applicant: SAMSUNG SDI CO., LTD.Inventor: Woo-Young SO
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Patent number: 7342353Abstract: The present invention provides a display device which includes signal lines which are formed on an upper surface side of a substrate, an insulation film which is formed such that the film covers the signal lines except for terminal portions of the signal lines, and conductive layers which extend in the extension direction of the signal lines such that the terminal portions traverse the terminal portions. In such a display device, gaps are formed between respective sides of the conductive layer parallel to the extension direction of the conductive layer and the insulation film and holes are formed in the signal lines at portions corresponding to the gaps along the extension direction of the signal lines.Type: GrantFiled: March 31, 2004Date of Patent: March 11, 2008Assignee: Hitachi Displays, Ltd.Inventors: Takahiro Ochiai, Kikuo Ono, Ryutaro Oke
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Publication number: 20080035930Abstract: A thin film transistor substrate includes a first conductive layer formed on a substrate, an anti-diffusion layer deposited on the first conductive layer, a semiconductor layer formed on the anti-diffusion layer, a gate insulating layer deposited on the semiconductor layer, a second conductive layer formed on the gate insulating layer, an interlayer insulating layer deposited on the second conductive layer, and a third conductive layer formed on the interlayer insulating layer, in a first contact hole penetrating through the interlayer insulating layer and the gate insulating layer to reach the semiconductor layer, and in a second contact hole penetrating through the interlayer insulating layer, the gate insulating layer and the anti-diffusion layer to reach the first conductive layer. The third conductive layer includes a pixel electrode formed in island shape on the interlayer insulating layer.Type: ApplicationFiled: July 24, 2007Publication date: February 14, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Atsunori Nishiura, Takuji Imamura
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Patent number: 7317207Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.Type: GrantFiled: June 7, 2005Date of Patent: January 8, 2008Assignee: Hitachi, Ltd.Inventors: Shinya Yamaguchi, Masanobu Miyao, Nobuyuki Sugii, Seang-kee Park, Kiyokazu Nakagawa
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Patent number: 7317227Abstract: A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switched from the fluorine-based gas to a chlorine-based gas at a point of time when a lower oxide film as an underlying film of the semiconductor film is exposed. As the fluorine-based gas, a mixed gas of CF4 and O2 is used, and suitably, a gas ratio of CF4 and O2 in the mixture gas is set at 1:1, and the dry etching is performed therefor. By this etching, a side face of a two-layer structure of the semiconductor film and upper oxide film is optimally tapered, and a crack or a disconnection is prevented from being occurring in a film crossing over the two-layer structure.Type: GrantFiled: May 28, 2004Date of Patent: January 8, 2008Assignee: NEC CorporationInventors: Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
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Publication number: 20080003729Abstract: A semiconductor device having a crystalline semiconductor film with production of a cavity suppressed and a manufacturing method thereof A manufacturing method of a semiconductor device according to the invention comprises the steps of forming an amorphous silicon film on a substrate having an insulating surface, adding a metal element such as Ni for promoting crystallization to the amorphous silicon film, applying heat treatment to crystallize the amorphous silicon film, so that a crystalline silicon film is formed on the substrate, removing a silicon oxide film formed on the surface of the crystalline silicon film due to the heat treatment by a solution containing organic solvent and fluoride, and irradiating laser light or strong light to the crystalline silicon film.Type: ApplicationFiled: August 30, 2007Publication date: January 3, 2008Inventors: Hideto Ohnuma, Masayuki Sakakura, Yasuhiro Mitani, Takuya Matsuo, Hidehito Kitakado
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Publication number: 20070298553Abstract: The production method of the thin film transistor according to the present invention involves the reactive heat CVD process to form the active layer and the source-drain layer. This offers the advantage of eliminating additional steps to crystallize the semiconductor thin film. The resulting stacked thin film transistor is composed of originally crystalline semiconductor thin films. Having the active layer and the source-drain layer formed from crystalline semiconductor thin film, the stacked thin film transistor has a faster working speed than the one formed from amorphous semiconductor thin film. Another advantage of eliminating steps for crystallization is uniform quality which would otherwise be adversely affected by crystallization. In addition, the fact that the source-drain layer is formed from a previously doped crystalline semiconductor thin film means that there is no need for any step to introduce impurities after film formation.Type: ApplicationFiled: June 15, 2007Publication date: December 27, 2007Inventor: Masafumi Kunii
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Patent number: 7312163Abstract: The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least one of the precursors is asymmetric with respect to a physical property. A field influencing the asymmetric physical property is oriented within the reaction chamber, and is utilized to affect alignment of the precursor having the asymmetric property as the material is formed. The asymmetric physical property can, for example, be an anisotropic charge distribution associated with the precursor, and in such aspect, the field utilized to influence the asymmetric physical property can be an electric field provided within the reaction chamber and/or a magnetic field provided within the reaction chamber. The methodology of the present invention can be utilized in atomic layer deposition processes.Type: GrantFiled: September 24, 2003Date of Patent: December 25, 2007Assignee: Micron Technology, Inc.Inventors: Garo J. Derderian, Gurtej S. Sandhu
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Patent number: 7307282Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.1 atomic % but not larger than 10 atomic % while adding a metal element thereto, wherein not smaller than 20% of the lattice plane {101} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, not larger than 3% of the lattice plane {001} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, and not larger than 5% of the lattice plane {111} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film as detected by the electron backscatter diffraction pattern method.Type: GrantFiled: December 5, 2003Date of Patent: December 11, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo, Yasuyuki Arai
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Patent number: 7291523Abstract: After crystallization of a semiconductor film is performed by irradiating first laser light (energy density of 400 to 500 mJ/cm2) in an atmosphere containing oxygen, an oxide film formed by irradiating the first laser light is removed. It is next performed to irradiate second laser light under an atmosphere that does not contain oxygen (at a higher energy density than that of the first laser light irradiation), thus to increase the flatness of the semiconductor film.Type: GrantFiled: January 3, 2006Date of Patent: November 6, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Setsuo Nakajima, Hidekazu Miyairi
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Publication number: 20070224744Abstract: A thin film transistor may include an active layer formed on an insulating substrate and formed with source/drain regions and a channel region; a gate insulating film formed on the active layer; and a gate electrode formed on the gate insulating film. The gate electrode may be formed of a conductive metal film pattern and a conductive oxide film covering the conductive metal film pattern. The source/drain regions may include an LDD region, and the LDD region may at least partially overlap with the gate electrode.Type: ApplicationFiled: May 22, 2007Publication date: September 27, 2007Applicant: SAMSUNG SDI CO., LTD.Inventors: Jae-Bon Koo, Sang-Gul Lee
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Publication number: 20070218615Abstract: A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is converted to a gate oxide layer. The conduction channel formed by the SiGe layer is permanently strained to increase its mobility particularly hole mobility.Type: ApplicationFiled: May 17, 2007Publication date: September 20, 2007Inventors: David Jones, Robert Haase
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Publication number: 20070210451Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.Type: ApplicationFiled: May 18, 2007Publication date: September 13, 2007Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hisashi Ohtani, Etsuko Fujimoto
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Publication number: 20070200139Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.Type: ApplicationFiled: April 27, 2007Publication date: August 30, 2007Inventors: Hiroshi Shibata, Shinji Maekawa
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Patent number: 7247527Abstract: It is an object of the present invention to provide a method for manufacturing a crystalline semiconductor film comprising the steps of crystallizing with the use of the metal element for promoting the crystallization to control the orientation and irradiating the laser once to form a crystalline semiconductor film having a small crystal grain arranged in a grid pattern at a regular interval. In the present invention made in view of the above object, a ridge forms a grid pattern on a surface of the crystalline semiconductor film in such a way that a crystalline semiconductor film is formed by adding the metal element for promoting the crystallization to the amorphous semiconductor film and the pulsed laser whose polarization direction is controlled is irradiated thereto. As the means for controlling the polarization direction, a half-wave plate or a mirror is used.Type: GrantFiled: July 28, 2004Date of Patent: July 24, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihisa Shimomura, Masaki Koyama, Hironobu Shoji
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Patent number: 7229872Abstract: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 ? to 1400 ? and the nitride is subsequently removed and a thin oxide, for example 320 ? is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon.Type: GrantFiled: May 13, 2004Date of Patent: June 12, 2007Assignee: International Rectifier CorporationInventor: Naresh Thapar
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Patent number: 7214554Abstract: A method for making an OLED device includes providing a substrate having one or more test regions and one or more device regions, moving the substrate into a least one deposition chamber for deposition of at least one organic layer, and depositing the at least one organic layer through a shadowmask selectively onto the at least one device region and at least one test region on the substrate. The method also includes measuring a property of the at least one organic layer in the at least one test region, and adjusting the deposition process in accordance with the measured property.Type: GrantFiled: March 18, 2004Date of Patent: May 8, 2007Assignee: Eastman Kodak CompanyInventors: Dustin L. Winters, Michele L. Ricks, Nancy J. Armstrong, Robert S. Cupello
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Patent number: 7211826Abstract: An organic electroluminescent display includes a substrate having an array portion with pixels, and a pad portion coupled to an external power supply. A semiconductor structure is formed on the substrate with a source electrode, a drain electrode and a pad. A passivation layer is formed on the semiconductor structure with via holes exposing regions of the source and the drain electrodes at the array portion and the pad at the pad portion. Portions of the passivation layer contacting the via holes between the array portion and the pad portion have the same thickness. A conductive layer fills the via holes. A pixel defining layer is formed over the entire surface of a flattening layer and the conductive layer with pixel regions exposing regions of the conductive layer at the array portion. An organic electroluminescent film is formed at each pixel region.Type: GrantFiled: August 27, 2004Date of Patent: May 1, 2007Assignee: Samsung SDI Co., Ltd.Inventors: Sang-Il Park, Tae-Wook Kang
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Patent number: 7202529Abstract: A field effect transistor includes a substrate having a doping of a first conductivity type, a drain area in the substrate having a doping of a second conductivity type oppposite the first conductivity type, a source area in the substrate being laterally spaced from the drain area and having a doping of the second conductivity type, and a channel area in the substrate that is arranged between the source area and the drain area. In a portion of the substrate bordering the drain area, an area having a doping of the second conductivity type, which is connected to the drain area, is arranged such that in the portion alternating regions having the first conductivity type and having the second conductivity type are arranged.Type: GrantFiled: March 11, 2004Date of Patent: April 10, 2007Assignee: Infineon Technologies AGInventors: Ulrich Krumbein, Hans Taddiken