Lateral Single Gate Single Channel Transistor With Noninverted Structure, I.e., Channel Layer Is Formed Before Gate (epo) Patents (Class 257/E21.413)
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Patent number: 7622739Abstract: A thin film transistor for a flat panel display, and more particularly to a thin film transistor for a flat panel display having a protrusion in a part of a gate electrode includes a substrate on which an insulating layer is deposited, a semiconductor layer, which is a layer having predetermined width and length on the insulating layer, provided with doping regions in a letter U shape and a channel region between the doping regions; a gate insulating layer formed on the semiconductor layer; a gate electrode formed on the gate insulating layer to traverse the doping region; and a protrusion, which is a part of the gate electrode, formed on the gate insulating layer to be opposed to the channel region.Type: GrantFiled: December 4, 2007Date of Patent: November 24, 2009Assignee: Samsung Mobile Display Co., Ltd.Inventor: Jong-yun Kim
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Patent number: 7618881Abstract: A method for forming a thin-film transistor on an insulating substrate includes the steps of: forming a non-single-crystal semiconductor thin film on the insulating substrate; forming a gate insulating film on the non-single-crystal semiconductor thin film; forming a gate electrode including a lower gate electrode and an upper gate electrode on the gate insulating film, the lower gate electrode having a portion that is not covered by the upper gate electrode; forming a source-drain region and an LDD (lightly doped drain) region in the non-single-crystal thin film semiconductor film concurrently by introducing an impurity into the non-single-crystal semiconductor thin film through the gate electrode and the gate insulating film; and etching away an exposed portion of the lower gate electrode by using the upper gate electrode as a mask.Type: GrantFiled: January 19, 2007Date of Patent: November 17, 2009Assignees: NEC Corporation, NEC LCD Technologies, Ltd.Inventor: Tadashi Satou
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Patent number: 7615384Abstract: A method of manufacturing a semiconductor device with the use of a laser crystallization method is provided which can prevent grain boundaries from being formed in a channel forming region of a TFT and which can avoid substantial reduction in TFT mobility, reduction in on current, and increase in off current due to the grain boundaries, and a semiconductor device manufactured by using the manufacturing method is also provided. Stripe shape or rectangular shape unevenness is formed only in a driver circuit. Continuous wave laser light is irradiated to a semiconductor film formed on an insulating film along the stripe unevenness of the insulating film or along a major axis or minor axis of the rectangular unevenness. Although it is most preferable to use the continuous wave laser light at this point, pulse wave laser light may also be used.Type: GrantFiled: June 6, 2005Date of Patent: November 10, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Publication number: 20090263942Abstract: A single crystal semiconductor substrate including an embrittlement layer is attached to a base substrate with an insulating layer interposed therebetween, and the single crystal semiconductor layer is separated at the embrittlement layer by heat treatment; accordingly, a single crystal semiconductor layer is fixed over the base substrate. The single crystal semiconductor layer is irradiated with a laser beam so that the single crystal semiconductor layer is partially melted and then is re-single crystallized, whereby crystal defects are removed. In addition, an island-shaped single crystal semiconductor layer for forming an n-channel transistor is channel-doped using a photomask and then is etched back using the photomask so that the island-shaped single crystal semiconductor layer for forming an n-channel transistor is thinner than the island-shaped single crystal semiconductor layer for forming a p-channel transistor.Type: ApplicationFiled: April 9, 2009Publication date: October 22, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideto OHNUMA, Noritsugu NOMURA
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Publication number: 20090258465Abstract: A silicon crystallization mask of the present invention includes; a main exposure portion including a plurality of complete light transmission regions which completely transmit light therethrough, and a preliminary exposure portion including a plurality of incomplete light transmission regions, which each partially transmit light therethrough, wherein at least two of the incomplete light transmission regions have different magnitudes of light transmittance from each other.Type: ApplicationFiled: March 19, 2009Publication date: October 15, 2009Applicant: SAMSUNG ELLECTRONIC CO., LTD.Inventor: Se-Jin CHUNG
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Patent number: 7601566Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.Type: GrantFiled: October 13, 2006Date of Patent: October 13, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masayuki Sakakura, Hideto Ohnuma, Hideaki Kuwabara
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Publication number: 20090230400Abstract: A method for fabricating a thin film transistor is described. The method includes: providing a substrate; forming a sacrificial layer on the substrate; forming a polysilicon pattern layer on the substrate to surround the sacrificial layer; forming a gate insulation layer to cover at least the polysilicon pattern layer; forming a gate pattern on the gate insulation layer above the polysilicon pattern layer; forming a source region, a drain region, and an active region in the polysilicon pattern layer, wherein the active region is between the source region and the drain region; forming a passivation layer to cover the gate pattern and a portion of the gate insulation layer; forming a source conductive layer and a drain conductive layer on the passivation layer, wherein the source conductive layer and the drain conductive layer are electrically connected to the source region and the drain region of the polysilicon pattern layer respectively.Type: ApplicationFiled: August 25, 2008Publication date: September 17, 2009Applicant: Chunghwa Picture Tubes, LTD.Inventors: Chia-Wen Chang, Jiun-Jia Huang, Tzu-Heng Chang, Tan-Fu Lei, Szu-Fen Chen
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Publication number: 20090224258Abstract: In a display device which forms thin film transistors on a substrate, the thin film transistor includes an n-type thin film transistor and a p-type thin film transistor, a gate electrode of one thin film transistor out of the n-type thin film transistor and the p-type thin film transistor forms a metal layer made of a material different from the gate electrode on a gate-insulation-film side thereof, and an LDD layer is formed over a semiconductor layer of at least one of the n-type thin film transistor and the p-type thin film transistor.Type: ApplicationFiled: February 25, 2009Publication date: September 10, 2009Inventors: Eiji OUE, Toshio Miyazawa
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Patent number: 7585717Abstract: A method for manufacturing a semiconductor device includes: forming a lower gate electrode over a substrate; forming a sacrifice film over the substrate such that the lower gate electrode is overlapped with the sacrifice film; forming a semiconductor film over the sacrifice film such that the semiconductor film crosses over the lower gate electrode; removing the sacrifice film; forming a lower gate insulating film in an empty space between the lower gate electrode and the semiconductor film, the empty space being obtained by removing the sacrifice film; forming an upper gate insulating film over the semiconductor film; and forming an upper gate electrode over the upper gate insulating film, the upper gate electrode being electrically connected to the lower gate electrode.Type: GrantFiled: November 29, 2006Date of Patent: September 8, 2009Assignee: Seiko Epson CorporationInventor: Ichio Yudasaka
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Publication number: 20090203177Abstract: A method of manufacturing a thin-film semiconductor device, including forming a crystallized region on a transparent insulating substrate, implanting an impurity into the crystallized region and an amorphous semiconductor layer to form a source diffusion region and a drain diffusion region in the crystallized region, subjecting the resultant structure to heat treatment, thereby not only activating the impurity implanted in the crystallized region and the amorphous semiconductor layer but also restoring crystallinity of only a portion of the amorphous semiconductor layer which is formed on the crystallized region to thereby turn the portion into a polycrystalline semiconductor layer, and subjecting the resultant surface to selective etching to thereby leave only the polycrystalline semiconductor layer and to remove the amorphous semiconductor layer formed on other regions, thereby forming, in a self-aligned manner, a stacked source diffusion layer and a stacked drain diffusion layer.Type: ApplicationFiled: February 5, 2009Publication date: August 13, 2009Inventor: Katsunori MITSUHASHI
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Publication number: 20090184321Abstract: This invention provides a top-gate microcrystalline thin film transistor and a method for manufacturing the same. An inversion layer channel is formed in a top interface of a microcrystalline active layer, and being separated from an incubation layer in a bottom interface of the microcrystalline active layer. The inversion layer channel is formed in the crystallized layer of the top interface of the microcrystalline active layer. As such, the present microcrystalline thin film transistor has better electrical performance and reliability.Type: ApplicationFiled: August 12, 2008Publication date: July 23, 2009Inventors: Cheng-Ju TSAI, Bo-Chu CHEN, Ding-Kang SHIH, Jung-Jie HUANG, Yung-Hui YEH
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Patent number: 7563658Abstract: The present invention relates to a method for manufacturing a semiconductor film, including the steps of forming a transparent conductive film, forming a first conductive film over the transparent conductive film, forming a second conductive film over the first conductive film, etching the second conductive film with a gas including chlorine, and etching the first conductive film with a gas including fluorine. During etching of the second conductive film with a gas including chlorine, the transparent conductive film is protected by the first conductive film. During etching of the first conductive film with the gas including fluorine, the transparent conductive film does not react with the gas including fluorine. Therefore, no particle is formed.Type: GrantFiled: December 22, 2005Date of Patent: July 21, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihiro Ishizuka, Satoru Okamoto, Shigeharu Monoe, Shunpei Yamazaki
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Patent number: 7560397Abstract: A method of manufacturing a semiconductor device is provided which uses a laser crystallization method capable of increasing substrate processing efficiency. An island-like semiconductor film including one or more islands is formed by patterning (sub-island). The sub-island is then irradiated with laser light to improve its crystallinity, and thereafter patterned to form an island. From pattern information of a sub-island, a laser light scanning path on a substrate is determined such that at least the sub-island is irradiated with laser light. In other words, the present invention runs laser light so as to obtain at least the minimum degree of crystallization of a portion that has to be crystallized, instead of irradiating the entire substrate with laser light.Type: GrantFiled: February 22, 2007Date of Patent: July 14, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiroshi Shibata, Koichiro Tanaka, Masaaki Hiroki, Mai Akiba
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Patent number: 7560321Abstract: According to a crystallization method, in the crystallization by irradiating a non-single semiconductor thin film of 40 to 100 nm provided on an insulation substrate with a laser light, a light intensity distribution having an inverse peak pattern is formed on the surface of the substrate, a light intensity gradient of the light intensity distribution is controlled, a crystal grain array is formed in which each crystal grain is aligned having a longer shape in a crystal growth direction than in a width direction and having a preferential crystal orientation (100) in a grain length direction, and a TFT is formed in which a source region and a drain region are formed so that current flows across a plurality of crystal grains of the crystal grain array in the crystal growth direction.Type: GrantFiled: March 16, 2007Date of Patent: July 14, 2009Assignee: Advanced LCD Technologies Development Center Co., Ltd.Inventors: Tomoya Kato, Masakiyo Matsumura
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Publication number: 20090170248Abstract: A method for manufacturing a thin film transistor with improved current characteristics and high electron mobility. According to the method, when an amorphous silicon thin film is crystallized into a polycrystalline silicon thin film by metal-induced crystallization, annealing conditions of the amorphous silicon thin film and the amount of a metal catalyst doped into the amorphous silicon thin film are optimized to reduce the regions of a metal silicide distributed at grain boundaries of the polycrystalline silicon thin film. In addition, oxygen (O2) gas or water (H2O) vapor is supplied to form a passivation film on the surface of the polycrystalline silicon thin film.Type: ApplicationFiled: December 22, 2008Publication date: July 2, 2009Inventors: Hyoung June Kim, Dong Hoon Shin, Su Kyoung Lee, Jung Min Lee, Wang Jun Park, Sung Ryoung Ryu, Hoon Kim
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Patent number: 7554116Abstract: A display device according to the present invention includes: a planarization layer for insulating between a gate electrode etc. and a data wiring, a drain electrode, or the like of the transistor; and a barrier layer that is formed on an upper surface or lower surface of the planarization layer and at the same time, adapted to suppress diffusion of moisture or degassing components from the planarization layer. The display device adopts a device structure effective in reducing the plasma damage on the planarization layer by devising a positional relationship between the planarization layer and the barrier layer. Also, in combination with a novel structure as a structure for a pixel electrode, effects such as an increase in luminance can be provided as well.Type: GrantFiled: May 26, 2005Date of Patent: June 30, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Murakami, Mitsuaki Osame
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Publication number: 20090159887Abstract: A thin film transistor and a method of manufacturing the thin film transistor is disclosed. The thin film transistor includes first and second ohmic contact layers, an activation layer, an insulating layer, a source electrode formed on the insulating layer and connected to the first ohmic contact layer through first contact hole, a drain electrode formed on the insulating layer and connected to the second ohmic contact layer through second contact hole, a gate electrode formed on the insulating layer between the source electrode and the drain electrode and overlapping the activation layer, and a protective layer formed on the source electrode, the drain electrode, and the gate electrode.Type: ApplicationFiled: July 16, 2008Publication date: June 25, 2009Inventors: Jong-Moo HUH, Joon-Hoo CHOI, Seung-Kyu PARK
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Patent number: 7550308Abstract: A field-effect transistor including an electrically conductive substrate; a first insulating film coating the electrically conductive substrate; a gate electrode disposed on the electrically conductive substrate with the first insulating film interposed therebetween; a source electrode; a drain electrode opposing the source electrode with the channel therebetween; a second insulating film covering the gate electrode; and a semiconductor layer having a width larger than a width of the gate electrode in the channel width direction and being partly provided on the gate electrode with the second insulating film interposed therebetween so that the gate electrode, the second insulating film, and the semiconductor layer are laminated in the channel.Type: GrantFiled: May 26, 2006Date of Patent: June 23, 2009Assignee: Canan Kabushiki KaishaInventors: Hideki Yoshinaga, Hideo Mori, Nobutaka Ukigaya, Nozomu Izumi
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Publication number: 20090142886Abstract: A method of fabricating a thin film transistor (TFT) includes first providing a strip-shaped silicon island which is a thin film region with a predetermined long side and short side. Next, the strip-shaped silicon island is subject to an ion implantation to form a first ion doping region and a second ion doping region. The first and second ion doping regions, respectively used as the source and the drain of the TFT, are located at two sides along the long side of the island and substantially perpendicular to the gate. A gate is formed over the strip-shaped silicon island and the first and second ion doping regions, wherein the gate is substantially parallel to the direction of the short side.Type: ApplicationFiled: February 16, 2009Publication date: June 4, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chi-Lin Chen, Yu-Cheng Chen, Hsing-Hua Wu, Po-Tsun Liu
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Publication number: 20090134397Abstract: A non-single-crystal semiconductor layer is formed over a substrate, and then a single crystal semiconductor layer is formed over part of the non-single-crystal semiconductor layer. Thus, a semiconductor element of a region which requires a large area (e.g. a pixel region in a display device) can be formed using the non-single-crystal semiconductor layer, and a semiconductor element of a region which requires high speed operation (e.g. a driver circuit region in a display device) can be formed using the single crystal semiconductor layer.Type: ApplicationFiled: November 21, 2008Publication date: May 28, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tomokazu YOKOI, Yujiro Sakurada
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Publication number: 20090121231Abstract: Aspects of the invention relate to thin film transistors, a method of fabricating the same, and an organic light-emitting diode device using the same. A thin film transistor according to an aspect of the invention includes a semiconductor layer formed from polysilicon in which a grain size deviation is within a range of substantially ±10%. Accordingly, aspects of the invention can improve non-uniformity of image characteristics due to a non-uniform grain size in polysilicon produced by a sequential lateral solidification (SLS) crystallization process.Type: ApplicationFiled: November 13, 2008Publication date: May 14, 2009Applicant: Samsung SDI Co., Ltd.Inventors: Kyoung-Bo KIM, Yong-Woo Park, Chang-Young Jeong, Sung-Won Doh, Dae-Woo Lee, Jong-Mo Yeo
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Patent number: 7528466Abstract: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).Type: GrantFiled: July 12, 2005Date of Patent: May 5, 2009Assignee: AU Optronics Corp.Inventors: Yu-Wei Liu, Wen-Ching Tsai, Kuo-Yu Huang, Hui-Fen Lin
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Publication number: 20090108260Abstract: A method for manufacturing a pixel structure is provided. First, a first mask process is performed to form a patterned first metal layer on a substrate, wherein the patterned first metal layer includes a gate. Next, a second mask process is performed to form a patterned insulating layer and a patterned semiconductor layer over the gate, wherein the patterned insulating layer is disposed on the patterned first metal layer, and the patterned semiconductor layer is disposed on the patterned insulating layer. Then, a third mask process is performed to define a thin film transistor (TFT) and a pixel electrode connected thereto and to form a passivation layer to cover the TFT.Type: ApplicationFiled: March 21, 2008Publication date: April 30, 2009Applicant: AU OPTRONCS CORP.Inventors: Han-Tu Lin, Chien-Hung Chen
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Patent number: 7525135Abstract: On a poly-silicon layer formed on a glass substrate, a gate electrode is formed via a gate insulation film. After forming an impurity-doped region in the poly-silicon layer using the gate electrode as a mask, an insulation layer is formed on the gate electrode and an insulation film is then formed covering these. At this stage, a step which is low in a periphery of the gate electrode but high in a center of the gate electrode is formed in the surface of the insulation layer which formed on the gate electrode, ensuring that the insulation layer and the insulation film on the center of the gate electrode attain a higher reflectance of laser beam than the insulation film and the gate insulation layer on the impurity-doped region do.Type: GrantFiled: July 8, 2005Date of Patent: April 28, 2009Assignee: NEC CorporationInventor: Daisuke Iga
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Patent number: 7518146Abstract: Plurality of pixels (102) are arranged on the substrate. Each of the pixels (102) is provided with an EL element which utilizes as a cathode a pixel electrode (105) connected to a current control TFT (104). On a counter substrate (110), a light shielding film (112) is disposed at the position corresponding to periphery of each pixel (102), while a color filter (113) is disposed at the position corresponding to each of the pixels (102). This light shielding film makes the contour of the pixels clear, resulting in an image display with high definition. In addition, it is possible to fabricate the EL display device of the present invention with most of an existing manufacturing line for liquid crystal display devices. Thus, an amount of equipment investment can be significantly reduced, thereby resulting in a reduction in the total manufacturing cost.Type: GrantFiled: March 1, 2005Date of Patent: April 14, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Mayumi Mizukami, Toshimitsu Konuma
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Publication number: 20090090913Abstract: A method and a dual-gate memory device having a memory transistor and an access transistor are provided to allow multiple bits to be stored in the dual-gate memory device. The memory transistor and the access transistor each have a channel region formed in a mobility enhanced material crystallized from an amorphous semiconductor material. The amorphous semiconductor material may include, for example, silicon. Mobility enhancement may be achieved by: (a) Excimer laser annealing; (b) lateral crystallization; (c) metal-induced lateral crystallization; (d) a combination of laser annealing and metal-induced laterally crystallization steps; or (e) solid-phase, epitaxially growth.Type: ApplicationFiled: October 3, 2007Publication date: April 9, 2009Inventor: Andrew J. Walker
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Patent number: 7514303Abstract: A liquid crystal display device includes (a) a first substrate, (b) a second substrate spaced away from and facing the first substrate, (c) a liquid crystal layer sandwiched between the first and second substrates, (d) a transistor formed on the first substrate, (e) a wiring layer formed on the first substrate and electrically connected to the transistor, (f) a reflection electrode formed on the first substrate, an external incident light being reflected at the reflection electrode towards a viewer, and (g) a compensation layer formed directly on the wiring layer. The reflection electrode does not cover the wiring layer therewith, and the compensation layer has almost the same height as a height of the reflection electrode, the height being measured from a surface of the first substrate.Type: GrantFiled: December 11, 2006Date of Patent: April 7, 2009Assignee: NEC LCD Technologies, Ltd.Inventors: Yuichi Yamaguchi, Hironori Kikkawa, Hiroshi Kanoh, Teruaki Suzuki, Hidenori Ikeno
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Patent number: 7510917Abstract: In an active matrix display device integrated with peripheral drive circuits, an image sensor is provided on the same substrate as a pixel matrix and peripheral drive circuits. The image sensor is formed on the substrate having pixel electrodes, pixel TFTs connected to the pixel electrodes and CMOS-TFTs for driving the pixel TFTs. The light receiving unit of the image sensor has light receiving elements having a photoelectric conversion layer and light receiving TFTs. These TFTs are produced in the same step. The lower electrode and transparent electrode of the light receiving element are produced by patterning the same film as the light shielding film and the pixel electrodes arranged in the pixel matrix.Type: GrantFiled: June 19, 2007Date of Patent: March 31, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Masayuki Sakakura
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Publication number: 20090057679Abstract: A manufacturing method of a TFT is provided. A polysilicon island, a gate insulating layer and a gate are sequentially formed on a substrate. LDD regions are formed in the polysilicon island below two sides of the gate, while the polysilicon island below the gate is a channel region. A metal oxidation process is performed to form a gate oxidation layer on the gate. A source and a drain are formed in the polysilicon island below two sides of the gate oxidation layer. A dielectric layer is formed on the gate insulating layer. Portions of the dielectric layer and the gate insulating layer are removed to expose a portion of the source and drain, and a patterned dielectric layer and a patterned gate insulating layer are formed. A source and a drain conductive layers electrically respectively connected to the source and the drain are formed on the patterned dielectric layer.Type: ApplicationFiled: July 7, 2008Publication date: March 5, 2009Applicant: CHUNGHWA PICTURE TUBES, LTD.Inventors: Chin-Chuan Lai, Wen-Chun Yeh
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Publication number: 20090061570Abstract: A thin film transistor (TFT) formed on a substrate includes a polycrystalline film, a gate insulator, a hydrogen-supplying film and a gate electrode. The polycrystalline film is formed on the substrate. Two sides of the polycrystalline film serve as the source and the drain of the semiconductor device, and the central region of the polycrystalline layer serves as the channel. The gate insulator is formed on the polycrystalline film, then the polycrystalline film is ions implanted, and the hydrogen-supplying film is formed on the gate insulator. The gate electrode is formed on the hydrogen-supplying film above the channel. The hydrogen-supplying film supplies hydrogen to the polycrystalline film, especially to the channel, so as to transform the unsaturated bonds into hydrogen bonds in the channel for avoiding the unsaturated bonds to degrade the charge carrier efficiency of the channel.Type: ApplicationFiled: October 30, 2008Publication date: March 5, 2009Inventors: Kuang-Chao Yeh, Wen-Bin Hsu
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Publication number: 20090050894Abstract: A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and including a channel region and source and drain regions, a gate electrode disposed in a position corresponding to the channel region of the semiconductor layer, a gate insulating layer interposed between the gate electrode and the semiconductor layer to electrically insulate the semiconductor layer from the gate electrode, a metal structure made up of metal layer, a metal silicide layer, or a double layer thereof disposed apart from the gate electrode over or under the semiconductor layer in a position corresponding to a region of the semiconductor layer other than a channel region, the structure being formed of the same material as the gate electrode, and source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer.Type: ApplicationFiled: August 20, 2008Publication date: February 26, 2009Applicant: Samsung SDI Co., Ltd.Inventors: Byoung-Keon PARK, Jin-Wook Seo, Tae-Hoon Yang, Kil-Won Lee
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Publication number: 20090050893Abstract: A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and crystallized using a metal catalyst, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes disposed on the interlayer insulating layer and electrically connected to source and drain regions of the semiconductor layer through contact holes exposing predetermined regions of the source and drain regions of the semiconductor layer formed within the gate insulating layer and the interlayer insulating layer. A metal silicide including a metal that is different from the metal catalyst is present within a region of the semiconductor layer under the contact hole from the surface of the semiconductor layer to a predetermined depth.Type: ApplicationFiled: August 20, 2008Publication date: February 26, 2009Applicant: Samsung SDI Co., Ltd.Inventor: Byoung-Keon PARK
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Patent number: 7491562Abstract: In a light emitting device, it is preferable that a surface of a film below a light-emitting element has flatness. Therefore, treatment such as planarization of a surface of a film is performed after forming the film. The present invention proposes a structure of a light-emitting device that can make the foregoing planarization easier. The same layer as a wiring formed on a first film is used to manufacture a second film. Herewith, a portion of the first film below a light-emitting element can be prevented from being etched to form unevenness at a surface of the first film during the formation of the wiring. In addition, a surface of a third film is made higher by providing the second film to enable local planarization.Type: GrantFiled: September 6, 2007Date of Patent: February 17, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Murakami, Noriko Miyagi
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Publication number: 20090029509Abstract: A substrate processing apparatus includes a plurality of evacuable treatment chambers connected to one another via an evacuable common chamber, and the common chamber is provided with means for transporting a substrate between each treatment chamber. More specifically, a substrate processing apparatus includes a plurality of evacuable treatment chambers, at least one of said treatment chambers having a film formation function through a vapor phase reaction therein, at least one of said treatment chambers having an annealing function with light irradiation and at least one of said treatment chambers having a heating function therein. The apparatus also has a common chamber through which said plurality of evacuable treatment chambers are connected to one another, and a transportation means provided in said common chamber for transporting a substrate between each treatment chamber.Type: ApplicationFiled: September 17, 2008Publication date: January 29, 2009Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Hiroyuki Shimada, Mitsunori Sakama, Hisashi Abe, Satoshi Teramoto
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Patent number: 7479415Abstract: A method for fabricating a polysilicon silicon liquid crystal display device is disclosed in which a contact hole connecting source and drain electrodes to an active layer is formed without a stepped portion. An insulation layer containing a porous silicon nitride layer is formed. Wet etching the contact hole through the porous silicon nitride layer and an underlying silicon oxide layer does not generate the stepped portion as the etch rates of the porous silicon nitride layer and the silicon oxide layer are the same. Because the stepped portion is not generated at a contact hole, disconnection of source and drain electrodes formed in the contact hole is prevented, thereby preventing deterioration of the liquid crystal display device from occurring.Type: GrantFiled: December 6, 2004Date of Patent: January 20, 2009Assignee: LG. Display Co., Ltd.Inventors: Hun Jeoung, Chang-Jae Jang
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Publication number: 20090014727Abstract: A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.Type: ApplicationFiled: July 14, 2008Publication date: January 15, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Man Kim, Young-Goo Song, Hyang-Shik Kong, Dong-Hyun Ki, Seong-Young Lee, Joo-Ae Yoon, Jong-Woong Chang
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Patent number: 7476600Abstract: The invention includes a method of fabricating a gate structure for a field effect transistor and the gate structure. The method includes providing a crystalline silicon substrate and epitaxially growing a gate insulating layer of crystalline rare earth insulating material on the crystalline silicon substrate. A gate stack of crystalline silicon is then epitaxially grown on the layer of crystalline rare earth insulating material and doped to provide a desired type of conductivity. The gate insulating layer and the gate stack are etched and a metal electrical contact is deposited on the epitaxially grown gate stack of crystalline silicon to define a gate structure.Type: GrantFiled: November 9, 2006Date of Patent: January 13, 2009Assignee: Translucent, Inc.Inventor: Petar B. Atanackovic
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Publication number: 20090001380Abstract: A thin film transistor includes a substrate, a semiconductor layer disposed on the substrate, including a channel region and source and drain regions and crystallized using a metal catalyst, a gate electrode disposed to correspond to a predetermined region of the semiconductor layer, a gate insulating layer disposed between the gate electrode and the semiconductor layer to insulate the semiconductor layer from the gate electrode, and source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer, respectively. The metal catalyst within 150 ? from a surface of the semiconductor layer in a vertical direction is formed to have a concentration exceeding 0 and not exceeding 6.5×E17 atoms per cm3 in the channel region of the semiconductor layer. An organic light emitting diode (OLED) display device includes the thin film transistor.Type: ApplicationFiled: June 27, 2008Publication date: January 1, 2009Applicant: Samsung SDI Co., Ltd.Inventors: Tae-Hoon Yang, Byoung-Keon Park, Jin-Wook Seo, Ki-Yong Lee, Kil-Won Lee
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Publication number: 20080308809Abstract: A thin film transistor (TFT), a method of fabricating the TFT, and a display device including the TFT are provided. The TFT includes a semiconductor layer having a channel region and source and drain regions is crystallized using a crystallization-inducing metal. The crystallization-inducing metal is gettered by either a metal other than the crystallization-inducing metal or a metal silicide of a metal other than the crystallization-inducing metal. A length and width of the channel region of the semiconductor layer and a leakage current of the semiconductor layer satisfy the following equation: Ioff/W=3.4E-15 L2+2.4E-12 L+c, wherein Ioff (A) is the leakage current of the semiconductor layer, W (mm) is the width of the channel region, L(?m) is the length of the channel region, and “c” is a constant ranging from 2.5E-13 to 6.8E-13.Type: ApplicationFiled: June 13, 2008Publication date: December 18, 2008Applicant: Samsung SDI Co., Ltd.Inventors: Tae-Hoon Yang, Ki-Yong Lee, Jin-Wook Seo, Byoung-Keon Park
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Patent number: 7465957Abstract: To realize a semiconductor device including a capacitor element capable of obtaining a sufficient capacitor without reducing an opening ratio, in which a pixel electrode is flattened in order to control a defect in orientation of liquid crystal. A semiconductor device of the present invention includes a light-shielding film formed on the thin film transistor, a capacitor insulating film formed on the light-shielding film, a conductive layer formed on the capacitor insulating film, and a pixel electrode that is formed so as to be electrically connected to the conductive layer, in which a storage capacitor element comprises the light-shielding film, the capacitor insulating film, and the conductive layer, whereby an area of a region serving as the capacitor element can be increased.Type: GrantFiled: December 8, 2004Date of Patent: December 16, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Arao
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Patent number: 7465648Abstract: When a rectangular image having homogeneous intensity distribution is transferred by an imaging optical system, aberration adversely affects the homogeneity of the intensity distribution. The present invention provides a laser irradiation apparatus that can suppress the aberration due to the imaging optical system typified by a cylindrical lens, that can enlarge the square measure of the beam spot in which the intensity distribution is homogenous, and that can anneal the irradiated surface homogeneously efficiently. Moreover, the present invention provides a method for manufacturing a semiconductor device with the use of the laser irradiation apparatus. In the present invention, the divergence of the laser beam is suppressed and the size of the imaging optical system is miniaturized by using an off-axis lens array such as an off-axis cylindrical lens array. By the miniaturization, it is possible to reduce the cost, to facilitate the maintenance, and to suppress the aberration.Type: GrantFiled: November 4, 2004Date of Patent: December 16, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Koichiro Tanaka
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Thin film transistor (TFT) and flat panel display including the TFT and their methods of manufacture
Publication number: 20080299713Abstract: A Thin Film Transistor (TFT) reduces interconnection resistance of source/drain electrodes, prevents contamination from an active layer, reduces contact resistance between a pixel electrode and the source/drain electrodes, smoothly supplies hydrogen to the active layer and has high mobility, on-current characteristics, and threshold voltage characteristics. The TFT includes an active layer having a channel region and source/drain regions, a gate electrode supplying a signal to the channel region, source/drain electrodes respectively connected to the source/drain regions and including at least one of Ti, a Ti alloy, Ta, and a Ta alloy; and an insulating layer interposed between the source/drain electrodes and the active layer and including silicon nitride.Type: ApplicationFiled: July 3, 2008Publication date: December 4, 2008Inventor: Tae-Seong Kim -
Patent number: 7446392Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.Type: GrantFiled: November 19, 2007Date of Patent: November 4, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Teramoto
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Patent number: 7445971Abstract: The present invention provides a thin-film transistor that is formed by using a patterning method capable of forming a semiconductor channel layer in sub-micron order and a method for manufacturing thereof that provides a thin-film transistor with a larger area, and suitable for mass production. These objects are achieved by a thin-film transistor formed on a substrate 1 with a finely processed concavoconvex surface 2, in which a source electrode and a drain electrode are formed on adjacent convex portions of the concavoconvex surface 2, with a channel and a gate being formed on a concave area between the convex portions. A gate electrode 5, a gate insulating film 6 and a semiconductor channel layer 7 are laminated in this order on the concave area from the bottom surface of the concave portion toward the top surface.Type: GrantFiled: January 10, 2007Date of Patent: November 4, 2008Assignee: Dai Nippon Printing Co., Ltd.Inventors: Wataru Saito, Yudai Yamashita
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Patent number: 7442956Abstract: To provide an organic EL device capable of making uniform a dry speed of a liquid material coated in a display area. There is provided an organic EL device in which a plurality of pixels XR, XG, XB is arranged in an effective display area of a substrate and each of the pixels XR, XG, XB is provided with a first organic EL element having a functional film formed by a liquid phase method, wherein a dummy area D having a plurality of dummy pixels D1R, D1G, D1B, D2R, D2G, D2B for inspection of characteristics is provided around the effective display area and each dummy pixel is provided with a second organic EL element having a functional film formed using the same process as the functional film of the first organic EL element.Type: GrantFiled: March 30, 2005Date of Patent: October 28, 2008Assignee: Seiko Epson CorporationInventor: Tadashi Yamada
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Patent number: 7439107Abstract: When the laser light is irradiated with high output in the manufacturing process for a semiconductor device, an attenuator is heated and cause a deformation due to the laser light scattered in the attenuator. As a result, the attenuation ratio of the attenuator fluctuates, and it is difficult to process the substrate with the homogeneous irradiation energy. It is a problem of the present invention to provide a laser irradiation apparatus, a method of irradiating laser light and a method of manufacturing a semiconductor device, which can perform the laser irradiation effectively and homogeneously. In the present invention, the thermal energy generated in an attenuator is absorbed by means of cooling in order to keep the temperature of the attenuator constant. By cooling the attenuator so as to prevent the change of the attenuation ratio, the function of the attenuator is protected. In addition, the energy fluctuation of the laser light irradiated on the substrate is also prevented.Type: GrantFiled: December 24, 2003Date of Patent: October 21, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Koji Dairiki
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Publication number: 20080246034Abstract: A thin film transistor for a flat panel display, and more particularly to a thin film transistor for a flat panel display having a protrusion in a part of a gate electrode includes a substrate on which an insulating layer is deposited, a semiconductor layer, which is a layer having predetermined width and length on the insulating layer, provided with doping regions in a letter U shape and a channel region between the doping regions; a gate insulating layer formed on the semiconductor layer; a gate electrode formed on the gate insulating layer to traverse the doping region; and a protrusion, which is a part of the gate electrode, formed on the gate insulating layer to be opposed to the channel region.Type: ApplicationFiled: December 4, 2007Publication date: October 9, 2008Applicant: Samsung SDI Co., Ltd.Inventor: JONG-YUN KIM
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Patent number: 7432140Abstract: A thin film transistor includes a channel layer of a specific shape, a thermal gradient inducer body, a gate insulating film, a gate electrode and an interlayer insulating film, a source electrode and a drain electrode. The channel layer is formed on a substrate. The channel layer has a nucleation region and a crystal end. The thermal gradient inducer body partially circumscribes the channel layer. The gate insulating film is formed on the substrate, and the channel layer is at least partially covered with the gate insulating film. The gate electrode is formed on the gate insulating film. The interlayer insulating film is formed on the gate insulating film, and the gate electrode is at least partially covered with the interlayer insulating film. The source electrode and the drain electrode are formed on the interlayer insulating film, passed through the gate insulating film and the interlayer insulating film, and electrically connected to the channel layer.Type: GrantFiled: January 15, 2007Date of Patent: October 7, 2008Assignee: Chi Mei Optoelectronics Corp.Inventors: Chin-Lung Ting, Cheng-Chi Wang
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Patent number: 7432141Abstract: A method is disclosed to form a large-grain, lightly p-doped polysilicon film suitable for use as a channel region in thin film transistors. The film is preferably deposited lightly in situ doped with boron atoms by an LPCVD method at temperatures sufficiently low that the film is amorphous as deposited. After deposition, such a film contains an advantageous balance of boron, which promotes crystallization, and hydrogen, which retards crystallization. The film is then preferably crystallized by a low-temperature anneal at, for example, about 560 degrees for about twelve hours. Alternatively, crystallization may occur during an oxidation step performed, for example at about 825 degrees for about sixty seconds. The oxidation step forms a gate oxide for a thin film transistor device, for example a tunneling oxide for a SONOS memory thin film transistor device.Type: GrantFiled: September 8, 2004Date of Patent: October 7, 2008Assignee: SanDisk 3D LLCInventors: Shuo Gu, Sucheta Nallamothu
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Patent number: 7422935Abstract: It is an object of the present invention to manufacture a semiconductor device easily and to provide a semiconductor device whose cost is reduced. According to the present invention, a thin film integrated circuit provided over a base insulating layer can be prevented from scattering by providing a region where a substrate and the base insulating layer are attached firmly after removing a peeling layer. Therefore, a semiconductor device including a thin film integrated circuit can be manufactured easily. In addition, since a semiconductor device is manufactured by using a substrate except a silicon substrate according to the invention, a large number of semiconductor devices can be manufactured at a time and a semiconductor device whose cost is reduced can be provided.Type: GrantFiled: September 16, 2005Date of Patent: September 9, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki